293 lines
11 KiB
C
293 lines
11 KiB
C
/* ioc-cont.c: Intel IPC DBB adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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27 Jun 16 - Original file.
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NOTES:
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*/
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#include "system_defs.h" /* system header in system dir */
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//dbb status flag bits
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#define OBF 1
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#define IBF 2
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#define F0 4
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#define CD 8
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//system status bits
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#define IIM 16 //illegal interrupt mask
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#define IDT 32 //illegal data transfer
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#define IC 64 //illegal command
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#define DE 128 //device error
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//dbb command codes
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#define PACIFY 0x00 //Resets IOC and its devices
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#define ERESET 0x01 //Resets device-generated error (not used by standard devices)
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#define SYSTAT 0x02 //Returns subsystem status byte to master
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#define DSTAT 0x03 //Returns device status byte to master
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#define SRQDAK 0x04 //Enables input of device interrupt acknowledge mask from master
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#define SRQACK 0x05 //Clears IOC subsystem interrupt request
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#define SRQ 0x06 //Tests ability of IOC to forward an interrupt request to the master
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#define DECHO 0x07 //Tests ability of IOC to echo data byte sent by master
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#define CSMEM 0x08 //Requests IOC to checksum on-board ROM. Returns pass/fail
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#define TRAM 0x09 //Requests IOC to test on-board RAM. Returns pass/fail
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#define SINT 0x0A //Enables specified device interrupt from IOC
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#define CRTC 0x10 //Requests data byte output to the CRT monitor
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#define CRTS 0x11 //Returns CRT status byte to master
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#define KEYC 0x12 //Requests data byte input from the keyboard
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#define KSTC 0x13 //Returns keyboard status byte to master
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#define WPBC 0x15 //Enables input of first of five bytes that define current diskette operation
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#define WPBCC 0x16 //Enables input of each of four bytes that follow WPBC
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#define WDBC 0x17 //Enables input of diskette write bytes from master
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#define RDBC 0x19 //Enables output of diskette read bytes to master
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#define RRSTS 0x1B //Returns diskette result byte to master
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#define RDSTS 0x1C //Returns diskette device status byte to master
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#define ioc_cont_NAME "Intel IOC Controller"
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/* external globals */
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extern uint16 PCX;
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/* function prototypes */
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t_stat ioc_cont_cfg(uint16 base, uint16 devnum, uint8 dummy);
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t_stat ioc_cont_clr(void);
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t_stat ioc_cont_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat ioc_cont_reset (DEVICE *dptr);
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uint8 ioc_cont0(t_bool io, uint8 data, uint8 devnum); /* ioc_cont*/
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uint8 ioc_cont1(t_bool io, uint8 data, uint8 devnum); /* ioc_cont*/
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern uint8 unreg_dev(uint16);
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/* globals */
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static const char* ioc_cont_desc(DEVICE *dptr) {
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return ioc_cont_NAME;
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}
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uint8 dbb_stat;
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uint8 dbb_cmd;
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uint8 dbb_in;
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uint8 dbb_out;
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uint8 ioc_cont_baseport = -1; //base port
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UNIT ioc_cont_unit[] = {
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{ UDATA (0, 0, 0) }, /* ioc_cont*/
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};
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REG ioc_cont_reg[] = {
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{ HRDATA (CONTROL0, ioc_cont_unit[0].u3, 8) }, /* ioc_cont */
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{ NULL }
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};
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DEBTAB ioc_cont_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ NULL }
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};
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MTAB ioc_cont_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, ioc_cont_show_param, NULL,
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"show configured parameters for ioc_cont" },
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE ioc_cont_dev = {
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"IOC-CONT", //name
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ioc_cont_unit, //units
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ioc_cont_reg, //registers
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ioc_cont_mod, //modifiers
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1, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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ioc_cont_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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ioc_cont_debug, //debflags
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NULL, //msize
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NULL//&ioc_cont_desc //device description
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};
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// ioc_cont configuration
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t_stat ioc_cont_cfg(uint16 base, uint16 devnum, uint8 dummy)
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{
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sim_printf(" ioc-cont: installed at base port 0%02XH\n",
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base & BYTEMASK);
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ioc_cont_baseport = base & BYTEMASK;
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reg_dev(ioc_cont0, base, 0, 0);
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reg_dev(ioc_cont1, base + 1, 0, 0);
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return SCPE_OK;
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}
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t_stat ioc_cont_clr(void)
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{
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unreg_dev(ioc_cont_baseport);
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unreg_dev(ioc_cont_baseport + 1);
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ioc_cont_baseport = -1;
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return SCPE_OK;
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}
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// show configuration parameters
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t_stat ioc_cont_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "%s, Base port 0%04XH",
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((ioc_cont_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled",
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ioc_cont_baseport);
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat ioc_cont_reset(DEVICE *dptr)
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{
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dbb_stat = 0x00; /* clear DBB status */
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return SCPE_OK;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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/* IOC data port functions */
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uint8 ioc_cont0(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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dbb_stat &= ~OBF; //reset OBF flag
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return dbb_out;
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} else { /* write data port */
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dbb_in = data;
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dbb_stat |= IBF;
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return 0;
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}
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}
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/* IOC control port functions */
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uint8 ioc_cont1(t_bool io, uint8 data, uint8 devnum)
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{
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int temp;
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if (io == 0) { /* read status port */
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if ((dbb_stat & F0) && (dbb_stat & IBF)) {
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return dbb_stat;
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}
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if ((dbb_stat & F0) && (dbb_stat & OBF)) {
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temp = dbb_stat;
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dbb_stat &= ~OBF; //reset OBF flag
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return temp;
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}
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if (dbb_stat & F0) {
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return dbb_stat;
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}
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return dbb_stat;
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} else { /* write command port */
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dbb_stat |= F0;
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dbb_cmd = data;
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switch(dbb_cmd){
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case PACIFY: //reset IOC and its devices
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dbb_stat = 0;
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break;
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case ERESET: //reset device-generated error(not used by std devices)
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break;
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case SYSTAT: //returns subsystem status byte to master
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dbb_out = 0;
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dbb_stat |= OBF;
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dbb_stat &= ~CD;
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break;
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case DSTAT: //returns device status to master
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break;
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case SRQDAK: //enables input of device int ack mask from master
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break;
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case SRQACK: //clears IOC subsystem int req
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break;
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case SRQ: //tests ability of IOC to forward an int req to master
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break;
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case DECHO: //tests ability of IOC to echo data byte sent by master
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break;
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case CSMEM: //requests IOC to checksum onboard ROM
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break;
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case TRAM: //requests IOC to test onboard RAM
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break;
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case SINT: //enables specified device int from IOC
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break;
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case CRTC: //requests data byte output to CRT
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break;
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case CRTS: //return CRT status byte to master
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dbb_out = 0;
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dbb_stat |= F0;
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break;
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case KEYC: //request data byte from KBD
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break;
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case KSTC: //return KBD status byte to master
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dbb_out = 0;
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break;
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case WPBC: //enables input of first 5 bytes of IOPB
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break;
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case WPBCC: //enables input of 4 bytes that follow WPDC
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break;
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case WDBC: //enables input of diskette write bytes from master
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break;
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case RDBC: //enables output of diskette read bytes to master.
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break;
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case RRSTS: //returns diskette result byte to master
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break;
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case RDSTS: //returns diskette device status byte to master
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dbb_out = 0x80; //not ready
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dbb_stat |= IBF;
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break;
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default:
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sim_printf(" IOC-CONT: Unknown command %02X PCX=%04X\n", dbb_cmd, PCX);
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}
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return 0;
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}
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}
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/* end of ioc-cont.c */
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