This avoids a potential invalid pointer dereference when formatting the return value from sim_instr() if it is < SCPE_BASE but greater than the previously defined static array size.sizeof Update simh.doc to reflect this generic change.
1347 lines
48 KiB
C
1347 lines
48 KiB
C
/* pdp18b_sys.c: 18b PDP's simulator interface
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Copyright (c) 1993-2016, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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07-Mar-16 RMS Revised for dynamically allocated memory
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03-Mar-16 RMS Added DR15C support
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26-Feb-16 RMS Added support for -u modifier (UC15 and Unix v0)
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13-Sep-15 RMS Added DR15C instructions
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30-Oct-06 RMS Added infinite loop stop
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18-Oct-06 RMS Re-ordered device list
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02-Oct-06 RMS Added RDCLK instruction
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12-Jun-06 RMS Added Fiodec, Baudot display
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RMS Generalized LOAD to handle HRI, RIM, or BIN files
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22-Jul-05 RMS Removed AAS, error in V1 reference manual
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09-Jan-04 RMS Fixed instruction table errors
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18-Oct-03 RMS Added DECtape off reel message
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30-Jul-03 RMS Fixed FPM class mask
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18-Jul-03 RMS Added FP15 support
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02-Mar-03 RMS Split loaders apart for greater flexibility
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09-Feb-03 RMS Fixed bug in FMTASC (Hans Pufal)
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31-Jan-03 RMS Added support for RB09
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05-Oct-02 RMS Added variable device number support
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25-Jul-02 RMS Added PDP-4 DECtape support
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10-Feb-02 RMS Added PDP-7 DECtape IOT's
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03-Feb-02 RMS Fixed typo (Robert Alan Byer)
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17-Sep-01 RMS Removed multiconsole support
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27-May-01 RMS Added second Teletype support
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18-May-01 RMS Added PDP-9,-15 API IOT's
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12-May-01 RMS Fixed bug in RIM loaders
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14-Mar-01 RMS Added extension detection of RIM format tapes
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21-Jan-01 RMS Added DECtape support
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30-Nov-00 RMS Added PDP-9,-15 RIM/BIN loader format
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30-Oct-00 RMS Added support for examine to file
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27-Oct-98 RMS V2.4 load interface
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20-Oct-97 RMS Fixed endian dependence in RIM loader (Michael Somos)
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*/
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#include "pdp18b_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev;
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#if defined (PDP15)
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extern DEVICE fpp_dev;
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#endif
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extern DEVICE ptr_dev, ptp_dev;
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extern DEVICE tti_dev, tto_dev;
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extern UNIT tti_unit, tto_unit;
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extern DEVICE clk_dev;
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#if defined (TYPE62)
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extern DEVICE lp62_dev;
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#endif
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#if defined (TYPE647)
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extern DEVICE lp647_dev;
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#endif
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#if defined (LP09)
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extern DEVICE lp09_dev;
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#endif
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#if defined (LP15)
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extern DEVICE lp15_dev;
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#endif
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extern DEVICE dt_dev;
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#if defined (DRM)
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extern DEVICE drm_dev;
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#endif
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#if defined (RB)
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extern DEVICE rb_dev;
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#endif
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#if defined (RF)
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extern DEVICE rf_dev;
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#endif
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#if defined (RP)
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extern DEVICE rp_dev;
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#endif
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#if defined (MTA)
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extern DEVICE mt_dev;
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#endif
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#if defined (TTY1)
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extern DEVICE tti1_dev, tto1_dev;
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extern UNIT tti1_unit, tto1_unit;
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#endif
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#if defined (GRAPHICS2)
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extern DEVICE g2out_dev, g2in_dev;
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#endif
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#if defined (UC15)
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extern DEVICE dr15_dev;
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#endif
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#if defined (GRAPHICS2)
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extern DEVICE g2out_dev, g2in_dev;
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#endif
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#if defined (TYPE340)
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extern DEVICE dpy_dev;
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#endif
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extern UNIT cpu_unit;
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extern REG cpu_reg[];
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extern int32 *M;
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extern int32 memm;
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extern int32 PC;
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax number of words for examine
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sim_devices array of pointers to simulated devices
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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#if defined (PDP4)
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char sim_name[] = "PDP-4";
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#elif defined (PDP7)
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char sim_name[] = "PDP-7";
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#elif defined (PDP9)
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char sim_name[] = "PDP-9";
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#elif defined (PDP15)
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char sim_name[] = "PDP-15";
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#endif
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 3;
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DEVICE *sim_devices[] = {
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&cpu_dev,
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&clk_dev,
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#if defined (PDP15)
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&fpp_dev,
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#endif
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&ptr_dev,
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&ptp_dev,
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&tti_dev,
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&tto_dev,
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#if defined (TYPE62)
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&lp62_dev,
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#endif
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#if defined (TYPE647)
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&lp647_dev,
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#endif
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#if defined (LP09)
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&lp09_dev,
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#endif
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#if defined (LP15)
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&lp15_dev,
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#endif
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#if defined (DRM)
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&drm_dev,
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#endif
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#if defined (RB)
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&rb_dev,
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#endif
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#if defined (RF)
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&rf_dev,
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#endif
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#if defined (RP)
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&rp_dev,
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#endif
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&dt_dev,
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#if defined (MTA)
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&mt_dev,
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#endif
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#if defined (TTY1)
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&tti1_dev, &tto1_dev,
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#endif
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#if defined (UC15)
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&dr15_dev,
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#endif
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#if defined (GRAPHICS2)
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&g2out_dev, &g2in_dev,
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#endif
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#if defined (TYPE340)
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&dpy_dev,
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#endif
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NULL
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};
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const char *sim_stop_messages[SCPE_BASE] = {
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"Unknown error",
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"Undefined instruction",
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"HALT instruction",
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"Breakpoint",
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"Nested XCT's",
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"Invalid API interrupt",
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"Non-standard device number",
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"Memory management error",
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"FP15 instruction disabled",
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"DECtape off reel",
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"Infinite loop"
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};
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/* Binary loaders */
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int32 getword (FILE *fileref, int32 *hi)
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{
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int32 word, bits, st, ch;
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word = st = bits = 0;
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do {
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if ((ch = getc (fileref)) == EOF)
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return -1;
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if (ch & 0200) {
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word = (word << 6) | (ch & 077);
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bits = (bits << 1) | ((ch >> 6) & 1);
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st++;
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}
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} while (st < 3);
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if (hi != NULL)
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*hi = bits;
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return word;
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}
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/* PDP-4/PDP-7 RIM format loader
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Tape format
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dac addr
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data
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:
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dac addr
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data
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jmp addr or hlt
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*/
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t_stat rim_load_47 (FILE *fileref, const char *cptr)
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{
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int32 origin, val;
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if (*cptr != 0)
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return SCPE_2MARG;
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origin = 0200;
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for (;;) {
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if ((val = getword (fileref, NULL)) < 0)
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return SCPE_FMT;
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if ((val & 0760000) == 0040000) { /* DAC? */
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origin = val & 017777;
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if ((val = getword (fileref, NULL)) < 0)
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return SCPE_FMT;
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if (MEM_ADDR_OK (origin))
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M[origin++] = val;
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}
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else if ((val & 0760000) == OP_JMP) { /* JMP? */
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PC = ((origin - 1) & 060000) | (val & 017777);
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return SCPE_OK;
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}
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else if (val == OP_HLT) /* HLT? */
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break;
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else return SCPE_FMT; /* error */
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}
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return SCPE_OK; /* done */
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}
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/* PDP-7/9/15 hardware read-in format loader
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Tape format (read in address specified externally)
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data
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data
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word to execute (bit 1 of last character set)
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*/
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t_stat hri_load_7915 (FILE *fileref, CONST char *cptr)
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{
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int32 bits, origin, val;
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char gbuf[CBUFSIZE];
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t_stat r;
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if (*cptr != 0) { /* more input? */
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cptr = get_glyph (cptr, gbuf, 0); /* get origin */
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origin = get_uint (gbuf, 8, AMASK, &r);
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if (r != SCPE_OK)
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return r;
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if (*cptr != 0) /* no more */
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return SCPE_ARG;
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}
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else origin = 0200; /* default 200 */
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for (;;) { /* word loop */
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if ((val = getword (fileref, &bits)) < 0)
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return SCPE_FMT;
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if (bits & 1) { /* end of tape? */
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if ((val & 0760000) == OP_JMP) PC =
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((origin - 1) & 060000) | (val & 017777);
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else if (val != OP_HLT)
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return SCPE_FMT;
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break;
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}
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else if (MEM_ADDR_OK (origin))
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M[origin++] = val;
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}
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return SCPE_OK;
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}
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/* PDP-9/15 BIN format loader
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BIN format (starts after RIM bootstrap)
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block/ origin (>= 0)
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count
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checksum
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data
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:
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data
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block/
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:
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endblock/ origin (< 0)
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*/
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t_stat bin_load_915 (FILE *fileref, const char *cptr)
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{
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int32 i, val, bits, origin, count, cksum;
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if (*cptr != 0) /* no arguments */
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return SCPE_2MARG;
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do {
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val = getword (fileref, & bits); /* find end RIM */
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} while ((val >= 0) && ((bits & 1) == 0));
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if (val < 0) /* no RIM? rewind */
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rewind (fileref);
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for (;;) { /* block loop */
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if ((val = getword (fileref, NULL)) < 0)
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return SCPE_FMT;
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if (val & SIGN) {
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if (val != DMASK)
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PC = val & 077777;
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break;
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}
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cksum = origin = val; /* save origin */
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if ((val = getword (fileref, NULL)) < 0)
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return SCPE_FMT;
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cksum = cksum + val; /* add to cksum */
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count = (-val) & DMASK; /* save count */
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if ((val = getword (fileref, NULL)) < 0)
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return SCPE_FMT;
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cksum = cksum + val; /* add to cksum */
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for (i = 0; i < count; i++) {
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if ((val = getword (fileref, NULL)) < 0)
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return SCPE_FMT;
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cksum = cksum + val;
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if (MEM_ADDR_OK (origin))
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M[origin++] = val;
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}
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if ((cksum & DMASK) != 0)
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return SCPE_CSUM;
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}
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return SCPE_OK;
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}
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/* Binary loader, all formats */
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t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
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{
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if (flag != 0)
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return SCPE_NOFNC;
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if (sim_switches & SWMASK ('S')) /* RIM format? */
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return rim_load_47 (fileref, cptr);
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if (sim_switches & SWMASK ('R')) /* HRI format? */
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return hri_load_7915 (fileref, cptr);
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if (!(sim_switches & SWMASK ('B')) && /* .rim extension? */
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match_ext (fnam, "RIM")) {
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int32 val, bits;
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do { /* look for HRI flag */
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val = getword (fileref, &bits);
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} while ((val >= 0) && ((bits & 1) == 0));
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rewind (fileref); /* rewind file */
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if (val < 0) /* eof reached? */
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return rim_load_47 (fileref, cptr);
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return hri_load_7915 (fileref, cptr); /* no, HRI */
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}
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return bin_load_915 (fileref, cptr); /* must be BIN */
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}
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/* Symbol tables */
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#define I_V_FL 18 /* inst class */
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#define I_M_FL 017 /* class mask */
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#define I_V_DC 22 /* default count */
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#define I_V_NPN 0 /* no operand */
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#define I_V_NPI 1 /* no operand IOT */
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#define I_V_IOT 2 /* IOT */
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#define I_V_MRF 3 /* memory reference */
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#define I_V_OPR 4 /* OPR */
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#define I_V_LAW 5 /* LAW */
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#define I_V_XR 6 /* index */
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#define I_V_XR9 7 /* index literal */
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#define I_V_EST 8 /* EAE setup */
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#define I_V_ESH 9 /* EAE shift */
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#define I_V_EMD 10 /* EAE mul-div */
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#define I_V_FPM 11 /* FP15 mem ref */
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#define I_V_FPI 12 /* FP15 indirect */
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#define I_V_FPN 13 /* FP15 no operand */
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#define I_NPN (I_V_NPN << I_V_FL)
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#define I_NPI (I_V_NPI << I_V_FL)
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#define I_IOT (I_V_IOT << I_V_FL)
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#define I_MRF (I_V_MRF << I_V_FL)
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#define I_OPR (I_V_OPR << I_V_FL)
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#define I_LAW (I_V_LAW << I_V_FL)
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#define I_XR (I_V_XR << I_V_FL)
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#define I_XR9 (I_V_XR9 << I_V_FL)
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#define I_EST (I_V_EST << I_V_FL)
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#define I_ESH (I_V_ESH << I_V_FL)
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#define I_EMD (I_V_EMD << I_V_FL)
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#define I_FPM (I_V_FPM << I_V_FL)
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#define I_FPI (I_V_FPI << I_V_FL)
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#define I_FPN (I_V_FPN << I_V_FL)
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#define MD(x) ((I_EMD) + ((x) << I_V_DC))
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static const int32 masks[] = {
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0777777, 0777767, 0770000, 0760000,
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0763730, 0760000, 0777000, 0777000,
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0740700, 0760700, 0777700, 0777777,
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0777777, 0777777
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};
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/* If both NPN (clear AC) and NPI versions of an IOT are defined,
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the NPN version must come first */
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static const char *opcode[] = {
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"CAL", "DAC", "JMS", "DZM", /* mem refs */
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"LAC", "XOR", "ADD", "TAD",
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"XCT", "ISZ", "AND", "SAD",
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"JMP",
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#if defined (PDP9) || defined (PDP15) /* mem ref ind */
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"CAL*", "DAC*", "JMS*", "DZM*", /* normal */
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"LAC*", "XOR*", "ADD*", "TAD*",
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"XCT*", "ISZ*", "AND*", "SAD*",
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"JMP*",
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#else
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"CAL I", "DAC I", "JMS I", "DZM I", /* decode only */
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"LAC I", "XOR I", "ADD I", "TAD I",
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"XCT I", "ISZ I", "AND I", "SAD I",
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"JMP I",
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#endif
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"LAW", /* LAW */
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"LACQ", "LACS", "ABS", "GSM", "LMQ", /* EAE */
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"MUL", "MULS", "DIV", "DIVS",
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"IDIV", "IDIVS", "FRDIV", "FRDIVS",
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"NORM", "NORMS",
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"MUY", "LLK MUY", "DVI", "LLK DVI",
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"NMI", "NMIS", "LRS", "LRSS",
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"LLS", "LLSS", "ALS", "ALSS",
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"EAE-setup", "EAE", /* setup, general */
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"CLSF", "IOF", "ION", "CLOF", "CLON", /* standard IO devs */
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"RSF", "RRB", "RCF", "RSA", "RSB",
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"PSF", "PCF", "PSA", "PSB", "PLS",
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"KSF", "KRB", "KCF", "IORS", "IOOS",
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"TSF", "TCF", "TPC", "TLS",
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"IDVE", "IDRA", "IDRS", "IDRA",
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"IDSI", "IDCA", "IDRD", "IDLA", "IDRD",
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"IDSP", "IDRC", "IDCF", "IDRC",
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"IDHE", "IDSC", "IDRP", "IDSC", "IDRP",
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#if defined (TYPE62) /* Type 62 */
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"LPSF", "LPCF", "LPLD", "LPSE",
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"LSSF", "LSCF", "LSPR",
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#endif
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#if defined (TYPE647) /* Type 647 */
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"LPSF", "LPCB", "LPCD", "LPCD", "LPCD",
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"LPL2", "LPLD", "LPL1",
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"LPEF", "LPCF", "LPCF", "LPCF", "LPCF",
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"LPPB", "LPLS", "LPPS",
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#endif
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#if defined (LP09)
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"LSDF", "LSEF", "LSCF", "LPLD",
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"LIOF", "LION",
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#endif
|
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#if defined (LP15) /* LP15 */
|
|
"LPSF", "LPPM", "LPP1", "LPDI",
|
|
"LPRS", "LPOS", "LPEI", "LPCD", "LPCF",
|
|
#endif
|
|
#if defined (DRM) /* drum */
|
|
"DRLR", "DRLW", "DRSS", "DRCS",
|
|
"DRSF", "DRSN", "DRCF",
|
|
"DRLCRD", "DRLCWR", "DRLBLK", "DRCONT",
|
|
"DRSF", "DRSOK", "DRCF",
|
|
#endif
|
|
#if defined (RB) /* RB09 */
|
|
"DBCF", "DBRD", "DBLD",
|
|
"DBSF", "DBRS", "DBLW",
|
|
"DBCS", "DBLM", "DBLS",
|
|
#endif
|
|
#if defined (RF) /* RF09 */
|
|
"DSSF", "DSCC", "DSCF",
|
|
"DRBR", "DRAL", "DSFX", "DRAH",
|
|
"DLBR", "DLAL", "DSCN", "DLAH",
|
|
"DLOK", "DSCD", "DSRS",
|
|
"DGHS", "DGSS",
|
|
#endif
|
|
#if defined (RP)
|
|
"DPSF", "DPSA", "DPSJ", "DPSE",
|
|
"DPRSA", "DPOSA", "DPRSB", "DPOSB",
|
|
"DPRM", "DPOM",
|
|
"DPLA", "DPCS", "DPCA", "DPWC",
|
|
"DPLM", "DPEM", "DPSN",
|
|
"DPRU", "DPOU", "DPRA", "DPOA",
|
|
"DPRC", "DPOC", "DPRW", "DPOW",
|
|
"DPCF", "DPLZ", "DPCN", "DPLO", "DPLF",
|
|
#endif
|
|
#if defined (MTA) /* TC59 */
|
|
"MTTR", "MTCR", "MTSF", "MTRC", "MTAF",
|
|
"MTRS", "MTGO", "MTCM", "MTLC",
|
|
#endif
|
|
#if defined (TYPE550) /* Type 550 */
|
|
"MMDF", "MMEF", "MMRD", "MMWR",
|
|
"MMBF", "MMRS", "MMLC", "MMSE",
|
|
#elif defined (TC02) /* TC02/TC15 */
|
|
"DTCA", "DTRA", "DTXA", "DTLA",
|
|
"DTEF", "DTRB", "DTDF",
|
|
#endif
|
|
#if defined (TTY1)
|
|
"KSF1", "KRB1",
|
|
"TSF1", "TCF1", "TLS1", "TCF1!TLS1",
|
|
#endif
|
|
#if defined (UC15) /* DR15C */
|
|
"SIOA", "CIOD", "LIOR",
|
|
"RDRS", "LDRS",
|
|
"SAPI0", "SAPI1", "SAPI2", "SAPI3",
|
|
"CAPI0", "CAPI1", "CAPI2", "CAPI3",
|
|
#endif
|
|
#if defined (PDP7)
|
|
"ITON", "TTS", "SKP7", "CAF",
|
|
"SEM", "EEM", "EMIR", "LEM",
|
|
#endif
|
|
#if defined (PDP9)
|
|
"SKP7", "SEM", "EEM", "LEM",
|
|
"LPDI", "LPEI",
|
|
#endif
|
|
#if defined (PDP15)
|
|
"SPCO", "SKP15", "RES",
|
|
"SBA", "DBA", "EBA",
|
|
"RDMM", "ORMM", "LDMM", "MPLR",
|
|
"ENB", "INH",
|
|
"RDCLK","MPRC", "IPFH",
|
|
"PAX", "PAL", "AAC", "PXA",
|
|
"AXS", "PXL", "PLA", "PLX",
|
|
"CLAC","CLX", "CLLR", "AXR",
|
|
|
|
"FPT", /* FP15 */
|
|
"ISB", "ESB", /* mem ref */
|
|
"FSB", "URFSB", "UNFSB", "UUFSB",
|
|
"DSB", "URDSB", "UNDSB", "UUDSB",
|
|
"IRS", "ERS",
|
|
"FRS", "URFRS", "UNFRS", "UUFRS",
|
|
"DRS", "URDRS", "UNDRS", "UUDRS",
|
|
"IMP", "EMP",
|
|
"FMP", "URFMP", "UNFMP", "UUFMP",
|
|
"DMP", "URDMP", "UNDMP", "UUDMP",
|
|
"IDV", "EDV",
|
|
"FDV", "URFDV", "UNFDV", "UUFDV",
|
|
"DDV", "URDDV", "UNDDV", "UUDDV",
|
|
"IRD", "ERD",
|
|
"FRD", "URFRD", "UNFRD", "UUFRD",
|
|
"DRD", "URDRD", "UNDRD", "UUDRD",
|
|
"ILD", "ELD",
|
|
"FLD", "UNFLD", "DLD", "UNDLD",
|
|
"IST", "EST",
|
|
"FST", "URFST", "UNFST", "UUFST",
|
|
"DST", "UNDST",
|
|
"ILF", "UNILF", "ELF", "UNELF",
|
|
"FLX", "URFLX", "DLX", "URDLX",
|
|
"ILQ", "ELQ",
|
|
"FLQ", "UNFLQ", "DLQ", "UNDLQ",
|
|
"LJE", "SJE",
|
|
"IAD", "EAD",
|
|
"FAD", "URFAD", "UNFAD", "UUFAD",
|
|
"DAD", "URDAD", "UNDAD", "UUDAD",
|
|
"BZA", "BMA", "BLE", "BPA",
|
|
"BRU", "BNA", "BAC",
|
|
"ISB*", "ESB*", /* indirect */
|
|
"FSB*", "URFSB*", "UNFSB*", "UUFSB*",
|
|
"DSB*", "URDSB*", "UNDSB*", "UUDSB*",
|
|
"IRS*", "ERS*",
|
|
"FRS*", "URFRS*", "UNFRS*", "UUFRS*",
|
|
"DRS*", "URDRS*", "UNDRS*", "UUDRS*",
|
|
"IMP*", "EMP*",
|
|
"FMP*", "URFMP*", "UNFMP*", "UUFMP*",
|
|
"DMP*", "URDMP*", "UNDMP*", "UUDMP*",
|
|
"IDV*", "EDV*",
|
|
"FDV*", "URFDV*", "UNFDV*", "UUFDV*",
|
|
"DDV*", "URDDV*", "UNDDV*", "UUDDV*",
|
|
"IRD*", "ERD",
|
|
"FRD*", "URFRD*", "UNFRD*", "UUFRD*",
|
|
"DRD*", "URDRD*", "UNDRD*", "UUDRD*",
|
|
"ILD*", "ELD",
|
|
"FLD*", "UNFLD*", "DLD*", "UNDLD*",
|
|
"IST*", "EST",
|
|
"FST*", "URFST*", "UNFST*", "UUFST*",
|
|
"DST*", "UNDST*",
|
|
"ILF*", "UNILF*", "ELF*", "UNELF*",
|
|
"FLX*", "URFLX*", "DLX*", "URDLX*",
|
|
"ILQ*", "ELQ*",
|
|
"FLQ*", "UNFLQ*", "DLQ*", "UNDLQ*",
|
|
"LJE*", "SJE*",
|
|
"IAD*", "EAD*",
|
|
"FAD*", "URFAD*", "UNFAD*", "UUFAD*",
|
|
"DAD*", "URDAD*", "UNDAD*", "UUDAD*",
|
|
|
|
"FLA", "UNFLA", "FXA", "URFXA", /* no operand */
|
|
"SWQ", "UNSWQ", "FZR",
|
|
"FAB", "FNG", "FCM", "FNM",
|
|
#endif
|
|
#if defined (PDP9) || defined (PDP15)
|
|
"MPSK", "MPSNE", "MPCV", "MPEU",
|
|
"MPLD", "MPCNE", "PFSF",
|
|
"TTS", "CAF", "DBK", "DBR",
|
|
"SPI", "RPL", "ISA",
|
|
#endif
|
|
"IOT", /* general */
|
|
|
|
"NOP", "STL", "RCL", "RCR",
|
|
"CLC", "LAS", "GLK",
|
|
"OPR", "SMA", "SZA", "SZA SMA",
|
|
"SNL", "SNL SMA", "SNL SZA", "SNL SZA SMA",
|
|
"SKP", "SPA", "SNA", "SNA SPA",
|
|
"SZL", "SZL SPA", "SZL SNA", "SZL SZA SPA",
|
|
"RAL", "SMA RAL", "SZA RAL", "SZA SMA RAL",
|
|
"SNL RAL", "SNL SMA RAL", "SNL SZA RAL", "SNL SZA SMA RAL",
|
|
"SKP RAL", "SPA RAL", "SNA RAL", "SNA SPA RAL",
|
|
"SZL RAL", "SZL SPA RAL", "SZL SNA RAL", "SZL SZA SPA RAL",
|
|
"RAR", "SMA RAR", "SZA RAR", "SZA SMA RAR",
|
|
"SNL RAR", "SNL SMA RAR", "SNL SZA RAR", "SNL SZA SMA RAR",
|
|
"SKP RAR", "SPA RAR", "SNA RAR", "SNA SPA RAR",
|
|
"SZL RAR", "SZL SPA RAR", "SZL SNA RAR", "SZL SZA SPA RAR",
|
|
#if defined (PDP15)
|
|
"IAC", "SMA IAC", "SZA IAC", "SZA SMA IAC",
|
|
"SNL IAC", "SNL SMA IAC", "SNL SZA IAC", "SNL SZA SMA IAC",
|
|
"SKP IAC", "SPA IAC", "SNA IAC", "SNA SPA IAC",
|
|
"SZL IAC", "SZL SPA IAC", "SZL SNA IAC", "SZL SZA SPA IAC",
|
|
#else
|
|
"RAL RAR", "SMA RAL RAR", "SZA RAL RAR", "SZA SMA RAL RAR",
|
|
"SNL RAL RAR", "SNL SMA RAL RAR", "SNL SZA RAL RAR", "SNL SZA SMA RAL RAR",
|
|
"SKP RAL RAR", "SPA RAL RAR", "SNA RAL RAR", "SNA SPA RAL RAR",
|
|
"SZL RAL RAR", "SZL SPA RAL RAR", "SZL SNA RAL RAR", "SZL SZA SPA RAL RAR",
|
|
#endif
|
|
"RTWO", "SMA RTWO", "SZA RTWO", "SZA SMA RTWO",
|
|
"SNL RTWO", "SNL SMA RTWO", "SNL SZA RTWO", "SNL SZA SMA RTWO",
|
|
"SKP RTWO", "SPA RTWO", "SNA RTWO", "SNA SPA RTWO",
|
|
"SZL RTWO", "SZL SPA RTWO", "SZL SNA RTWO", "SZL SZA SPA RTWO",
|
|
"RTL", "SMA RTL", "SZA RTL", "SZA SMA RTL",
|
|
"SNL RTL", "SNL SMA RTL", "SNL SZA RTL", "SNL SZA SMA RTL",
|
|
"SKP RTL", "SPA RTL", "SNA RTL", "SNA SPA RTL",
|
|
"SZL RTL", "SZL SPA RTL", "SZL SNA RTL", "SZL SZA SPA RTL",
|
|
"RTR", "SMA RTR", "SZA RTR", "SZA SMA RTR",
|
|
"SNL RTR", "SNL SMA RTR", "SNL SZA RTR", "SNL SZA SMA RTR",
|
|
"SKP RTR", "SPA RTR", "SNA RTR", "SNA SPA RTR",
|
|
"SZL RTR", "SZL SPA RTR", "SZL SNA RTR", "SZL SZA SPA RTR",
|
|
#if defined (PDP15)
|
|
"BSW", "SMA BSW", "SZA BSW", "SZA SMA BSW",
|
|
"SNL BSW", "SNL SMA BSW", "SNL SZA BSW", "SNL SZA SMA BSW",
|
|
"SKP BSW", "SPA BSW", "SNA BSW", "SNA SPA BSW",
|
|
"SZL BSW", "SZL SPA BSW", "SZL SNA BSW", "SZL SZA SPA BSW",
|
|
#else
|
|
"RTL RTR", "SMA RTL RTR", "SZA RTL RTR", "SZA SMA RTL RTR",
|
|
"SNL RTL RTR", "SNL SMA RTL RTR", "SNL SZA RTL RTR", "SNL SZA SMA RTL RTR",
|
|
"SKP RTL RTR", "SPA RTL RTR", "SNA RTL RTR", "SNA SPA RTL RTR",
|
|
"SZL RTL RTR", "SZL SPA RTL RTR", "SZL SNA RTL RTR", "SZL SZA SPA RTL RTR",
|
|
#endif
|
|
|
|
"LLK", "CLQ", "LSN", "OACQ", "ECLA", /* encode only masks */
|
|
"CMQ", "OMQ", "OSC",
|
|
"CLA", "CLL", "CML", "CMA",
|
|
"OAS", "HLT",
|
|
NULL
|
|
};
|
|
|
|
static const int32 opc_val[] = {
|
|
0000000+I_MRF, 0040000+I_MRF, 0100000+I_MRF, 0140000+I_MRF,
|
|
0200000+I_MRF, 0240000+I_MRF, 0300000+I_MRF, 0340000+I_MRF,
|
|
0400000+I_MRF, 0440000+I_MRF, 0500000+I_MRF, 0540000+I_MRF,
|
|
0600000+I_MRF,
|
|
0020000+I_MRF, 0060000+I_MRF, 0120000+I_MRF, 0160000+I_MRF,
|
|
0220000+I_MRF, 0260000+I_MRF, 0320000+I_MRF, 0360000+I_MRF,
|
|
0420000+I_MRF, 0460000+I_MRF, 0520000+I_MRF, 0560000+I_MRF,
|
|
0620000+I_MRF,
|
|
|
|
0760000+I_LAW,
|
|
|
|
0641002+I_NPN, 0641001+I_NPN, 0644000+I_NPN, 0664000+I_NPN, 0652000+I_NPN,
|
|
0653100+MD(022), 0657100+MD(022), 0640300+MD(023), 0644300+MD(023),
|
|
0653300+MD(023), 0657300+MD(023), 0650300+MD(023), 0654300+MD(023),
|
|
0640400+MD(044), 0660400+MD(044),
|
|
0640100+I_ESH, 0660100+I_ESH, 0640300+I_ESH, 0660300+I_ESH,
|
|
0640400+I_ESH, 0660400+I_ESH, 0640500+I_ESH, 0660500+I_ESH,
|
|
0640600+I_ESH, 0660600+I_ESH, 0640700+I_ESH, 0660700+I_ESH,
|
|
0640000+I_EST, 0640000+I_IOT,
|
|
|
|
0700001+I_NPI, 0700002+I_NPI, 0700042+I_NPI, 0700004+I_NPI, 0700044+I_NPI,
|
|
0700101+I_NPI, 0700112+I_NPN, 0700102+I_NPI, 0700104+I_NPI, 0700144+I_NPI,
|
|
0700201+I_NPI, 0700202+I_NPI, 0700204+I_NPI, 0700244+I_NPI, 0700206+I_NPI,
|
|
0700301+I_NPI, 0700312+I_NPN, 0700302+I_NPI, 0700314+I_NPN, 0700304+I_NPI,
|
|
0700401+I_NPI, 0700402+I_NPI, 0700404+I_NPI, 0700406+I_NPI,
|
|
0700501+I_NPI, 0700502+I_NPI, 0700504+I_NPI, 0700512+I_NPI,
|
|
0700601+I_NPI, 0700602+I_NPI, 0700604+I_NPI, 0700606+I_NPI, 0700614+I_NPI,
|
|
0700701+I_NPI, 0700702+I_NPI, 0700704+I_NPI, 0700712+I_NPI,
|
|
0701001+I_NPI, 0701002+I_NPI, 0701004+I_NPI, 0701012+I_NPI, 0701014+I_NPI,
|
|
#if defined (TYPE62)
|
|
0706501+I_NPI, 0706502+I_NPI, 0706542+I_NPI, 0706506+I_NPI,
|
|
0706601+I_NPI, 0706602+I_NPI, 0706606+I_NPI,
|
|
#endif
|
|
#if defined (TYPE647)
|
|
0706501+I_NPI, 0706502+I_NPI, 0706522+I_NPI, 0706542+I_NPI, 0706562+I_NPI,
|
|
0706526+I_NPI, 0706546+I_NPI, 0706566+I_NPI,
|
|
0706601+I_NPI, 0706602+I_NPI, 0706622+I_NPI, 0706642+I_NPI, 0706662+I_NPI,
|
|
0706606+I_NPI, 0706626+I_NPI, 0706646+I_NPI,
|
|
#endif
|
|
#if defined (LP09)
|
|
0706601+I_NPI, 0706621+I_NPI, 0706602+I_NPI, 0706622+I_NPI,
|
|
0706604+I_NPI, 0706644+I_NPI,
|
|
#endif
|
|
#if defined (LP15)
|
|
0706501+I_NPI, 0706521+I_NPI, 0706541+I_NPI, 0706561+I_NPI,
|
|
0706552+I_NPN, 0706542+I_NPI, 0706544+I_NPI, 0706621+I_NPI, 0706641+I_NPI,
|
|
#endif
|
|
#if defined (DRM)
|
|
0706006+I_NPI, 0706046+I_NPI, 0706106+I_NPI, 0706204+I_NPI,
|
|
0706101+I_NPI, 0706201+I_NPI, 0706102+I_NPI,
|
|
0706006+I_NPI, 0706046+I_NPI, 0706106+I_NPI, 0706204+I_NPI,
|
|
0706101+I_NPI, 0706201+I_NPI, 0706102+I_NPI,
|
|
#endif
|
|
#if defined (RB)
|
|
0707101+I_NPI, 0707112+I_NPN, 0707104+I_NPI,
|
|
0707121+I_NPI, 0707132+I_NPN, 0707124+I_NPI,
|
|
0707141+I_NPI, 0707142+I_NPI, 0707144+I_NPI,
|
|
#endif
|
|
#if defined (RF)
|
|
0707001+I_NPI, 0707021+I_NPI, 0707041+I_NPI,
|
|
0707002+I_NPI, 0707022+I_NPI, 0707042+I_NPI, 0707062+I_NPI,
|
|
0707004+I_NPI, 0707024+I_NPI, 0707044+I_NPI, 0707064+I_NPI,
|
|
0707202+I_NPI, 0707242+I_NPI, 0707262+I_NPI,
|
|
0707204+I_NPI, 0707224+I_NPI,
|
|
#endif
|
|
#if defined (RP)
|
|
0706301+I_NPI, 0706321+I_NPI, 0706341+I_NPI, 0706361+I_NPI,
|
|
0706312+I_NPN, 0706302+I_NPI, 0706332+I_NPN, 0706322+I_NPI,
|
|
0706352+I_NPN, 0706342+I_NPI,
|
|
0706304+I_NPI, 0706324+I_NPI, 0706344+I_NPI, 0706364+I_NPI,
|
|
0706411+I_NPN, 0706401+I_NPI, 0706421+I_NPI,
|
|
0706412+I_NPN, 0706402+I_NPI, 0706432+I_NPN, 0706422+I_NPI,
|
|
0706452+I_NPN, 0706442+I_NPI, 0706472+I_NPN, 0706462+I_NPI,
|
|
0706404+I_NPI, 0706424+I_NPI, 0706454+I_NPN, 0706444+I_NPI, 0706464+I_NPI,
|
|
#endif
|
|
#if defined (MTA)
|
|
0707301+I_NPI, 0707321+I_NPI, 0707341+I_NPI, 0707312+I_NPN, 0707322+I_NPI,
|
|
0707352+I_NPN, 0707304+I_NPI, 0707324+I_NPI, 0707326+I_NPI,
|
|
#endif
|
|
#if defined (TYPE550) /* Type 550 */
|
|
0707501+I_NPI, 0707541+I_NPI, 0707512+I_NPN, 0707504+I_NPI,
|
|
0707601+I_NPI, 0707612+I_NPN, 0707604+I_NPI, 0707644+I_NPI,
|
|
#elif defined (TC02) /* TC02/TC15 */
|
|
0707541+I_NPI, 0707552+I_NPN, 0707544+I_NPI, 0707545+I_NPI,
|
|
0707561+I_NPI, 0707572+I_NPN, 0707601+I_NPI,
|
|
#endif
|
|
#if defined (TTY1)
|
|
0704101+I_NPI, 0704112+I_NPN,
|
|
0704001+I_NPI, 0704002+I_NPI, 0704004+I_NPI, 0704006+I_NPI,
|
|
#endif
|
|
#if defined (UC15)
|
|
0706001+I_NPI, 0706002+I_NPI, 0706006+I_NPI,
|
|
0706112+I_NPN, 0706122+I_NPI,
|
|
0706101+I_NPI, 0706121+I_NPI, 0706141+I_NPI, 0706161+I_NPI,
|
|
0706104+I_NPI, 0706124+I_NPI, 0706144+I_NPI, 0706164+I_NPI,
|
|
#endif
|
|
#if defined (PDP7)
|
|
0703201+I_NPI, 0703301+I_NPI, 0703341+I_NPI, 0703302+I_NPI,
|
|
0707701+I_NPI, 0707702+I_NPI, 0707742+I_NPI, 0707704+I_NPI,
|
|
#endif
|
|
#if defined (PDP9)
|
|
0703341+I_NPI, 0707701+I_NPI, 0707702+I_NPI, 0707704+I_NPI,
|
|
0706504+I_NPI, 0706604+I_NPI,
|
|
#endif
|
|
#if defined (PDP15)
|
|
0703341+I_NPI, 0707741+I_NPI, 0707742+I_NPI,
|
|
0707761+I_NPI, 0707762+I_NPI, 0707764+I_NPI,
|
|
0700032+I_NPN, 0700022+I_NPI, 0700024+I_NPI, 0701724+I_NPI,
|
|
0705521+I_NPI, 0705522+I_NPI,
|
|
0701772+I_NPN, 0701762+I_NPI, 0701764+I_NPI,
|
|
0721000+I_XR, 0722000+I_XR, 0723000+I_XR9, 0724000+I_XR,
|
|
0725000+I_XR9, 0726000+I_XR, 0730000+I_XR, 0731000+I_XR,
|
|
0734000+I_XR, 0735000+I_XR, 0736000+I_XR, 0737000+I_XR9,
|
|
|
|
0710314+I_FPN,
|
|
0710400+I_FPM, 0710500+I_FPM,
|
|
0710440+I_FPM, 0710450+I_FPM, 0710460+I_FPM, 0710470+I_FPM,
|
|
0710540+I_FPM, 0710550+I_FPM, 0710560+I_FPM, 0710570+I_FPM,
|
|
0711000+I_FPM, 0711100+I_FPM,
|
|
0711040+I_FPM, 0711050+I_FPM, 0711060+I_FPM, 0711070+I_FPM,
|
|
0711140+I_FPM, 0711150+I_FPM, 0711160+I_FPM, 0711170+I_FPM,
|
|
0711400+I_FPM, 0711500+I_FPM,
|
|
0711440+I_FPM, 0711450+I_FPM, 0711460+I_FPM, 0711470+I_FPM,
|
|
0711540+I_FPM, 0711550+I_FPM, 0711560+I_FPM, 0711570+I_FPM,
|
|
0712000+I_FPM, 0712100+I_FPM,
|
|
0712040+I_FPM, 0712050+I_FPM, 0712060+I_FPM, 0712070+I_FPM,
|
|
0712140+I_FPM, 0712150+I_FPM, 0712160+I_FPM, 0712170+I_FPM,
|
|
0712400+I_FPM, 0712500+I_FPM,
|
|
0712440+I_FPM, 0712450+I_FPM, 0712460+I_FPM, 0712470+I_FPM,
|
|
0712540+I_FPM, 0712550+I_FPM, 0712560+I_FPM, 0712570+I_FPM,
|
|
0713000+I_FPM, 0713100+I_FPM,
|
|
0713050+I_FPM, 0713070+I_FPM, 0713150+I_FPM, 0713170+I_FPM,
|
|
0713600+I_FPM, 0713700+I_FPM,
|
|
0713640+I_FPM, 0713650+I_FPM, 0713660+I_FPM, 0713670+I_FPM,
|
|
0713750+I_FPM, 0713770+I_FPM,
|
|
0714010+I_FPM, 0714030+I_FPM, 0714110+I_FPM, 0714130+I_FPM,
|
|
0714460+I_FPM, 0714470+I_FPM, 0714560+I_FPM, 0714570+I_FPM,
|
|
0715000+I_FPM, 0715100+I_FPM,
|
|
0715050+I_FPM, 0715070+I_FPM, 0715150+I_FPM, 0715170+I_FPM,
|
|
0715400+I_FPM, 0715600+I_FPM,
|
|
0716000+I_FPM, 0716100+I_FPM,
|
|
0716040+I_FPM, 0716050+I_FPM, 0716060+I_FPM, 0716070+I_FPM,
|
|
0716140+I_FPM, 0716150+I_FPM, 0716160+I_FPM, 0716170+I_FPM,
|
|
0716601+I_FPM, 0716602+I_FPM, 0716603+I_FPM,
|
|
0716604+I_FPM, 0716606+I_FPM, 0716610+I_FPM, 0716620+I_FPM,
|
|
0710400+I_FPI, 0710500+I_FPI, /* indirect */
|
|
0710440+I_FPI, 0710450+I_FPI, 0710460+I_FPI, 0710470+I_FPI,
|
|
0710540+I_FPI, 0710550+I_FPI, 0710560+I_FPI, 0710570+I_FPI,
|
|
0711000+I_FPI, 0711100+I_FPI,
|
|
0711040+I_FPI, 0711050+I_FPI, 0711060+I_FPI, 0711070+I_FPI,
|
|
0711140+I_FPI, 0711150+I_FPI, 0711160+I_FPI, 0711170+I_FPI,
|
|
0711400+I_FPI, 0711500+I_FPI,
|
|
0711440+I_FPI, 0711450+I_FPI, 0711460+I_FPI, 0711470+I_FPI,
|
|
0711540+I_FPI, 0711550+I_FPI, 0711560+I_FPI, 0711570+I_FPI,
|
|
0712000+I_FPI, 0712100+I_FPI,
|
|
0712040+I_FPI, 0712050+I_FPI, 0712060+I_FPI, 0712070+I_FPI,
|
|
0712140+I_FPI, 0712150+I_FPI, 0712160+I_FPI, 0712170+I_FPI,
|
|
0712400+I_FPI, 0712500+I_FPI,
|
|
0712440+I_FPI, 0712450+I_FPI, 0712460+I_FPI, 0712470+I_FPI,
|
|
0712540+I_FPI, 0712550+I_FPI, 0712560+I_FPI, 0712570+I_FPI,
|
|
0713000+I_FPI, 0713100+I_FPI,
|
|
0713050+I_FPI, 0713070+I_FPI, 0713150+I_FPI, 0713170+I_FPI,
|
|
0713600+I_FPI, 0713700+I_FPI,
|
|
0713640+I_FPI, 0713650+I_FPI, 0713660+I_FPI, 0713670+I_FPI,
|
|
0713750+I_FPI, 0713770+I_FPI,
|
|
0714010+I_FPI, 0714030+I_FPI, 0714110+I_FPI, 0714130+I_FPI,
|
|
0714460+I_FPI, 0714470+I_FPI, 0714560+I_FPI, 0714570+I_FPI,
|
|
0715000+I_FPI, 0715100+I_FPI,
|
|
0715050+I_FPI, 0715070+I_FPI, 0715150+I_FPI, 0715170+I_FPI,
|
|
0715400+I_FPI, 0715600+I_FPI,
|
|
0716000+I_FPI, 0716100+I_FPI,
|
|
0716040+I_FPI, 0716050+I_FPI, 0716060+I_FPI, 0716070+I_FPI,
|
|
0716140+I_FPI, 0716150+I_FPI, 0716160+I_FPI, 0716170+I_FPI,
|
|
0714210+I_FPN, 0714230+I_FPN, 0714660+I_FPN, 0714670+I_FPN,
|
|
0715250+I_FPN, 0715270+I_FPN, 0711200+I_FPN,
|
|
0713271+I_FPN, 0713272+I_FPN, 0713273+I_FPN, 0713250+I_FPN,
|
|
#endif
|
|
#if defined (PDP9) || defined (PDP15)
|
|
0701701+I_NPI, 0701741+I_NPI, 0701702+I_NPI, 0701742+I_NPI,
|
|
0701704+I_NPI, 0701744+I_NPI, 0703201+I_NPI,
|
|
0703301+I_NPI, 0703302+I_NPI, 0703304+I_NPI, 0703344+I_NPI,
|
|
0705501+I_NPI, 0705512+I_NPN, 0705504+I_NPI,
|
|
#endif
|
|
0700000+I_IOT,
|
|
|
|
0740000+I_NPN, 0744002+I_NPN, 0744010+I_NPN, 0744020+I_NPN,
|
|
0750001+I_NPN, 0750004+I_NPN, 0750010+I_NPN,
|
|
0740000+I_OPR, 0740100+I_OPR, 0740200+I_OPR, 0740300+I_OPR,
|
|
0740400+I_OPR, 0740500+I_OPR, 0740600+I_OPR, 0740700+I_OPR,
|
|
0741000+I_OPR, 0741100+I_OPR, 0741200+I_OPR, 0741300+I_OPR,
|
|
0741400+I_OPR, 0741500+I_OPR, 0741600+I_OPR, 0741700+I_OPR,
|
|
0740010+I_OPR, 0740110+I_OPR, 0740210+I_OPR, 0740310+I_OPR,
|
|
0740410+I_OPR, 0740510+I_OPR, 0740610+I_OPR, 0740710+I_OPR,
|
|
0741010+I_OPR, 0741110+I_OPR, 0741210+I_OPR, 0741310+I_OPR,
|
|
0741410+I_OPR, 0741510+I_OPR, 0741610+I_OPR, 0741710+I_OPR,
|
|
0740020+I_OPR, 0740120+I_OPR, 0740220+I_OPR, 0740320+I_OPR,
|
|
0740420+I_OPR, 0740520+I_OPR, 0740620+I_OPR, 0740720+I_OPR,
|
|
0741020+I_OPR, 0741120+I_OPR, 0741220+I_OPR, 0741320+I_OPR,
|
|
0741420+I_OPR, 0741520+I_OPR, 0741620+I_OPR, 0741720+I_OPR,
|
|
0740030+I_OPR, 0740130+I_OPR, 0740230+I_OPR, 0740330+I_OPR,
|
|
0740430+I_OPR, 0740530+I_OPR, 0740630+I_OPR, 0740730+I_OPR,
|
|
0741030+I_OPR, 0741130+I_OPR, 0741230+I_OPR, 0741330+I_OPR,
|
|
0741430+I_OPR, 0741530+I_OPR, 0741630+I_OPR, 0741730+I_OPR,
|
|
0742000+I_OPR, 0742100+I_OPR, 0742200+I_OPR, 0742300+I_OPR,
|
|
0742400+I_OPR, 0742500+I_OPR, 0742600+I_OPR, 0742700+I_OPR,
|
|
0743000+I_OPR, 0743100+I_OPR, 0743200+I_OPR, 0743300+I_OPR,
|
|
0743400+I_OPR, 0743500+I_OPR, 0743600+I_OPR, 0743700+I_OPR,
|
|
0742010+I_OPR, 0742110+I_OPR, 0742210+I_OPR, 0742310+I_OPR,
|
|
0742410+I_OPR, 0742510+I_OPR, 0742610+I_OPR, 0742710+I_OPR,
|
|
0743010+I_OPR, 0743110+I_OPR, 0743210+I_OPR, 0743310+I_OPR,
|
|
0743410+I_OPR, 0743510+I_OPR, 0743610+I_OPR, 0743710+I_OPR,
|
|
0742020+I_OPR, 0742120+I_OPR, 0742220+I_OPR, 0742320+I_OPR,
|
|
0742420+I_OPR, 0742520+I_OPR, 0742620+I_OPR, 0742720+I_OPR,
|
|
0743020+I_OPR, 0743120+I_OPR, 0743220+I_OPR, 0743320+I_OPR,
|
|
0743420+I_OPR, 0743520+I_OPR, 0743620+I_OPR, 0743720+I_OPR,
|
|
0742030+I_OPR, 0742130+I_OPR, 0742230+I_OPR, 0742330+I_OPR,
|
|
0742430+I_OPR, 0742530+I_OPR, 0742630+I_OPR, 0742730+I_OPR,
|
|
0743030+I_OPR, 0743130+I_OPR, 0743230+I_OPR, 0743330+I_OPR,
|
|
0743430+I_OPR, 0743530+I_OPR, 0743630+I_OPR, 0743730+I_OPR,
|
|
|
|
0660000+I_EST, 0650000+I_EST, 0644000+I_EST, 0642000+I_EST, 0641000+I_EST,
|
|
0640004+I_EST, 0640002+I_EST, 0640001+I_EST,
|
|
0750000+I_OPR, 0744000+I_OPR, 0740002+I_OPR, 0740001+I_OPR,
|
|
0740004+I_OPR, 0740040+I_OPR,
|
|
-1
|
|
};
|
|
|
|
/* Operate or EAE decode
|
|
|
|
Inputs:
|
|
*of = output stream
|
|
inst = mask bits
|
|
class = instruction class code
|
|
sp = space needed?
|
|
Outputs:
|
|
status = space needed?
|
|
*/
|
|
|
|
int32 fprint_opr (FILE *of, int32 inst, int32 clss, int32 sp)
|
|
{
|
|
int32 i, j;
|
|
|
|
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
|
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
|
if ((j == clss) && (opc_val[i] & inst)) { /* same class? */
|
|
inst = inst & ~opc_val[i]; /* mask bit set? */
|
|
fprintf (of, (sp? " %s": "%s"), opcode[i]);
|
|
sp = 1;
|
|
}
|
|
}
|
|
return sp;
|
|
}
|
|
|
|
static int32 rar (int32 c)
|
|
{
|
|
c = c & 077;
|
|
return (c >> 1) | (c << 5);
|
|
}
|
|
|
|
/* Symbolic decode
|
|
|
|
Inputs:
|
|
*of = output stream
|
|
addr = current PC
|
|
*val = pointer to values
|
|
*uptr = pointer to unit
|
|
sw = switches
|
|
Outputs:
|
|
return = status code
|
|
*/
|
|
|
|
#define FMTASC(x) (((x) < 040)? "<%03o>": "%c"), (x)
|
|
#define SIXTOASC(x) (((x) >= 040)? (x): ((x) + 0100))
|
|
|
|
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
|
|
UNIT *uptr, int32 sw)
|
|
{
|
|
int32 i, j, k, sp, inst, disp, ma;
|
|
t_bool cflag;
|
|
DEVICE *dptr;
|
|
|
|
if (uptr == NULL)
|
|
uptr = &cpu_unit;
|
|
dptr = find_dev_from_unit (uptr);
|
|
if (dptr == NULL)
|
|
return SCPE_IERR;
|
|
|
|
inst = val[0];
|
|
if ((sw & SWMASK ('A')) != 0) { /* ASCII? */
|
|
if (inst > 0377)
|
|
return SCPE_ARG;
|
|
fprintf (of, FMTASC (inst & 0177));
|
|
return SCPE_OK;
|
|
}
|
|
|
|
if (dptr->dwidth < 18) /* 18b device? */
|
|
return SCPE_ARG;
|
|
|
|
if ((sw & SWMASK ('C')) != 0) { /* character? */
|
|
fprintf (of, "%c", SIXTOASC ((inst >> 12) & 077));
|
|
fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077));
|
|
fprintf (of, "%c", SIXTOASC (inst & 077));
|
|
return SCPE_OK;
|
|
}
|
|
if ((sw & SWMASK ('F')) != 0) { /* FIODEC? */
|
|
fprintf (of, "%c", fio_to_asc[(inst >> 12) & 077]);
|
|
fprintf (of, "%c", fio_to_asc[(inst >> 6) & 077]);
|
|
fprintf (of, "%c", fio_to_asc[inst & 077]);
|
|
return SCPE_OK;
|
|
}
|
|
if ((sw & SWMASK ('B')) != 0) { /* Baudot? */
|
|
fprintf (of, "%c", baud_to_asc[rar (inst >> 12) & 077]);
|
|
fprintf (of, "%c", baud_to_asc[rar (inst >> 6) & 077]);
|
|
fprintf (of, "%c", baud_to_asc[rar (inst) & 077]);
|
|
return SCPE_OK;
|
|
}
|
|
#if defined (PDP7) || defined (PDP9)
|
|
if ((sw & SWMASK ('U')) != 0) { /* Unix v0 ASCII? */
|
|
fprintf (of, FMTASC ((inst >> 9) & 0177));
|
|
fprintf (of, FMTASC (inst & 0177));
|
|
return SCPE_OK;
|
|
}
|
|
#elif defined (PDP15)
|
|
if ((sw & SWMASK ('P')) != 0) { /* packed ASCII? */
|
|
int32 t = val[1];
|
|
fprintf (of, FMTASC ((inst >> 11) & 0177));
|
|
fprintf (of, FMTASC ((inst >> 4) & 0177));
|
|
fprintf (of, FMTASC (((inst << 3) | (t >> 15)) & 0177));
|
|
fprintf (of, FMTASC ((t >> 8) & 0177));
|
|
fprintf (of, FMTASC ((t >> 1) & 0177));
|
|
return -1;
|
|
}
|
|
if ((sw & SWMASK ('U')) != 0) { /* Unibus ASCII? */
|
|
fprintf (of, FMTASC (inst & 0177));
|
|
fprintf (of, FMTASC ((inst >> 8) & 0177));
|
|
return SCPE_OK;
|
|
}
|
|
#endif
|
|
if ((sw & SWMASK ('M')) == 0) /* symbolic? */
|
|
return SCPE_ARG;
|
|
|
|
/* Instruction decode */
|
|
|
|
cflag = (uptr == &cpu_unit);
|
|
inst = val[0];
|
|
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
|
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
|
if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */
|
|
|
|
switch (j) { /* case on class */
|
|
|
|
case I_V_NPN: /* no operands */
|
|
case I_V_XR: /* index no opers */
|
|
fprintf (of, "%s", opcode[i]); /* opcode */
|
|
break;
|
|
|
|
case I_V_NPI: /* IOT no operand */
|
|
fprintf (of, "%s", opcode[i]); /* opcode */
|
|
if (inst & 010)
|
|
fprintf (of, " +10");
|
|
break;
|
|
|
|
case I_V_IOT: /* IOT or EAE */
|
|
fprintf (of, "%s %-o", opcode[i], inst & 037777);
|
|
break;
|
|
|
|
case I_V_MRF: /* mem ref */
|
|
#if defined (PDP15)
|
|
if (memm) {
|
|
disp = inst & B_DAMASK;
|
|
ma = (addr & (AMASK & ~B_DAMASK)) | disp;
|
|
}
|
|
else {
|
|
disp = inst & P_DAMASK;
|
|
ma = (addr & (AMASK & ~P_DAMASK)) | disp;
|
|
}
|
|
fprintf (of, "%s %-o", opcode[i], (cflag? ma & AMASK: disp));
|
|
if (!memm && (inst & I_IDX))
|
|
fprintf (of, ",X");
|
|
#else
|
|
disp = inst & B_DAMASK;
|
|
ma = (addr & (AMASK & ~B_DAMASK)) | disp;
|
|
fprintf (of, "%s %-o", opcode[i], (cflag? ma & AMASK: disp));
|
|
#endif
|
|
break;
|
|
|
|
case I_V_OPR: /* operate */
|
|
if ((sp = (inst & 03730)))
|
|
fprintf (of, "%s", opcode[i]);
|
|
fprint_opr (of, inst & 014047, I_V_OPR, sp);
|
|
break;
|
|
|
|
case I_V_LAW: /* LAW */
|
|
fprintf (of, "%s %-o", opcode[i], inst & 017777);
|
|
break;
|
|
|
|
case I_V_XR9: /* index with lit */
|
|
disp = inst & 0777;
|
|
if (disp & 0400)
|
|
fprintf (of, "%s -%-o", opcode[i], 01000 - disp);
|
|
else fprintf (of, "%s %-o", opcode[i], disp);
|
|
break;
|
|
|
|
case I_V_EST: /* EAE setup */
|
|
fprint_opr (of, inst & 037007, I_V_EST, 0);
|
|
break;
|
|
|
|
case I_V_ESH: /* EAE shift */
|
|
sp = fprint_opr (of, inst & 017000, I_V_EST, 0);
|
|
fprintf (of, (sp? " %s %-o": "%s %-o"), opcode[i], inst & 077);
|
|
break;
|
|
|
|
case I_V_EMD: /* EAE mul-div */
|
|
disp = inst & 077; /* get actual val */
|
|
k = (opc_val[i] >> I_V_DC) & 077; /* get default val */
|
|
if (disp == k)
|
|
fprintf (of, "%s", opcode[i]);
|
|
else if (disp < k)
|
|
fprintf (of, "%s -%-o", opcode[i], k - disp);
|
|
else fprintf (of, "%s +%-o", opcode[i], disp - k);
|
|
break;
|
|
|
|
case I_V_FPM: case I_V_FPI: /* FP15 mem ref */
|
|
fprintf (of, "%s", opcode[i]);
|
|
if (val[1] & SIGN)
|
|
fputc ('*', of);
|
|
fprintf (of, " %-o", val[1] & ~SIGN);
|
|
return -1;
|
|
|
|
case I_V_FPN: /* FP15 no operand */
|
|
fprintf (of, "%s", opcode[i]);
|
|
return -1;
|
|
} /* end case */
|
|
return SCPE_OK;
|
|
} /* end if */
|
|
} /* end for */
|
|
return SCPE_ARG;
|
|
}
|
|
|
|
/* Get 18b signed number
|
|
|
|
Inputs:
|
|
*cptr = pointer to input string
|
|
*sign = pointer to sign
|
|
*status = pointer to error status
|
|
Outputs:
|
|
val = output value
|
|
*/
|
|
|
|
t_value get_sint (char *cptr, int32 *sign, t_stat *status)
|
|
{
|
|
*sign = 0;
|
|
if (*cptr == '+') {
|
|
*sign = 1;
|
|
cptr++;
|
|
}
|
|
else if (*cptr == '-') {
|
|
*sign = -1;
|
|
cptr++;
|
|
}
|
|
return get_uint (cptr, 8, 0777777, status);
|
|
}
|
|
|
|
/* Symbolic input
|
|
|
|
Inputs:
|
|
*cptr = pointer to input string
|
|
addr = current PC
|
|
uptr = pointer to unit
|
|
*val = pointer to output values
|
|
sw = switches
|
|
Outputs:
|
|
status = error status
|
|
*/
|
|
t_stat parse_sym (CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
|
{
|
|
int32 d, i, j, k, sign, damask, epcmask;
|
|
t_stat r, sta = SCPE_OK;
|
|
char gbuf[CBUFSIZE], cbuf[2*CBUFSIZE];
|
|
t_bool cflag;
|
|
DEVICE *dptr;
|
|
|
|
if (uptr == NULL)
|
|
uptr = &cpu_unit;
|
|
dptr = find_dev_from_unit (uptr);
|
|
if (dptr == NULL)
|
|
return SCPE_IERR;
|
|
|
|
while (isspace (*cptr))
|
|
cptr++;
|
|
memset (cbuf, '\0', sizeof(cbuf));
|
|
strcpy (cbuf, cptr);
|
|
cptr = cbuf;
|
|
if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
|
|
if (cptr[0] == 0) /* must have 1 char */
|
|
return SCPE_ARG;
|
|
val[0] = (t_value) cptr[0] | 0200;
|
|
return SCPE_OK;
|
|
}
|
|
if (dptr->dwidth < 18) /* 18b decode? */
|
|
return SCPE_ARG; /* no, fail */
|
|
|
|
if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */
|
|
if (cptr[0] == 0) /* must have 1 char */
|
|
return SCPE_ARG;
|
|
val[0] = (((t_value) cptr[0] & 077) << 12) |
|
|
(((t_value) cptr[1] & 077) << 6) |
|
|
((t_value) cptr[2] & 077);
|
|
return SCPE_OK;
|
|
}
|
|
#if defined (PDP7) || defined (PDP9)
|
|
if (sw & SWMASK ('U')) { /* Unix v0 ASCII? */
|
|
if (cptr[0] == 0) /* must have 1 char */
|
|
return SCPE_ARG;
|
|
val[0] = (((t_value) cptr[0] & 0177) << 9) |
|
|
((t_value) cptr[1] & 0177);
|
|
return SCPE_OK;
|
|
}
|
|
#elif defined (PDP15)
|
|
if (sw & SWMASK ('P')) { /* packed string? */
|
|
if (cptr[0] == 0) /* must have 1 char */
|
|
return SCPE_ARG;
|
|
val[0] = (((t_value) cptr[0] & 0177) << 11) |
|
|
(((t_value) cptr[1] & 0177) << 4) |
|
|
(((t_value) cptr[2] & 0170) >> 3);
|
|
val[1] = (((t_value) cptr[2] & 0007) << 15) |
|
|
(((t_value) cptr[3] & 0177) << 8) |
|
|
(((t_value) cptr[4] & 0177) << 1);
|
|
return -1;
|
|
}
|
|
if (sw & SWMASK ('U')) { /* Unibus ASCII? */
|
|
if (cptr[0] == 0) /* must have 1 char */
|
|
return SCPE_ARG;
|
|
val[0] = (((t_value) cptr[1] & 0377) << 8) |
|
|
((t_value) cptr[0] & 0377);
|
|
return SCPE_OK;
|
|
}
|
|
#endif
|
|
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
|
|
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
|
if (opcode[i] == NULL)
|
|
return SCPE_ARG;
|
|
val[0] = opc_val[i] & DMASK; /* get value */
|
|
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
|
|
|
cflag = (uptr == &cpu_unit);
|
|
switch (j) { /* case on class */
|
|
|
|
case I_V_XR: /* index */
|
|
break;
|
|
|
|
case I_V_XR9: /* index literal */
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
|
d = get_sint (gbuf, &sign, &r);
|
|
if (r != SCPE_OK)
|
|
return SCPE_ARG;
|
|
if (((sign >= 0) && (d > 0377)) || ((sign < 0) && (d > 0400)))
|
|
return SCPE_ARG;
|
|
val[0] = val[0] | ((sign >= 0)? d: (01000 - d));
|
|
break;
|
|
|
|
case I_V_LAW: /* law */
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
|
d = get_uint (gbuf, 8, 017777, &r);
|
|
if (r != SCPE_OK)
|
|
return SCPE_ARG;
|
|
val[0] = val[0] | d;
|
|
break;
|
|
|
|
case I_V_MRF: /* mem ref */
|
|
#if defined (PDP15)
|
|
if (memm)
|
|
damask = B_DAMASK;
|
|
else damask = P_DAMASK;
|
|
cptr = get_glyph (cptr, gbuf, ','); /* get glyph */
|
|
#else
|
|
damask = B_DAMASK;
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
|
#endif
|
|
#if defined (PDP4) || defined (PDP7)
|
|
if (strcmp (gbuf, "I") == 0) { /* indirect? */
|
|
val[0] = val[0] | I_IND;
|
|
cptr = get_glyph (cptr, gbuf, 0);
|
|
}
|
|
#endif
|
|
epcmask = AMASK & ~damask; /* get ePC */
|
|
d = get_uint (gbuf, 8, AMASK, &r); /* get addr */
|
|
if (r != SCPE_OK)
|
|
return SCPE_ARG;
|
|
if (d <= damask) /* fit in 12/13b? */
|
|
val[0] = val[0] | d;
|
|
else if (cflag && (((addr ^ d) & epcmask) == 0))
|
|
val[0] = val[0] | (d & damask); /* hi bits = ePC? */
|
|
else return SCPE_ARG;
|
|
#if defined (PDP15)
|
|
if (!memm) {
|
|
cptr = get_glyph (cptr, gbuf, 0);
|
|
if (gbuf[0] != 0) {
|
|
if (strcmp (gbuf, "X") != 0)
|
|
return SCPE_ARG;
|
|
val[0] = val[0] | I_IDX;
|
|
}
|
|
}
|
|
#endif
|
|
break;
|
|
|
|
case I_V_EMD: /* or'able */
|
|
val[0] = val[0] | ((opc_val[i] >> I_V_DC) & 077); /* default shift */
|
|
case I_V_EST: case I_V_ESH:
|
|
case I_V_NPN: case I_V_NPI:
|
|
case I_V_IOT: case I_V_OPR:
|
|
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
|
|
cptr = get_glyph (cptr, gbuf, 0)) {
|
|
for (i = 0; (opcode[i] != NULL) &&
|
|
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
|
if (opcode[i] != NULL) {
|
|
k = opc_val[i] & DMASK;
|
|
if (((k ^ val[0]) & 0740000) != 0)
|
|
return SCPE_ARG;
|
|
val[0] = val[0] | k;
|
|
}
|
|
else {
|
|
d = get_sint (gbuf, & sign, &r);
|
|
if (r != SCPE_OK)
|
|
return SCPE_ARG;
|
|
if (sign > 0)
|
|
val[0] = val[0] + d;
|
|
else if (sign < 0)
|
|
val[0] = val[0] - d;
|
|
else val[0] = val[0] | d;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case I_V_FPM: /* FP15 mem ref */
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
|
val[1] = get_uint (gbuf, 8, AMASK, &r); /* get addr */
|
|
if (r != SCPE_OK)
|
|
return SCPE_ARG;
|
|
sta = -1;
|
|
break;
|
|
|
|
case I_V_FPI: /* FP15 ind mem ref */
|
|
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
|
val[1] = get_uint (gbuf, 8, AMASK, &r) | SIGN; /* get @addr */
|
|
if (r != SCPE_OK)
|
|
return SCPE_ARG;
|
|
sta = -1;
|
|
break;
|
|
|
|
case I_V_FPN: /* FP15 no operand */
|
|
val[1] = 0;
|
|
sta = -1;
|
|
break;
|
|
} /* end case */
|
|
|
|
if (*cptr != 0) /* junk at end? */
|
|
return SCPE_ARG;
|
|
return sta;
|
|
}
|