459 lines
18 KiB
C
459 lines
18 KiB
C
/* pdp8_rf.c: RF08 fixed head disk simulator
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Copyright (c) 1993-2021, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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rf RF08 fixed head disk
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21-Apr-21 RMS Fixed bug if read overwrites WC memory location
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17-Sep-13 RMS Changed to use central set_bootpc routine
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03-Sep-13 RMS Added explicit void * cast
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15-May-06 RMS Fixed bug in autosize attach (Dave Gesswein)
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07-Jan-06 RMS Fixed unaligned register access bug (Doug Carman)
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04-Jan-04 RMS Changed sim_fsize calling sequence
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26-Oct-03 RMS Cleaned up buffer copy code
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26-Jul-03 RMS Fixed bug in set size routine
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14-Mar-03 RMS Fixed variable platter interaction with save/restore
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03-Mar-03 RMS Fixed autosizing
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02-Feb-03 RMS Added variable platter and autosizing support
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04-Oct-02 RMS Added DIB, device number support
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28-Nov-01 RMS Added RL8A support
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25-Apr-01 RMS Added device enable/disable support
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19-Mar-01 RMS Added disk monitor bootstrap, fixed IOT decoding
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15-Feb-01 RMS Fixed 3 cycle data break sequence
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14-Apr-99 RMS Changed t_addr to unsigned
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30-Mar-98 RMS Fixed bug in RF bootstrap
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The RF08 is a head-per-track disk. It uses the three cycle data break
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facility. To minimize overhead, the entire RF08 is buffered in memory.
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Two timing parameters are provided:
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rf_time Interword timing, must be non-zero
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rf_burst Burst mode, if 0, DMA occurs cycle by cycle; otherwise,
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DMA occurs in a burst
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*/
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#include "pdp8_defs.h"
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#include <math.h>
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#define UNIT_V_AUTO (UNIT_V_UF + 0) /* autosize */
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#define UNIT_V_PLAT (UNIT_V_UF + 1) /* #platters - 1 */
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#define UNIT_M_PLAT 03
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#define UNIT_GETP(x) ((((x) >> UNIT_V_PLAT) & UNIT_M_PLAT) + 1)
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#define UNIT_AUTO (1 << UNIT_V_AUTO)
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#define UNIT_PLAT (UNIT_M_PLAT << UNIT_V_PLAT)
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/* Constants */
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#define RF_NUMWD 2048 /* words/track */
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#define RF_NUMTR 128 /* tracks/disk */
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#define RF_DKSIZE (RF_NUMTR * RF_NUMWD) /* words/disk */
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#define RF_NUMDK 4 /* disks/controller */
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#define RF_WC 07750 /* word count */
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#define RF_MA 07751 /* mem address */
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#define RF_WMASK (RF_NUMWD - 1) /* word mask */
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/* Parameters in the unit descriptor */
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#define FUNC u4 /* function */
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#define RF_READ 2 /* read */
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#define RF_WRITE 4 /* write */
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/* Status register */
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#define RFS_PCA 04000 /* photocell status */
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#define RFS_DRE 02000 /* data req enable */
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#define RFS_WLS 01000 /* write lock status */
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#define RFS_EIE 00400 /* error int enable */
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#define RFS_PIE 00200 /* photocell int enb */
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#define RFS_CIE 00100 /* done int enable */
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#define RFS_MEX 00070 /* memory extension */
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#define RFS_DRL 00004 /* data late error */
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#define RFS_NXD 00002 /* non-existent disk */
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#define RFS_PER 00001 /* parity error */
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#define RFS_ERR (RFS_WLS + RFS_DRL + RFS_NXD + RFS_PER)
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#define RFS_V_MEX 3
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#define GET_MEX(x) (((x) & RFS_MEX) << (12 - RFS_V_MEX))
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#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \
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((double) RF_NUMWD)))
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#define UPDATE_PCELL if (GET_POS(rf_time) < 6) rf_sta = rf_sta | RFS_PCA; \
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else rf_sta = rf_sta & ~RFS_PCA
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#define RF_INT_UPDATE if ((rf_done && (rf_sta & RFS_CIE)) || \
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((rf_sta & RFS_ERR) && (rf_sta & RFS_EIE)) || \
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((rf_sta & RFS_PCA) && (rf_sta & RFS_PIE))) \
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int_req = int_req | INT_RF; \
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else int_req = int_req & ~INT_RF
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extern uint16 M[];
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extern int32 int_req, stop_inst;
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extern UNIT cpu_unit;
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int32 rf_sta = 0; /* status register */
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int32 rf_da = 0; /* disk address */
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int32 rf_done = 0; /* done flag */
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int32 rf_wlk = 0; /* write lock */
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int32 rf_time = 10; /* inter-word time */
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int32 rf_burst = 1; /* burst mode flag */
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int32 rf_stopioe = 1; /* stop on error */
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int32 rf60 (int32 IR, int32 AC);
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int32 rf61 (int32 IR, int32 AC);
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int32 rf62 (int32 IR, int32 AC);
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int32 rf64 (int32 IR, int32 AC);
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t_stat rf_svc (UNIT *uptr);
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t_stat pcell_svc (UNIT *uptr);
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t_stat rf_reset (DEVICE *dptr);
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t_stat rf_boot (int32 unitno, DEVICE *dptr);
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t_stat rf_attach (UNIT *uptr, CONST char *cptr);
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t_stat rf_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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const char *rf_description (DEVICE *dptr);
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/* RF08 data structures
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rf_dev RF device descriptor
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rf_unit RF unit descriptor
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pcell_unit photocell timing unit
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rf_reg RF register list
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*/
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DIB rf_dib = { DEV_RF, 5, { &rf60, &rf61, &rf62, NULL, &rf64 } };
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UNIT rf_units[] = {
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{ UDATA (&rf_svc, UNIT_FIX+UNIT_ATTABLE+
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UNIT_BUFABLE+UNIT_MUSTBUF, RF_DKSIZE) },
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{ UDATA (&pcell_svc, UNIT_DIS, 0) }
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};
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#define rf_unit rf_units[0]
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#define pcell_unit rf_units[1]
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REG rf_reg[] = {
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{ ORDATAD (STA, rf_sta, 12, "status") },
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{ ORDATAD (DA, rf_da, 20, "low order disk address") },
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{ ORDATAD (WC, M[RF_WC], 12, "word count (in memory)"), REG_FIT },
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{ ORDATAD (MA, M[RF_MA], 12, "memory address (in memory)"), REG_FIT },
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{ FLDATAD (DONE, rf_done, 0, "device done flag") },
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{ FLDATAD (INT, int_req, INT_V_RF, "interrupt pending flag") },
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{ ORDATAD (WLK, rf_wlk, 32, "write lock switches") },
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{ DRDATAD (TIME, rf_time, 24, "rotational delay, per word"), REG_NZ + PV_LEFT },
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{ FLDATAD (BURST, rf_burst, 0, "burst flag") },
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{ FLDATAD (STOP_IOE, rf_stopioe, 0, "stop on I/O error") },
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{ DRDATA (CAPAC, rf_unit.capac, 21), REG_HRO },
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{ ORDATA (DEVNUM, rf_dib.dev, 6), REG_HRO },
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{ NULL }
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};
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MTAB rf_mod[] = {
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{ UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &rf_set_size },
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{ UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &rf_set_size },
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{ UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &rf_set_size },
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{ UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &rf_set_size },
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{ UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
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&set_dev, &show_dev, NULL },
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{ 0 }
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};
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DEVICE rf_dev = {
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"RF", rf_units, rf_reg, rf_mod,
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2, 8, 20, 1, 8, 12,
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NULL, NULL, &rf_reset,
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&rf_boot, &rf_attach, NULL,
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&rf_dib, DEV_DISABLE | DEV_DIS, 0,
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NULL, NULL, NULL, NULL, NULL, NULL,
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&rf_description
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};
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/* IOT routines */
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int32 rf60 (int32 IR, int32 AC)
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{
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int32 t;
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int32 pulse = IR & 07;
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UPDATE_PCELL; /* update photocell */
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if (pulse & 1) { /* DCMA */
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rf_da = rf_da & ~07777; /* clear DAR<8:19> */
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rf_done = 0; /* clear done */
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rf_sta = rf_sta & ~RFS_ERR; /* clear errors */
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RF_INT_UPDATE; /* update int req */
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}
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if (pulse & 6) { /* DMAR, DMAW */
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rf_da = rf_da | AC; /* DAR<8:19> |= AC */
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rf_unit.FUNC = pulse & ~1; /* save function */
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t = (rf_da & RF_WMASK) - GET_POS (rf_time); /* delta to new loc */
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if (t < 0) /* wrap around? */
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t = t + RF_NUMWD;
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sim_activate (&rf_unit, t * rf_time); /* schedule op */
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AC = 0; /* clear AC */
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}
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return AC;
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}
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int32 rf61 (int32 IR, int32 AC)
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{
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int32 pulse = IR & 07;
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UPDATE_PCELL; /* update photocell */
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switch (pulse) { /* decode IR<9:11> */
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case 1: /* DCIM */
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rf_sta = rf_sta & 07007; /* clear STA<3:8> */
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int_req = int_req & ~INT_RF; /* clear int req */
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sim_cancel (&pcell_unit); /* cancel photocell */
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return AC;
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case 2: /* DSAC */
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return ((rf_da & RF_WMASK) == GET_POS (rf_time))? IOT_SKP: 0;
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case 5: /* DIML */
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rf_sta = (rf_sta & 07007) | (AC & 0770); /* STA<3:8> <- AC */
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if (rf_sta & RFS_PIE) /* photocell int? */
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sim_activate (&pcell_unit, (RF_NUMWD - GET_POS (rf_time)) *
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rf_time);
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else sim_cancel (&pcell_unit);
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RF_INT_UPDATE; /* update int req */
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return 0; /* clear AC */
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case 6: /* DIMA */
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return rf_sta; /* AC <- STA<0:11> */
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}
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return AC;
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}
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int32 rf62 (int32 IR, int32 AC)
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{
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int32 pulse = IR & 07;
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UPDATE_PCELL; /* update photocell */
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if (pulse & 1) { /* DFSE */
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if (rf_sta & RFS_ERR)
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AC = AC | IOT_SKP;
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}
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if (pulse & 2) { /* DFSC */
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if (pulse & 4) /* for DMAC */
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AC = AC & ~07777;
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else if (rf_done)
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AC = AC | IOT_SKP;
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}
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if (pulse & 4) /* DMAC */
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AC = AC | (rf_da & 07777);
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return AC;
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}
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int32 rf64 (int32 IR, int32 AC)
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{
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int32 pulse = IR & 07;
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UPDATE_PCELL; /* update photocell */
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switch (pulse) { /* decode IR<9:11> */
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case 1: /* DCXA */
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rf_da = rf_da & 07777; /* clear DAR<0:7> */
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break;
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case 3: /* DXAL */
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rf_da = rf_da & 07777; /* clear DAR<0:7> */
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case 2: /* DXAL w/o clear */
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rf_da = rf_da | ((AC & 0377) << 12); /* DAR<0:7> |= AC */
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AC = 0; /* clear AC */
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break;
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case 5: /* DXAC */
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AC = 0; /* clear AC */
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case 4: /* DXAC w/o clear */
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AC = AC | ((rf_da >> 12) & 0377); /* AC |= DAR<0:7> */
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break;
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default:
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AC = (stop_inst << IOT_V_REASON) + AC;
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break;
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} /* end switch */
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if ((uint32) rf_da >= rf_unit.capac)
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rf_sta = rf_sta | RFS_NXD;
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else rf_sta = rf_sta & ~RFS_NXD;
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RF_INT_UPDATE;
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return AC;
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}
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/* Unit service
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Note that for reads and writes, memory addresses wrap around in the
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current field. This code assumes the entire disk is buffered.
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*/
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t_stat rf_svc (UNIT *uptr)
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{
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int32 pa, t, mex;
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int16 *fbuf = (int16 *) uptr->filebuf;
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uint16 wc = 0;
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UPDATE_PCELL; /* update photocell */
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if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */
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rf_sta = rf_sta | RFS_NXD;
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rf_done = 1;
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RF_INT_UPDATE; /* update int req */
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return IORETURN (rf_stopioe, SCPE_UNATT);
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}
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mex = GET_MEX (rf_sta);
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do {
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if ((uint32) rf_da >= rf_unit.capac) { /* disk overflow? */
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rf_sta = rf_sta | RFS_NXD;
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break;
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}
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wc = M[RF_WC] = (M[RF_WC] + 1) & 07777; /* incr word count */
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M[RF_MA] = (M[RF_MA] + 1) & 07777; /* incr mem addr */
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pa = mex | M[RF_MA]; /* add extension */
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if (uptr->FUNC == RF_READ) { /* read? */
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if (MEM_ADDR_OK (pa)) /* if !nxm */
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M[pa] = fbuf[rf_da]; /* read word */
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}
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else { /* write */
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t = ((rf_da >> 15) & 030) | ((rf_da >> 14) & 07);
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if ((rf_wlk >> t) & 1) /* write locked? */
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rf_sta = rf_sta | RFS_WLS;
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else { /* not locked */
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fbuf[rf_da] = M[pa]; /* write word */
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if (((uint32) rf_da) >= uptr->hwmark)
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uptr->hwmark = rf_da + 1;
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}
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}
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rf_da = (rf_da + 1) & 03777777; /* incr disk addr */
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} while ((wc != 0) && (rf_burst != 0)); /* brk if wc, no brst */
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if ((wc != 0) && ((rf_sta & RFS_ERR) == 0)) /* more to do? */
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sim_activate (&rf_unit, rf_time); /* sched next */
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else {
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rf_done = 1; /* done */
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RF_INT_UPDATE; /* update int req */
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}
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return SCPE_OK;
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}
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/* Photocell unit service */
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t_stat pcell_svc (UNIT *uptr)
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{
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rf_sta = rf_sta | RFS_PCA; /* set photocell */
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if (rf_sta & RFS_PIE) { /* int enable? */
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sim_activate (&pcell_unit, RF_NUMWD * rf_time);
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int_req = int_req | INT_RF;
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}
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat rf_reset (DEVICE *dptr)
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{
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rf_sta = rf_da = 0;
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rf_done = 1;
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int_req = int_req & ~INT_RF; /* clear interrupt */
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sim_cancel (&rf_unit);
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sim_cancel (&pcell_unit);
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return SCPE_OK;
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}
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/* Bootstrap routine */
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#define OS8_START 07750
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#define OS8_LEN (sizeof (os8_rom) / sizeof (int16))
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#define DM4_START 00200
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#define DM4_LEN (sizeof (dm4_rom) / sizeof (int16))
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static const uint16 os8_rom[] = {
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07600, /* 7750, CLA CLL ; also word count */
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06603, /* 7751, DMAR ; also address */
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06622, /* 7752, DFSC ; done? */
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05352, /* 7753, JMP .-1 ; no */
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05752 /* 7754, JMP @.-2 ; enter boot */
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};
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static const uint16 dm4_rom[] = {
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00200, 07600, /* 0200, CLA CLL */
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00201, 06603, /* 0201, DMAR ; read */
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00202, 06622, /* 0202, DFSC ; done? */
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00203, 05202, /* 0203, JMP .-1 ; no */
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00204, 05600, /* 0204, JMP @.-4 ; enter boot */
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07750, 07576, /* 7750, 7576 ; word count */
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07751, 07576 /* 7751, 7576 ; address */
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};
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t_stat rf_boot (int32 unitno, DEVICE *dptr)
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{
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size_t i;
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if (rf_dib.dev != DEV_RF) /* only std devno */
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return STOP_NOTSTD;
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if (sim_switches & SWMASK ('D')) {
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for (i = 0; i < DM4_LEN; i = i + 2)
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M[dm4_rom[i]] = dm4_rom[i + 1];
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cpu_set_bootpc (DM4_START);
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}
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else {
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for (i = 0; i < OS8_LEN; i++)
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M[OS8_START + i] = os8_rom[i];
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cpu_set_bootpc (OS8_START);
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}
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return SCPE_OK;
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}
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/* Attach routine */
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t_stat rf_attach (UNIT *uptr, CONST char *cptr)
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{
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uint32 sz, p;
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uint32 ds_bytes = RF_DKSIZE * sizeof (int16);
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if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {
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p = (sz + ds_bytes - 1) / ds_bytes;
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if (p >= RF_NUMDK)
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p = RF_NUMDK - 1;
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uptr->flags = (uptr->flags & ~UNIT_PLAT) |
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(p << UNIT_V_PLAT);
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}
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uptr->capac = UNIT_GETP (uptr->flags) * RF_DKSIZE;
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return attach_unit (uptr, cptr);
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}
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/* Change disk size */
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t_stat rf_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
|
|
if (val < 0)
|
|
return SCPE_IERR;
|
|
if (uptr->flags & UNIT_ATT)
|
|
return SCPE_ALATT;
|
|
uptr->capac = UNIT_GETP (val) * RF_DKSIZE;
|
|
uptr->flags = uptr->flags & ~UNIT_AUTO;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
const char *rf_description (DEVICE *dptr)
|
|
{
|
|
return "RF08 fixed head disk";
|
|
}
|