358 lines
13 KiB
C
358 lines
13 KiB
C
/* i8251.c: Intel i8251 UART adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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?? ??? 10 - Original file.
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16 Dec 12 - Modified to use isbc_80_10.cfg file to set i8251_baseport and size.
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24 Apr 15 -- Modified to use simh_debug
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NOTES:
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These functions support a simulated i8251 interface device on an iSBC.
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The device had one physical I/O port which could be connected
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to any serial I/O device that would connect to a current loop,
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RS232, or TTY interface. Available baud rates were jumper
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selectable for each port from 110 to 9600.
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All I/O is via programmed I/O. The i8251 has a status port
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and a data port.
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The simulated device does not support synchronous mode. The simulated device
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supports a select from I/O space and one address line. The data port is at the
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lower address and the status/command port is at the higher.
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A write to the status port can select some options for the device:
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Asynchronous Mode Instruction
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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| S2 S1 EP PEN L2 L1 B2 B1|
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+---+---+---+---+---+---+---+---+
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Baud Rate Factor
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B2 0 1 0 1
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B1 0 0 1 1
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sync 1X 16X 64X
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mode
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Character Length
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L2 0 1 0 1
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L1 0 0 1 1
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5 6 7 8
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bits bits bits bits
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EP - A 1 in this bit position selects even parity.
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PEN - A 1 in this bit position enables parity.
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Number of Stop Bits
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S2 0 1 0 1
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S1 0 0 1 1
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invalid 1 1.5 2
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bit bits bits
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Command Instruction Format
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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| EH IR RTS ER SBRK RxE DTR TxE|
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+---+---+---+---+---+---+---+---+
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TxE - A 1 in this bit position enables transmit.
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DTR - A 1 in this bit position forces *DTR to zero.
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RxE - A 1 in this bit position enables receive.
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SBRK - A 1 in this bit position forces TxD to zero.
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ER - A 1 in this bit position resets the error bits
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RTS - A 1 in this bit position forces *RTS to zero.
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IR - A 1 in this bit position returns the 8251 to Mode Instruction Format.
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EH - A 1 in this bit position enables search for sync characters.
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A read of the status port gets the port status:
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Status Read Format
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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|DSR SD FE OE PE TxE RxR TxR|
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+---+---+---+---+---+---+---+---+
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TxR - A 1 in this bit position signals transmit ready to receive a character.
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RxR - A 1 in this bit position signals receiver has a character.
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TxE - A 1 in this bit position signals transmitter has no more characters to transmit.
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PE - A 1 in this bit signals a parity error.
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OE - A 1 in this bit signals an transmit overrun error.
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FE - A 1 in this bit signals a framing error.
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SD - A 1 in this bit position returns the 8251 to Mode Instruction Format.
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DSR - A 1 in this bit position signals *DSR is at zero.
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A read from the data port gets the typed character, a write
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to the data port writes the character to the device.
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*/
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#include "system_defs.h"
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#define UNIT_V_ANSI (UNIT_V_UF + 0) /* ANSI mode */
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#define UNIT_ANSI (1 << UNIT_V_ANSI)
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// 8251 status bits
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#define TXR 0x01
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#define RXR 0x02
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#define TXE 0x04
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#define SD 0x40
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#define i8251_NAME "Intel i8251 UART Chip"
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/* external globals */
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern uint8 unreg_dev(uint16);
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/* globals */
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static const char* i8251_desc(DEVICE *dptr) {
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return i8251_NAME;
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}
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int i8251_num = 0;
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int i8251_baseport[4] = { -1, -1, -1, -1 }; //base port
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uint8 i8251_intnum[4] = { 0, 0, 0, 0 }; //interrupt number
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uint8 i8251_verb[4] = { 0, 0, 0, 0 }; //verbose flag
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/* function prototypes */
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t_stat i8251_cfg(uint16 base, uint16 devnum, uint8 dummy);
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t_stat i8251_clr(void);
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t_stat i8251_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat i8251_svc (UNIT *uptr);
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t_stat i8251_reset (DEVICE *dptr);
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uint8 i8251s(t_bool io, uint8 data, uint8 devnum);
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uint8 i8251d(t_bool io, uint8 data, uint8 devnum);
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void i8251_reset_dev(uint16 devnum);
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/* i8251 Standard I/O Data Structures */
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/* up to 4 i8251 devices */
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UNIT i8251_unit[4] = {
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{ UDATA (&i8251_svc, 0, 0), KBD_POLL_WAIT },
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{ UDATA (&i8251_svc, 0, 0), KBD_POLL_WAIT },
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{ UDATA (&i8251_svc, 0, 0), KBD_POLL_WAIT },
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{ UDATA (&i8251_svc, 0, 0), KBD_POLL_WAIT }
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};
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REG i8251_reg[] = {
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{ HRDATA (DATA0, i8251_unit[0].buf, 8) },
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{ HRDATA (STAT0, i8251_unit[0].u3, 8) },
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{ HRDATA (MODE0, i8251_unit[0].u4, 8) },
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{ HRDATA (CMD0, i8251_unit[0].u5, 8) },
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{ HRDATA (DATA1, i8251_unit[1].buf, 8) },
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{ HRDATA (STAT1, i8251_unit[1].u3, 8) },
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{ HRDATA (MODE1, i8251_unit[1].u4, 8) },
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{ HRDATA (CMD1, i8251_unit[1].u5, 8) },
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{ HRDATA (DATA2, i8251_unit[2].buf, 8) },
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{ HRDATA (STAT2, i8251_unit[2].u3, 8) },
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{ HRDATA (MODE2, i8251_unit[2].u4, 8) },
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{ HRDATA (CMD2, i8251_unit[2].u5, 8) },
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{ HRDATA (DATA3, i8251_unit[3].buf, 8) },
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{ HRDATA (STAT3, i8251_unit[3].u3, 8) },
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{ HRDATA (MODE3, i8251_unit[3].u4, 8) },
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{ HRDATA (CMD3, i8251_unit[3].u5, 8) },
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{ NULL }
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};
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DEBTAB i8251_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ NULL }
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};
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MTAB i8251_mod[] = {
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{ UNIT_ANSI, 0, "ANSI", "ANSI", NULL },
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{ UNIT_ANSI, UNIT_ANSI, "TTY", "TTY", NULL },
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i8251_show_param, NULL,
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"show configured parameters for i8251" },
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE i8251_dev = {
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"I8251", //name
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i8251_unit, //units
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i8251_reg, //registers
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i8251_mod, //modifiers
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I8251_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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&i8251_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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i8251_debug, //debflags
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NULL, //memeory size change
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NULL, //lname
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NULL, //help routine
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NULL, //attach help routine
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NULL, //help context
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&i8251_desc //device description
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};
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// i8251 configuration
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t_stat i8251_cfg(uint16 base, uint16 devnum, uint8 dummy)
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{
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i8251_baseport[devnum] = base & BYTEMASK;
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sim_printf(" i8251%d: installed at base port 0%02XH\n",
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devnum, i8251_baseport[devnum]);
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reg_dev(i8251d, i8251_baseport[devnum], devnum, 0);
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reg_dev(i8251s, i8251_baseport[devnum] + 1, devnum, 0);
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i8251_reset_dev(devnum);
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if (devnum == 0)
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sim_activate (&i8251_unit[devnum], i8251_unit[devnum].wait); /* activate unit 0 */
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i8251_num++; //next device
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return SCPE_OK;
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}
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t_stat i8251_clr(void)
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{
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int i;
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for (i=0; i<i8251_num; i++) {
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unreg_dev(i8251_baseport[i]);
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unreg_dev(i8251_baseport[i] + 1);
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i8251_baseport[i] = -1;
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i8251_intnum[i] = 0;
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i8251_verb[i] = 0;
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}
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i8251_num = 0;
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return SCPE_OK;
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}
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// show configuration parameters
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t_stat i8251_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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int i;
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "Device %s\n", ((i8251_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled");
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for (i=0; i<i8251_num; i++) {
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fprintf(st, "Unit %d at Base port ", i);
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fprintf(st, "0%02XH, ", i8251_baseport[i]);
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fprintf(st, "Interrupt # is ");
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fprintf(st, "%d, ", i8251_intnum[i]);
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fprintf(st, "Mode ");
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fprintf(st, "%s", i8251_verb[i] ? "Verbose" : "Quiet");
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if (i<i8251_num && i8251_num != 1) fprintf(st, "\n");
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}
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return SCPE_OK;
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}
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/* Service routines to handled simulator functions */
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/* i8251_svc - actually gets char & places in buffer */
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t_stat i8251_svc (UNIT *uptr)
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{
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int32 temp;
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sim_activate (uptr, uptr->wait); /* continue poll */
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if ((temp = sim_poll_kbd ()) < SCPE_KFLAG)
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return temp; /* no char or error? */
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uptr->buf = temp & 0x7F; /* Save char */
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if (uptr->flags & UNIT_ANSI)
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uptr->buf = toupper(uptr->buf);
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uptr->u3 |= RXR; /* Set status */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat i8251_reset (DEVICE *dptr)
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{
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uint8 devnum;
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for (devnum=0; devnum<i8251_num+1; devnum++) {
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i8251_reset_dev(devnum);
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if (devnum == 0)
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sim_activate (&i8251_unit[devnum], i8251_unit[devnum].wait); /* activate unit 0 */
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}
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return SCPE_OK;
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}
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void i8251_reset_dev(uint16 devnum)
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{
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i8251_unit[devnum].u3 = TXR + TXE; /* status */
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i8251_unit[devnum].u4 = 0; /* mode instruction */
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i8251_unit[devnum].u5 = 0; /* command instruction */
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i8251_unit[devnum].u6 = 0;
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i8251_unit[devnum].buf = 0;
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i8251_unit[devnum].pos = 0;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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uint8 i8251s(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read status port */
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return i8251_unit[devnum].u3;
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} else { /* write status port */
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if (i8251_unit[devnum].u4) { /* if mode, set cmd */
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i8251_unit[devnum].u5 = data;
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if (data & SD) /* reset port! */
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i8251_reset_dev(devnum);
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} else { /* set mode */
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i8251_unit[devnum].u4 = data;
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i8251_unit[devnum].u6 = 1; /* set cmd received */
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}
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}
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return 0;
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}
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uint8 i8251d(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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i8251_unit[devnum].u3 &= ~RXR;
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return (i8251_unit[devnum].buf);
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} else { /* write data port */
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sim_putchar(data);
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}
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return 0;
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}
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/* end of i8251.c */
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