305 lines
10 KiB
C
305 lines
10 KiB
C
/* i8259.c: Intel i8259 PIC adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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NOTES:
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This software was written by Bill Beech, 24 Jan 13, to allow emulation of
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more complex Multibus Computer Systems.
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This program simulates up to 4 i8259 devices. It handles 1 i8259
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device on the iSBC 80/20 and iSBC 80/30 SBCs. Other devices could be on
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other multibus boards in the simulated system.
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*/
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#include "system_defs.h" /* system header in system dir */
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#define i8259_NAME "Intel i8259 PIC Chip"
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/* function prototypes */
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t_stat i8259_cfg(uint16 base, uint16 devnum, uint8 dummy);
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t_stat i8259_clr(void);
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t_stat i8259_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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uint8 i8259a(t_bool io, uint8 data, uint8 devnum);
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uint8 i8259b(t_bool io, uint8 data, uint8 devnum);
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void i8259_dump(uint8 devnum);
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t_stat i8259_reset (DEVICE *dptr);
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/* external globals */
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static const char* i8259_desc(DEVICE *dptr) {
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return i8259_NAME;
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}
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int i8259_num = 0;
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uint8 icw_num0 = 1, icw_num1 = 1;
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern uint8 unreg_dev(uint16);
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/* globals */
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/* these bytes represent the input and output to/from a device instance */
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uint8 i8259_IR[4]; //interrupt inputs (bits 0-7)
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uint8 i8259_CAS[4]; //interrupt cascade I/O (bits 0-2)
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uint8 i8259_INT[4]; //interrupt output (bit 0)
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uint8 i8259_base[4];
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uint8 i8259_icw1[4];
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uint8 i8259_icw2[4];
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uint8 i8259_icw3[4];
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uint8 i8259_icw4[4];
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uint8 i8259_ocw1[4];
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uint8 i8259_ocw2[4];
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uint8 i8259_ocw3[4];
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int i8259_baseport[] = { -1, -1, -1, -1 }; //base port
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uint8 i8259_intnum[4] = { 0, 0, 0, 0 }; //interrupt number
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uint8 i8259_verb[4] = { 0, 0, 0, 0 }; //verbose flag
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/* i8259 Standard I/O Data Structures */
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/* up to 4 i8259 devices */
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UNIT i8259_unit[] = {
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{ UDATA (0, 0, 0) }, /* i8259 0 */
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{ UDATA (0, 0, 0) }, /* i8259 1 */
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{ UDATA (0, 0, 0) }, /* i8259 2 */
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{ UDATA (0, 0, 0) } /* i8259 3 */
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};
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REG i8259_reg[] = {
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{ URDATAD(IRR0,i8259_unit[0].u3,16,8,0,4,0,"IRR0") },
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{ URDATAD(ISR0,i8259_unit[0].u4,16,8,0,4,0,"ISR0") },
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{ URDATAD(IMR0,i8259_unit[0].u5,16,8,0,4,0,"IMR0") },
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{ NULL }
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};
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DEBTAB i8259_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ NULL }
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};
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MTAB i8259_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i8259_show_param, NULL,
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"show configured parameters for i8259" },
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE i8259_dev = {
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"I8259", //name
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i8259_unit, //units
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i8259_reg, //registers
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i8259_mod, //modifiers
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4, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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i8259_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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i8259_debug, //debflags
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NULL, //msize
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NULL, //lname
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NULL, //help routine
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NULL, //attach help routine
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NULL, //help context
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&i8259_desc //device description
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};
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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// i8259 configuration
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t_stat i8259_cfg(uint16 base, uint16 devnum, uint8 dummy)
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{
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i8259_baseport[devnum] = base & BYTEMASK;
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sim_printf(" i8259%d: installed at base port 0%02XH\n",
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devnum, i8259_baseport[devnum]);
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reg_dev(i8259a, i8259_baseport[devnum], devnum, 0);
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reg_dev(i8259b, i8259_baseport[devnum] + 1, devnum, 0);
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i8259_num++;
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return SCPE_OK;
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}
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t_stat i8259_clr(void)
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{
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int i;
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for (i=0; i<i8259_num; i++) {
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unreg_dev(i8259_baseport[i]);
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unreg_dev(i8259_baseport[i] + 1);
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i8259_baseport[i] = -1;
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i8259_intnum[i] = 0;
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i8259_verb[i] = 0;
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}
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i8259_num = 0;
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return SCPE_OK;
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}
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// show configuration parameters
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t_stat i8259_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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int i;
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "Device %s\n", ((i8259_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled");
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for (i=0; i<i8259_num; i++) {
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fprintf(st, "Unit %d at Base port ", i);
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fprintf(st, "0%02X ", i8259_baseport[i]);
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fprintf(st, "Interrupt # is ");
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fprintf(st, "%d ", i8259_intnum[i]);
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fprintf(st, "Mode ");
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fprintf(st, "%s", i8259_verb[i] ? "Verbose" : "Quiet");
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if (i<i8259_num && i8259_num != 1) fprintf(st, "\n");
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}
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat i8259_reset (DEVICE *dptr)
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{
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uint8 devnum;
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for (devnum=0; devnum < 4; devnum++) {
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if (devnum < i8259_num) {
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i8259_unit[devnum].flags = 0;
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i8259_unit[devnum].u3 = 0x00; /* IRR */
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i8259_unit[devnum].u4 = 0x00; /* ISR */
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i8259_unit[devnum].u5 = 0x00; /* IMR */
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} else {
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sim_cancel (&i8259_unit[devnum]);
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i8259_unit[devnum].flags = UNIT_DIS;
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}
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}
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return SCPE_OK;
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}
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/* i8259 functions */
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uint8 i8259a(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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if ((i8259_ocw3[devnum] & 0x03) == 0x02)
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return (i8259_unit[devnum].u3); /* IRR */
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if ((i8259_ocw3[devnum] & 0x03) == 0x03)
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return (i8259_unit[devnum].u4); /* ISR */
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} else { /* write data port */
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if (data & 0x10) {
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icw_num0 = 1;
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}
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if (icw_num0 == 1) {
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i8259_icw1[devnum] = data; /* ICW1 */
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i8259_unit[devnum].u5 = 0x00; /* clear IMR */
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i8259_ocw3[devnum] = 0x02; /* clear OCW3, Sel IRR */
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} else {
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switch (data & 0x18) {
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case 0: /* OCW2 */
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i8259_ocw2[devnum] = data;
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break;
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case 8: /* OCW3 */
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i8259_ocw3[devnum] = data;
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break;
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default:
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sim_printf("8259a-%d: OCW Error %02X\n", devnum, data);
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break;
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}
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}
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icw_num0++; /* step ICW number */
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}
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// i8259_dump(devnum);
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return 0;
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}
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uint8 i8259b(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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if ((i8259_ocw3[devnum] & 0x03) == 0x02)
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return (i8259_unit[devnum].u3); /* IRR */
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if ((i8259_ocw3[devnum] & 0x03) == 0x03)
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return (i8259_unit[devnum].u4); /* ISR */
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} else { /* write data port */
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if (data & 0x10) {
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icw_num1 = 1;
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}
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if (icw_num1 == 1) {
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i8259_icw1[devnum] = data; /* ICW1 */
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i8259_unit[devnum].u5 = 0x00; /* clear IMR */
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i8259_ocw3[devnum] = 0x02; /* clear OCW3, Sel IRR */
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} else {
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switch (data & 0x18) {
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case 0: /* OCW2 */
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i8259_ocw2[devnum] = data;
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break;
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case 8: /* OCW3 */
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i8259_ocw3[devnum] = data;
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break;
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default:
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sim_printf("8259b-%d: OCW Error %02X\n", devnum, data);
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break;
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}
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}
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icw_num1++; /* step ICW number */
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}
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// i8259_dump(devnum);
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return 0;
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}
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void i8259_dump(uint8 devnum)
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{
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sim_printf("Device %d", devnum);
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sim_printf(" IRR=%02X", i8259_unit[devnum].u3);
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sim_printf(" ISR=%02X", i8259_unit[devnum].u4);
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sim_printf(" IMR=%02X", i8259_unit[devnum].u5);
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sim_printf(" ICW1=%02X", i8259_icw1[devnum]);
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sim_printf(" ICW2=%02X", i8259_icw2[devnum]);
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sim_printf(" ICW3=%02X", i8259_icw3[devnum]);
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sim_printf(" ICW4=%02X", i8259_icw4[devnum]);
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sim_printf(" OCW1=%02X", i8259_ocw1[devnum]);
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sim_printf(" OCW2=%02X", i8259_ocw2[devnum]);
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sim_printf(" OCW3=%02X\n", i8259_ocw3[devnum]);
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}
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/* end of i8259.c */
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