84bf5f4d14
This change updates the 3B2 README.md file, and fixes all line endings on 3B2 source files.
346 lines
8.4 KiB
C
346 lines
8.4 KiB
C
/* 3b2_mem.c: Memory Map Access Routines
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Copyright (c) 2021-2022, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#include "3b2_mem.h"
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#include "3b2_cpu.h"
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#include "3b2_csr.h"
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#include "3b2_io.h"
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#include "3b2_mmu.h"
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#include "3b2_stddev.h"
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#include "3b2_dmac.h"
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#if defined(REV3)
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static uint32 ecc_addr; /* ECC address */
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static t_bool ecc_err; /* ECC multi-bit error */
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#endif
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/*
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* ECC is simulated just enough to pass diagnostics, and no more.
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*
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* Checking and setting of ECC syndrome bits is a no-op for Rev 2.
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*/
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static SIM_INLINE void check_ecc(uint32 pa, t_bool write, uint8 src)
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{
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#if defined(REV3)
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/* Force ECC Syndrome mode enables a diagnostic mode on the AM2960
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data correction ICs */
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if (write && !CSR(CSRFECC)) {
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sim_debug(EXECUTE_MSG, &mmu_dev,
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"ECC Error on Write. pa=%08x\n",
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pa);
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ecc_addr = pa;
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ecc_err = TRUE;
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} else if (ecc_err && !write && pa == ecc_addr) {
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sim_debug(EXECUTE_MSG, &mmu_dev,
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"ECC Error detected on Read. pa=%08x psw=%08x cur_ipl=%d csr=%08x\n",
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pa, R[NUM_PSW], PSW_CUR_IPL, csr_data);
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flt[0] = ecc_addr & 0x3ffff;
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flt[1] = MA_CPU_IO|MA_CPU_BU;
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ecc_err = FALSE;
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CSRBIT(CSRFRF, TRUE); /* Fault registers frozen */
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CSRBIT(CSRMBERR, TRUE); /* Multi-bit error */
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CPU_SET_INT(INT_MBERR);
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/* Only abort if CPU is doing the read */
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if (src == BUS_CPU) {
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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}
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#endif
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}
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/* Read Word (Physical Address) */
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uint32 pread_w(uint32 pa, uint8 src)
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{
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uint8 *m;
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uint32 index = 0;
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#if defined(REV3)
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if ((pa & 3) && (R[NUM_PSW] & PSW_EA_MASK) == 0) {
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#else
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if (pa & 3) {
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#endif
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sim_debug(READ_MSG, &mmu_dev,
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"Cannot read physical address. ALIGNMENT ISSUE: %08x\n",
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pa);
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CSRBIT(CSRALGN, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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if (IS_IO(pa)) {
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return io_read(pa, 32);
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}
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if (IS_ROM(pa)) {
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m = ROM;
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index = pa;
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} else if (IS_RAM(pa)) {
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check_ecc(pa, FALSE, src);
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m = RAM;
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index = (pa - PHYS_MEM_BASE);
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} else {
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return 0;
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}
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return ATOW(m, index);
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}
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/*
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* Write Word (Physical Address)
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*/
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void pwrite_w(uint32 pa, uint32 val, uint8 src)
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{
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uint32 index;
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if (pa & 3) {
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sim_debug(WRITE_MSG, &mmu_dev,
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"Cannot write physical address. ALIGNMENT ISSUE: %08x\n",
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pa);
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CSRBIT(CSRALGN, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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if (IS_IO(pa)) {
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io_write(pa, val, 32);
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return;
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}
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if (IS_RAM(pa)) {
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check_ecc(pa, TRUE, src);
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index = pa - PHYS_MEM_BASE;
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RAM[index] = (val >> 24) & 0xff;
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RAM[index + 1] = (val >> 16) & 0xff;
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RAM[index + 2] = (val >> 8) & 0xff;
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RAM[index + 3] = val & 0xff;
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return;
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}
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}
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/*
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* Read Halfword (Physical Address)
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*/
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uint16 pread_h(uint32 pa, uint8 src)
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{
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uint8 *m;
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uint32 index;
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if (pa & 1) {
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sim_debug(READ_MSG, &mmu_dev,
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"Cannot read physical address. ALIGNMENT ISSUE %08x\n",
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pa);
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CSRBIT(CSRALGN, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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if (IS_IO(pa)) {
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return (uint16) io_read(pa, 16);
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}
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if (IS_ROM(pa)) {
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m = ROM;
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index = pa;
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} else if (IS_RAM(pa)) {
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check_ecc(pa, FALSE, src);
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m = RAM;
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index = pa - PHYS_MEM_BASE;
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} else {
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return 0;
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}
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return ATOH(m, index);
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}
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/*
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* Write Halfword (Physical Address)
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*/
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void pwrite_h(uint32 pa, uint16 val, uint8 src)
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{
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uint32 index;
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#if defined(REV3)
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if ((pa & 1) && (R[NUM_PSW] & PSW_EA_MASK) == 0) {
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#else
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if (pa & 1) {
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#endif
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sim_debug(WRITE_MSG, &mmu_dev,
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"Cannot write physical address %08x, ALIGNMENT ISSUE\n",
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pa);
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CSRBIT(CSRALGN, TRUE);
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}
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if (IS_IO(pa)) {
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io_write(pa, val, 16);
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return;
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}
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if (IS_RAM(pa)) {
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check_ecc(pa, TRUE, src);
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index = pa - PHYS_MEM_BASE;
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RAM[index] = (val >> 8) & 0xff;
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RAM[index + 1] = val & 0xff;
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return;
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}
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}
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/*
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* Read Byte (Physical Address)
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*/
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uint8 pread_b(uint32 pa, uint8 src)
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{
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if (IS_IO(pa)) {
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return (uint8)(io_read(pa, 8));
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}
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if (IS_ROM(pa)) {
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return ROM[pa];
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} else if (IS_RAM(pa)) {
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check_ecc(pa, FALSE, src);
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return RAM[pa - PHYS_MEM_BASE];
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} else {
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return 0;
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}
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}
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/* Write Byte (Physical Address) */
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void pwrite_b(uint32 pa, uint8 val, uint8 src)
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{
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uint32 index;
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if (IS_IO(pa)) {
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io_write(pa, val, 8);
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return;
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}
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if (IS_RAM(pa)) {
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check_ecc(pa, TRUE, src);
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index = pa - PHYS_MEM_BASE;
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RAM[index] = val;
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return;
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}
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}
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/* Write to ROM (used by ROM load) */
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void pwrite_b_rom(uint32 pa, uint8 val) {
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if (IS_ROM(pa)) {
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ROM[pa] = val;
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}
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}
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/* Read Byte (Virtual Address) */
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uint8 read_b(uint32 va, uint8 r_acc, uint8 src)
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{
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return pread_b(mmu_xlate_addr(va, r_acc), src);
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}
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/* Write Byte (Virtual Address) */
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void write_b(uint32 va, uint8 val, uint8 src)
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{
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pwrite_b(mmu_xlate_addr(va, ACC_W), val, src);
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}
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/* Read Halfword (Virtual Address) */
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uint16 read_h(uint32 va, uint8 r_acc, uint8 src)
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{
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return pread_h(mmu_xlate_addr(va, r_acc), src);
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}
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/* Write Halfword (Virtual Address) */
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void write_h(uint32 va, uint16 val, uint8 src)
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{
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pwrite_h(mmu_xlate_addr(va, ACC_W), val, src);
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}
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/* Read Word (Virtual Address) */
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uint32 read_w(uint32 va, uint8 r_acc, uint8 src)
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{
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return pread_w(mmu_xlate_addr(va, r_acc), src);
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}
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/* Write Word (Virtual Address) */
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void write_w(uint32 va, uint32 val, uint8 src)
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{
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pwrite_w(mmu_xlate_addr(va, ACC_W), val, src);
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}
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t_stat read_operand(uint32 va, uint8 *val)
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{
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uint32 pa;
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t_stat succ;
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succ = mmu_decode_va(va, ACC_IF, TRUE, &pa);
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if (succ == SCPE_OK) {
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*val = pread_b(pa, BUS_CPU);
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} else {
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*val = 0;
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}
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return succ;
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}
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t_stat examine(uint32 va, uint8 *val)
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{
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uint32 pa;
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t_stat succ;
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succ = mmu_decode_va(va, 0, FALSE, &pa);
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if (succ == SCPE_OK) {
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if (IS_ROM(pa) || IS_RAM(pa)) {
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*val = pread_b(pa, BUS_CPU);
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return SCPE_OK;
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} else {
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*val = 0;
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return SCPE_NXM;
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}
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} else {
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*val = 0;
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return succ;
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}
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}
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t_stat deposit(uint32 va, uint8 val)
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{
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uint32 pa;
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t_stat succ;
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succ = mmu_decode_va(va, 0, FALSE, &pa);
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if (succ == SCPE_OK) {
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if (IS_RAM(pa)) {
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pwrite_b(pa, val, BUS_CPU);
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return SCPE_OK;
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} else {
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return SCPE_NXM;
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}
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} else {
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return succ;
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}
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}
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