1a3e5af755
Refactor in preparation for the addition of a Rev 3 simulator for the
3B2/1000 system.
This change also includes a full cleanup of the rat's-nest of includes
and externs that plagued the 3B2 simulator and made it difficult to
understand and maintain. Headers are now required in the following
order:
compilation unit -> "3b2_defs.h" -> {... dependencies ...}
Finally, HELP has been added to the CPU device.
111 lines
3.9 KiB
C
111 lines
3.9 KiB
C
/* 3b2_400_defs.h: AT&T 3B2 Model 400 Simulator Definitions
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Copyright (c) 2017, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#ifndef _3B2_400_DEFS_H_
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#define _3B2_400_DEFS_H_
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#include "sim_defs.h"
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#define MAXMEMSIZE (1 << 22) /* 4 MB */
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#define TODBASE 0x41000
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#define TODSIZE 0x40
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#define TIMERBASE 0x42000
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#define TIMERSIZE 0x20
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#define NVRAMBASE 0x43000
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#define NVRAMSIZE 0x1000
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#define CSRBASE 0x44000
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#define CSRSIZE 0x100
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#define IFBASE 0x4d000
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#define IFSIZE 0x10
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#define IDBASE 0x4a000
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#define IDSIZE 0x2
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#define IF_STATUS_REG 0
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#define IF_CMD_REG 0
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#define IF_TRACK_REG 1
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#define IF_SECTOR_REG 2
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#define IF_DATA_REG 3
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#define ID_DATA_REG 0
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#define ID_CMD_STAT_REG 1
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/* CSR Flags */
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#define CSRTIMO 0x8000 /* Bus Timeout Error */
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#define CSRPARE 0x4000 /* Memory Parity Error */
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#define CSRRRST 0x2000 /* System Reset Request */
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#define CSRALGN 0x1000 /* Memory Alignment Fault */
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#define CSRLED 0x0800 /* Failure LED */
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#define CSRFLOP 0x0400 /* Floppy Motor On */
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#define CSRRES 0x0200 /* Reserved */
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#define CSRITIM 0x0100 /* Inhibit Timers */
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#define CSRIFLT 0x0080 /* Inhibit Faults */
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#define CSRCLK 0x0040 /* Clock Interrupt */
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#define CSRPIR8 0x0020 /* Programmed Interrupt 8 */
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#define CSRPIR9 0x0010 /* Programmed Interrupt 9 */
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#define CSRUART 0x0008 /* UART Interrupt */
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#define CSRDISK 0x0004 /* Floppy Interrupt */
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#define CSRDMA 0x0002 /* DMA Interrupt */
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#define CSRIOF 0x0001 /* I/O Board Fail */
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#define MEMSIZE_REG 0x4C003
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/* DMA Controller */
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#define DMACBASE 0x48000
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#define DMACSIZE 0x11
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/* DMA integrated disk page buffer */
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#define DMAIDBASE 0x45000
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#define DMAIDSIZE 0x5
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/* DMA integrated uart A page buffer */
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#define DMAIUABASE 0x46000
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#define DMAIUASIZE 0x5
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/* DMA integrated uart B page buffer */
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#define DMAIUBBASE 0x47000
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#define DMAIUBSIZE 0x5
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/* DMA integrated floppy page buffer */
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#define DMAIFBASE 0x4E000
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#define DMAIFSIZE 0x5
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#define DMA_ID_CHAN 0
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#define DMA_IF_CHAN 1
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#define DMA_IUA_CHAN 2
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#define DMA_IUB_CHAN 3
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#define DMA_ID 0x45
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#define DMA_IUA 0x46
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#define DMA_IUB 0x47
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#define DMA_C 0x48
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#define DMA_IF 0x4E
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#endif /* _3B2_400_DEFS_H_ */
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