a5feaf2815
- Add 1752 Drum support. Allow shared subroutines across interrupt levels. - Document and add sample scripts for customizing MSOS5.
372 lines
11 KiB
C
372 lines
11 KiB
C
/*
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Copyright (c) 2015-2016, John Forecast
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JOHN FORECAST BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of John Forecast shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from John Forecast.
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*/
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/* cdc1700_rtc.c: 10336-1 Real-time clock support
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* Simh devices: rtc
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*/
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#include "cdc1700_defs.h"
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#define HOLDREG iod_writeR[0] /* Holding register */
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#define COUNTER iod_readR[1] /* Counter */
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extern char INTprefix[];
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extern t_stat checkReset(DEVICE *, uint8);
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extern t_stat show_addr(FILE *, UNIT *, int32, CONST void *);
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extern t_stat set_equipment(UNIT *, int32, CONST char *, void *);
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extern void RaiseExternalInterrupt(DEVICE *);
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extern void rebuildPending(void);
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extern uint16 Areg;
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extern t_bool IOFWinitialized;
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t_stat rtc_show_rate(FILE *, UNIT *, int32, CONST void *);
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t_stat rtc_set_rate(UNIT *, int32, CONST char *, void *);
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void RTCstate(char *, DEVICE *, IO_DEVICE *);
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uint16 RTCraised(DEVICE *);
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enum IOstatus RTCin(IO_DEVICE *, uint8);
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enum IOstatus RTCout(IO_DEVICE *, uint8);
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t_stat rtc_svc(UNIT *);
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t_stat rtc_reset(DEVICE *);
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t_stat rtc_help(FILE *, DEVICE *, UNIT *, int32, const char *);
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/*
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10336-1 Real-Time Clock
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Addresses
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Computer Instruction
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Q Register Output From A Input to A
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(Bits 01-00)
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00 Load Register
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01 Director Function Read Counter
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Operations:
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Director Function 1
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15 14 7 6 1 0
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+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
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| | | X | X | X | X | X | X | | | X | X | X | X | | |
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+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
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| | | | | |
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| | | | | Clr Controller
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| | | | Ack. Interrupt
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| | | Stop Clock
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| | Start Clock
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| Disable Interrupt
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Enable Interrupt
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The counter and register values are unsigned 16-bit values.
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*/
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IO_DEVICE RTCdev = IODEV(NULL, "10336-1", 10336, 13, 0xFF, 0,
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NULL, RTCin, RTCout, NULL, NULL,
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NULL, NULL, RTCraised, NULL, NULL, NULL,
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0x7F, 2,
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MASK_REGISTER0 | MASK_REGISTER1,
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MASK_REGISTER1,
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MASK_REGISTER0, 0,
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AQ_ONLY, 0, NULL);
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/*
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* Define usage for "private" IO_DEVICE data areas.
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*/
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#define iod_RTCstate iod_private
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#define iod_RTCraised iod_private4
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/*
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* Current state of the device.
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*/
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#define IODP_RTCIDLE 0x0000
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#define IODP_RTCRUNNING 0x0001
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#define IODP_RTCINTR 0x0002
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/*
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* The RTC operates at a user determined frequency (via a jumper plug).
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* Basic time periods are:
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*
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* 1 uSec, 10 uSec, 100 uSec, 1 mSec, 10 mSec, 100 mSec and 1 second.
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*
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* We use CPU instruction execution as a proxy for generating these
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* frequencies. If we assume an average execution time of 1.25 uSec (1784-2
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* processor), each time period will be represented by the following
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* instruction counts:
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*
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* 1, 8, 80, 800, 8000, 80000, 800000
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*/
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#define RTC_1USEC 1
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#define RTC_10USEC 8
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#define RTC_100USEC 80
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#define RTC_1MSEC 800
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#define RTC_10MSEC 8000
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#define RTC_100MSEC 80000
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#define RTC_1SEC 800000
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struct RTCtimebase {
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const char *name;
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const char *rate;
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int32 icount;
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} timeBase[] = {
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{ "1USEC", "1 uSec", RTC_1USEC },
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{ "10USEC", "10 uSec", RTC_10USEC },
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{ "100USEC", "100 uSec", RTC_100USEC },
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{ "1MSEC", "1 mSec", RTC_1MSEC },
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{ "10MSEC", "10 mSec", RTC_10MSEC },
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{ "100MSEC", "100 mSec", RTC_100MSEC },
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{ "1SEC", "1 Seccond", RTC_1SEC },
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{ NULL }
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};
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/* RTC data structures
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rtc_dev RTC device descriptor
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rtc_unit RTC unit descriptor
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rtc_reg RTC register list
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rtc_mod RTC modifiers list
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*/
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UNIT rtc_unit = {
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UDATA(&rtc_svc, 0, 0), RTC_10USEC
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};
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REG rtc_reg[] = {
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{ HRDATAD(FUNCTION, RTCdev.FUNCTION, 16, "Last director function issued") },
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{ HRDATAD(COUNTER, RTCdev.COUNTER, 16, "Counter register") },
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{ HRDATAD(HOLDING, RTCdev.HOLDREG, 16, "Hold register") },
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{ NULL }
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};
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MTAB rtc_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "10336-1 Real Time Clock" },
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{ MTAB_XTD|MTAB_VDV, 0, "EQUIPMENT", "EQUIPMENT=hexAddress",
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&set_equipment, &show_addr, NULL, "Display equipment address" },
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{ MTAB_XTD|MTAB_VDV, 0, "RATE", "RATE={1usec|10usec|100usec|1msec|10msec|100msec|1second}",
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&rtc_set_rate, &rtc_show_rate, NULL, "Show timer tick interval" },
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{ 0 }
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};
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DEBTAB rtc_deb[] = {
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{ "TRACE", DBG_DTRACE, "Trace device I/O requests" },
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{ NULL }
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};
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DEVICE rtc_dev = {
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"RTC", &rtc_unit, rtc_reg, rtc_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &rtc_reset,
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NULL, NULL, NULL,
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&RTCdev,
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DEV_DEBUG | DEV_DISABLE, 0, rtc_deb,
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NULL, NULL, &rtc_help, NULL, NULL, NULL
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};
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t_stat rtc_show_rate(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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struct RTCtimebase *tb = timeBase;
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while (tb->name != NULL) {
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if (tb->icount == rtc_unit.wait) {
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fprintf(st, "Timebase rate: %s", tb->rate);
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return SCPE_OK;
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}
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tb++;
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}
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return SCPE_IERR;
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}
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t_stat rtc_set_rate(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (cptr) {
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struct RTCtimebase *tb = timeBase;
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while (tb->name != NULL) {
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if (!strcmp(cptr, tb->name)) {
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rtc_unit.wait = tb->icount;
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return SCPE_OK;
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}
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tb++;
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}
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}
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return SCPE_IERR;
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}
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/*
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* Determine if the clock interrupt is asserted, returning the appropriate
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* interrupt bit or 0.
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*/
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uint16 RTCraised(DEVICE *dptr)
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{
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IO_DEVICE *iod = (IO_DEVICE *)dptr->ctxt;
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return iod->iod_RTCraised ? iod->iod_interrupt : 0;
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}
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/* Unit service */
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t_stat rtc_svc(UNIT *uptr)
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{
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if (RTCdev.iod_RTCstate != IODP_RTCIDLE) {
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if ((RTCdev.iod_RTCstate & IODP_RTCRUNNING) != 0) {
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RTCdev.COUNTER++;
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if ((RTCdev.iod_RTCstate & IODP_RTCINTR) != 0) {
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if (RTCdev.COUNTER == RTCdev.HOLDREG) {
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RTCdev.COUNTER = 0;
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RTCdev.iod_RTCraised = TRUE;
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RaiseExternalInterrupt(&rtc_dev);
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}
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}
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sim_activate(&rtc_unit, rtc_unit.wait);
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}
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}
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat rtc_reset(DEVICE * dptr)
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{
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t_stat r;
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if (IOFWinitialized)
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if ((dptr->flags & DEV_DIS) == 0)
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if ((r = checkReset(dptr, RTCdev.iod_equip)) != SCPE_OK)
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return r;
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RTCdev.iod_RTCstate = IODP_RTCIDLE;
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RTCdev.iod_RTCraised = FALSE;
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return SCPE_OK;
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}
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/* Perform I/O */
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enum IOstatus RTCin(IO_DEVICE *iod, uint8 reg)
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{
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/*
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* The framework only passes IN operations for the data register.
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*/
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return IO_REJECT;
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}
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enum IOstatus RTCout(IO_DEVICE *iod, uint8 reg)
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{
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switch (reg) {
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case 0x00:
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RTCdev.HOLDREG = Areg;
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break;
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case 0x01:
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/*
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* Check for illegal bit combinations
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*/
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if (((Areg & (IO_10336_ENA | IO_10336_DIS)) ==
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(IO_10336_ENA | IO_10336_DIS)) ||
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((Areg & (IO_10336_START | IO_10336_STOP)) ==
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(IO_10336_START | IO_10336_STOP)))
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return IO_REJECT;
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if ((Areg & IO_DIR_CCONT) != 0) {
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sim_cancel(&rtc_unit);
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RTCdev.iod_RTCstate = IODP_RTCIDLE;
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RTCdev.iod_RTCraised = FALSE;
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rebuildPending();
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RTCdev.HOLDREG = 0;
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RTCdev.COUNTER = 0;
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}
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if ((Areg & IO_10336_STOP) != 0) {
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RTCdev.iod_RTCstate &= ~IODP_RTCRUNNING;
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sim_cancel(&rtc_unit);
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}
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if ((Areg & IO_10336_START) != 0) {
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RTCdev.COUNTER = 0;
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RTCdev.iod_RTCstate |= IODP_RTCRUNNING;
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sim_activate(&rtc_unit, rtc_unit.wait);
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}
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if ((Areg & IO_10336_ACK) != 0) {
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RTCdev.iod_RTCraised = FALSE;
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rebuildPending();
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}
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if ((Areg & IO_10336_DIS) != 0) {
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RTCdev.iod_RTCstate &= ~IODP_RTCINTR;
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RTCdev.iod_RTCraised = FALSE;
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rebuildPending();
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}
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if ((Areg & IO_10336_ENA) != 0)
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RTCdev.iod_RTCstate |= IODP_RTCINTR;
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break;
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}
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return IO_REPLY;
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}
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t_stat rtc_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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const char helpString[] =
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/****************************************************************************/
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" The %D device 10336-1 Real Time Clock.\n"
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"1 Hardware Description\n"
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" The 10336-1 is a Real Time Clock which can generate periodic interrupts\n"
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" or measure elapsed time. The timer resolution is set via jumpers on the\n"
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" physical hardware. For the simulator, the default resolution is\n"
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" 10 uSec and can be changed by:\n\n"
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"+sim> SET %D RATE=1usec\n"
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"+sim> SET %D RATE=10usec\n"
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"+sim> SET %D RATE=100usec\n"
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"+sim> SET %D RATE=1msec\n"
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"+sim> SET %D RATE=10msec\n"
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"+sim> SET %D RATE=100msec\n"
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"+sim> SET %D RATE=1second\n\n"
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"2 Equipment Address\n"
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" The %D device is set to equipment address 13. This address may be\n"
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" changed by:\n\n"
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"+sim> SET %D EQUIPMENT=hexValue\n\n"
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"2 $Registers\n"
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"\n"
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" These registers contain the emulated state of the device. These values\n"
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" don't necessarily relate to any detail of the original device being\n"
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" emulated but are merely internal details of the emulation.\n"
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"1 Configuration\n"
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" A %D device is configured with various simh SET commands\n"
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"2 $Set commands\n";
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return scp_help(st, dptr, uptr, flag, helpString, cptr);
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}
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