621e97e170
- Different VAX models had different groups of instructions which were implemented in hardware vs trappng to the OS for emulation. Functionality has been added to differentiate the various mix of instruction groups for different models and to display both the groups and the actual instructions. - Visibility to Instruction groups is provided by SHOW CPU INSTRUCTIONS and the list of the active instructions implemented and emulated via SHOW CPU -V INSTRUCTIONS. - The MicroVAX I CPU handled some execution fault conditions differently from other VAX systems these differences are now specifically handled. - Add build time test support to MicroVAX I running EHKAA v1.13 suggested in #683 - Add more CPU debug details relating to exception and interrupt processing
286 lines
12 KiB
C
286 lines
12 KiB
C
/* is1000_defs.h: InfoServer 1000 model-specific definitions file
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Copyright (c) 2019, Matt Burke
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This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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This file covers the InfoServer 1000.
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System memory map
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0000 0000 - 003F FFFF main memory
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0040 0000 - 2003 FFFF reserved
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2004 0000 - 2007 FFFF ROM space
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2008 0000 - 20FF FFFF reserved
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2100 0000 - 2100 0008 network controller
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2100 0020 - 2100 0024 configuration/test register
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2200 0000 - 2200 00C0 scsi controller
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2300 0000 - 2300 xxxx watch chip registers
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2400 0000 - 2400 xxxx local register space
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2400 0060 - 2400 0070 serial line controller
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3002 0000 - 3FFF FFFF reserved
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*/
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#ifdef FULL_VAX /* subset VAX */
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#undef FULL_VAX
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#endif
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#ifndef _IS_1000_DEFS_H_
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#define _IS_1000_DEFS_H_ 1
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/* Microcode constructs */
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#define CVAX_SID (10 << 24) /* system ID */
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#define CVAX_UREV 6 /* ucode revision */
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#define CON_HLTPIN 0x0200 /* external CPU halt */
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#define CON_PWRUP 0x0300 /* powerup code */
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#define CON_HLTINS 0x0600 /* HALT instruction */
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#define CON_DBLMCK 0x0500 /* Machine check in machine check */
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#define CON_BADPSL 0x4000 /* invalid PSL flag */
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#define CON_MAPON 0x8000 /* mapping on flag */
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#define MCHK_READ 0x80 /* read check */
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#define MCHK_WRITE 0x82 /* write check */
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/* Machine specific IPRs */
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#define MT_CADR 37 /* Cache disable reg */
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#define MT_MCESR 38 /* Machine check error/status reg */
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#define MT_CAER 39 /* Cache error reg */
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#define MT_ACCS 40 /* FPA control */
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#define MT_CONISP 41 /* Console Saved ISP */
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#define MT_CONPC 42 /* Console Saved PC */
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#define MT_CONPSL 43 /* Console Saved PSL */
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#define MT_MAX 127 /* last valid IPR */
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/* Cache disable register */
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#define CADR_RW 0xF3
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#define CADR_MBO 0x0C
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/* CPU */
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#define CPU_MODEL_MODIFIERS
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/* Memory */
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#define MAXMEMWIDTH 22 /* max mem, std KA420 */
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#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */
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#define MAXMEMWIDTH_X 22 /* max mem, KA420 */
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#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)
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#define INITMEMSIZE (1 << 24) /* initial memory size */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
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#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }
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/* Read only memory */
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#define ROMAWIDTH 19 /* ROM addr width */
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#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */
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#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */
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#define ROMBASE 0x20040000 /* ROM base */
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#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \
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(((uint32) (x)) < (ROMBASE + ROMSIZE)))
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/* LANCE Ethernet controller */
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#define XSSIZE 0x8 /* XS length */
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#define XSBASE 0x21000000 /* XS base */
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/* Config/test register */
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#define CFGSIZE 4 /* CFG length */
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#define CFGBASE 0x21000020 /* CFG base */
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/* SCSI disk controller */
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#define RZSIZE 0xC0 /* RZ length */
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#define RZBASE 0x22000000 /* RZ base */
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/* Non-volatile RAM - 32KB Bytes long */
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#define NVRAWIDTH 15 /* NVR addr width */
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#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */
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#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */
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#define NVRBASE 0x23000000 /* NVR base */
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#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \
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(((uint32) (x)) < (NVRBASE + NVRSIZE)))
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/* IS1000 board registers */
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#define KASIZE 0x60 /* REG length */
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#define KABASE 0x24000000 /* REG addr base */
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/* Serial line controller */
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#define DZSIZE 0x10 /* DZ length */
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#define DZBASE 0x24000060 /* DZ base */
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/* Network address ROM */
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#define NARAWIDTH 5 /* NAR addr width */
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#define NARSIZE (1u << NARAWIDTH) /* NAR length */
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#define NARAMASK (NARSIZE - 1) /* NAR addr mask */
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/* Other address spaces */
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#define ADDR_IS_IO(x) (0)
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#define ADDR_IS_CDG(x) (0)
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/* Machine specific reserved operand tests (mostly NOPs) */
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#define ML_PA_TEST(r)
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#define ML_LR_TEST(r)
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#define ML_SBR_TEST(r)
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#define ML_PXBR_TEST(r)
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#define LP_AST_TEST(r)
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
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/* Common CSI flags */
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#define CSR_V_GO 0 /* go */
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#define CSR_V_IE 6 /* interrupt enable */
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#define CSR_V_DONE 7 /* done */
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#define CSR_V_BUSY 11 /* busy */
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#define CSR_V_ERR 15 /* error */
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#define CSR_GO (1u << CSR_V_GO)
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#define CSR_IE (1u << CSR_V_IE)
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#define CSR_DONE (1u << CSR_V_DONE)
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#define CSR_BUSY (1u << CSR_V_BUSY)
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#define CSR_ERR (1u << CSR_V_ERR)
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/* Timers */
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#define TMR_CLK 0 /* 100Hz clock */
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/* SCSI Bus */
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#define RZ_SCSI_ID 6 /* initiator SCSI id */
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/* I/O system definitions */
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#define MT_MAXFR (1 << 16) /* magtape max rec */
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#define DEV_V_4XX (DEV_V_UF + 0) /* KA4xx I/O */
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#define DEV_4XX (1u << DEV_V_4XX)
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#define DEV_RDX 16 /* default device radix */
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/* Device information block */
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#define VEC_DEVMAX 4 /* max device vec */
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typedef struct {
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int32 rom_index; /* option ROM index */
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uint8 *rom_array; /* option ROM code */
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t_addr rom_size; /* option ROM size */
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} DIB;
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/* Within each IPL, priority is left to right */
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/* IPL 14 */
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#define INT_V_SC 0 /* storage controller */
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#define INT_V_XS1 1 /* network */
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#define INT_V_DZTX 2 /* serial transmitter */
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#define INT_V_DZRX 3 /* serial receiver */
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#define INT_V_PE 6 /* parity error */
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#define INT_SC (1u << INT_V_SC)
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#define INT_XS1 (1u << INT_V_XS1)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_PE (1u << INT_V_PE)
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#define IPL_CLK 0x16
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#define IPL_HW 0x14 /* hwre level */
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#define IPL_SC (0x14 - IPL_HMIN)
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#define IPL_XS1 (0x14 - IPL_HMIN)
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#define IPL_DZTX (0x14 - IPL_HMIN)
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#define IPL_DZRX (0x14 - IPL_HMIN)
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#define IPL_HMIN IPL_HW
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#define IPL_HMAX IPL_HW
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#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
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#define IPL_SMAX 0xF /* highest swre level */
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/* Device vectors */
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#define VEC_QBUS 0 /* Not a Qbus system */
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#define VEC_Q 0
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/* Interrupt macros */
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#define IREQ(dv) int_req[0]
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#define SET_INT(dv) int_req[0] = int_req[0] | (INT_##dv)
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#define CLR_INT(dv) int_req[0] = int_req[0] & ~(INT_##dv)
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
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/* System model */
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extern int32 sys_model;
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/* Machine specific definitions - DZ */
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#define DZ_L3C 1 /* line 3 console */
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/* Machine specific definitions - RZ94 */
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#define RZ_READB(ba,bc,buf) Map_ReadB(ba, bc, buf, TRUE)
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#define RZ_READW(ba,bc,buf) Map_ReadW(ba, bc, buf, TRUE)
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#define RZ_WRITEB(ba,bc,buf) Map_WriteB(ba, bc, buf, TRUE)
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#define RZ_WRITEW(ba,bc,buf) Map_WriteW(ba, bc, buf, TRUE)
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/* Machine specific definitions - XS */
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#define XS_ROM_INDEX -1 /* no ROM needed */
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#define XS_FLAGS 0
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#define XS_READB(ba,bc,buf) Map_ReadB(ba, bc, buf, FALSE)
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#define XS_READW(ba,bc,buf) Map_ReadW(ba, bc, buf, FALSE)
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#define XS_WRITEB(ba,bc,buf) Map_WriteB(ba, bc, buf, FALSE)
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#define XS_WRITEW(ba,bc,buf) Map_WriteW(ba, bc, buf, FALSE)
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#define XS_ADRMBO (0)
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/* Function prototypes for I/O */
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf, t_bool map);
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf, t_bool map);
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int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf, t_bool map);
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int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf, t_bool map);
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/* Function prototypes for system-specific unaligned support */
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int32 ReadIOU (uint32 pa, int32 lnt);
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int32 ReadRegU (uint32 pa, int32 lnt);
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void WriteIOU (uint32 pa, int32 val, int32 lnt);
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void WriteRegU (uint32 pa, int32 val, int32 lnt);
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t_stat auto_config (const char *name, int32 nctrl);
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/* Function prototypes for virtual and physical memory interface (inlined) */
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#include "vax_mmu.h"
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#endif
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