84bf5f4d14
This change updates the 3B2 README.md file, and fixes all line endings on 3B2 source files.
772 lines
26 KiB
C
772 lines
26 KiB
C
/* 3b2_io.c: Common I/O (CIO) Feature Card Support
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Copyright (c) 2017-2022, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#include "3b2_io.h"
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#include "3b2_cpu.h"
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#include "3b2_csr.h"
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#include "3b2_dmac.h"
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#include "3b2_if.h"
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#include "3b2_iu.h"
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#include "3b2_mem.h"
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#include "3b2_mmu.h"
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#include "3b2_stddev.h"
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#include "3b2_timer.h"
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#if defined(REV2)
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#include "3b2_id.h"
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#endif
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CIO_STATE cio[CIO_SLOTS] = {{0}};
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uint16 cio_int_req = 0; /* Bitset of card slots requesting interrupts */
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#if defined(REV3)
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iolink iotable[] = {
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{ MMUBASE, MMUBASE+MMUSIZE, &mmu_read, &mmu_write },
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{ IFBASE, IFBASE+IFSIZE, &if_read, &if_write },
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{ IFCSRBASE, IFCSRBASE+IFCSRSIZE, &if_csr_read, &if_csr_write },
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{ FLTLBASE, FLTLBASE+FLTLSIZE, &flt_read, &flt_write },
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{ FLTHBASE, FLTHBASE+FLTHSIZE, &flt_read, &flt_write },
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{ NVRBASE, NVRBASE+NVRSIZE, &nvram_read, &nvram_write },
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{ TIMERBASE, TIMERBASE+TIMERSIZE, &timer_read, &timer_write },
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{ CSRBASE, CSRBASE+CSRSIZE, &csr_read, &csr_write },
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{ IUBASE, IUBASE+IUSIZE, &iu_read, &iu_write },
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{ DMAIUABASE, DMAIUABASE+DMAIUASIZE, &dmac_read, &dmac_write },
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{ DMAIUBBASE, DMAIUBBASE+DMAIUBSIZE, &dmac_read, &dmac_write },
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{ DMACBASE, DMACBASE+DMACSIZE, &dmac_read, &dmac_write },
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{ DMAIFBASE, DMAIFBASE+DMAIFSIZE, &dmac_read, &dmac_write },
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{ TODBASE, TODBASE+TODSIZE, &tod_read, &tod_write },
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{ 0, 0, NULL, NULL}
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};
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#else
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iolink iotable[] = {
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{ MMUBASE, MMUBASE+MMUSIZE, &mmu_read, &mmu_write },
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{ IFBASE, IFBASE+IFSIZE, &if_read, &if_write },
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{ IDBASE, IDBASE+IDSIZE, &id_read, &id_write },
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{ DMAIDBASE, DMAIDBASE+DMAIDSIZE, &dmac_read, &dmac_write },
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{ NVRBASE, NVRBASE+NVRSIZE, &nvram_read, &nvram_write },
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{ TIMERBASE, TIMERBASE+TIMERSIZE, &timer_read, &timer_write },
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{ CSRBASE, CSRBASE+CSRSIZE, &csr_read, &csr_write },
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{ IUBASE, IUBASE+IUSIZE, &iu_read, &iu_write },
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{ DMAIUABASE, DMAIUABASE+DMAIUASIZE, &dmac_read, &dmac_write },
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{ DMAIUBBASE, DMAIUBBASE+DMAIUBSIZE, &dmac_read, &dmac_write },
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{ DMACBASE, DMACBASE+DMACSIZE, &dmac_read, &dmac_write },
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{ DMAIFBASE, DMAIFBASE+DMAIFSIZE, &dmac_read, &dmac_write },
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{ TODBASE, TODBASE+TODSIZE, &tod_read, &tod_write },
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{ 0, 0, NULL, NULL}
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};
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#endif
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/*
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* Insert a CIO card into the backplane.
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*
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* If a space could be found, SPCE_OK is returned, and the slot the
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* card was installed in is placed in `slot`.
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*
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* If no room is availalbe, return SCPE_NXM.
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*/
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t_stat cio_install(uint16 id,
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CONST char *name,
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uint8 ipl,
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void (*exp_handler)(uint8 slot),
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void (*full_handler)(uint8 slot),
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void (*sysgen)(uint8 slot),
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void (*reset_handler)(uint8 slot),
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uint8 *slot)
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{
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uint8 s;
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for (s = 0; s < CIO_SLOTS; s++) {
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sim_debug(EXECUTE_MSG, &cpu_dev,
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"[cio_install] cio[%d]: populated=%d, id=%d\n",
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s, cio[s].populated, cio[s].id);
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if (!cio[s].populated) {
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sim_debug(EXECUTE_MSG, &cpu_dev,
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"[cio_install] >>> I found a free slot! Slot #%d has nothing\n", s);
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*slot = s;
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/* Ensure the slot is in a clean state */
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cio_remove(s);
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/* Populate the slot */
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cio[s].populated = TRUE;
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cio[s].id = id;
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cio[s].ipl = ipl;
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strncpy(cio[s].name, name, CIO_NAME_LEN);
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cio[s].exp_handler = exp_handler;
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cio[s].full_handler = full_handler;
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cio[s].sysgen = sysgen;
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cio[s].reset_handler = reset_handler;
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return SCPE_OK;
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}
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}
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return SCPE_NXM;
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}
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/*
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* Remove a CIO card from the specified backplane slot.
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*/
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void cio_remove(uint8 slot)
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{
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memset(&cio[slot], 0, sizeof(CIO_STATE));
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/* cio[slot].populated = FALSE; */
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CIO_CLR_INT(slot);
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}
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/*
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* Remove all CIO cards of the matching type.
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*/
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void cio_remove_all(uint16 id)
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{
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int i;
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for (i = 0; i < CIO_SLOTS; i++) {
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if (cio[i].populated && cio[i].id == id) {
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cio_remove(i);
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}
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}
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}
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/*
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* A braindead CRC32 calculator.
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*
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* This is overkill for what we need: A simple way to tag the contents
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* of a block of memory uploaded to a CIO card (so we can
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* differentiate between desired functions without actually having to
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* disassemble and understand 80186 code!)
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*/
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uint32 cio_crc32_shift(uint32 crc, uint8 data)
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{
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uint8 i;
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crc = ~crc;
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crc ^= data;
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for (i = 0; i < 8; i++) {
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if (crc & 1) {
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crc = (crc >> 1) ^ CRC_POLYNOMIAL;
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} else {
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crc = crc >> 1;
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}
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}
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return ~crc;
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}
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void cio_sysgen(uint8 slot)
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{
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uint32 sysgen_p;
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sysgen_p = pread_w(SYSGEN_PTR, BUS_PER);
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sim_debug(CIO_DBG, &cpu_dev,
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"[SYSGEN] Starting sysgen for card %d (%s). sysgen_p=%08x\n",
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slot, cio[slot].name, sysgen_p);
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/* seqbit is always reset to 0 on completion */
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cio[slot].seqbit = 0;
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cio[slot].rqp = pread_w(sysgen_p, BUS_PER);
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cio[slot].cqp = pread_w(sysgen_p + 4, BUS_PER);
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cio[slot].rqs = pread_b(sysgen_p + 8, BUS_PER);
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cio[slot].cqs = pread_b(sysgen_p + 9, BUS_PER);
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cio[slot].ivec = pread_b(sysgen_p + 10, BUS_PER);
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cio[slot].no_rque = pread_b(sysgen_p + 11, BUS_PER);
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sim_debug(CIO_DBG, &cpu_dev,
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"[SYSGEN] sysgen rqp = %08x\n",
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cio[slot].rqp);
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sim_debug(CIO_DBG, &cpu_dev,
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"[SYSGEN] sysgen cqp = %08x\n",
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cio[slot].cqp);
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sim_debug(CIO_DBG, &cpu_dev,
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"[SYSGEN] sysgen rqs = %02x\n",
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cio[slot].rqs);
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sim_debug(CIO_DBG, &cpu_dev,
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"[SYSGEN] sysgen cqs = %02x\n",
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cio[slot].cqs);
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sim_debug(CIO_DBG, &cpu_dev,
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"[SYSGEN] sysgen ivec = %02x\n",
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cio[slot].ivec);
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sim_debug(CIO_DBG, &cpu_dev,
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"[SYSGEN] sysgen no_rque = %02x\n",
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cio[slot].no_rque);
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/* If the card has a custom sysgen handler, run it */
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if (cio[slot].sysgen != NULL) {
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cio[slot].sysgen(slot);
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} else {
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sim_debug(CIO_DBG, &cpu_dev,
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"[cio_sysgen] Not running custom sysgen.\n");
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}
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}
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void cio_cexpress(uint8 slot, uint32 esize, cio_entry *cqe, uint8 *app_data)
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{
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uint32 i, cqp;
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cqp = cio[slot].cqp;
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sim_debug(CIO_DBG, &cpu_dev,
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"[cio_cexpress] [%s] cqp = %08x seqbit = %d\n",
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cio[slot].name, cqp, cio[slot].seqbit);
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cio[slot].seqbit ^= 1;
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cqe->subdevice |= (cio[slot].seqbit << 6);
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pwrite_h(cqp, cqe->byte_count, BUS_PER);
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pwrite_b(cqp + 2, cqe->subdevice, BUS_PER);
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pwrite_b(cqp + 3, cqe->opcode, BUS_PER);
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pwrite_w(cqp + 4, cqe->address, BUS_PER);
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/* Write application-specific data. */
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for (i = 0; i < (esize - QESIZE); i++) {
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pwrite_b(cqp + 8 + i, app_data[i], BUS_PER);
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}
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}
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void cio_cqueue(uint8 slot, uint8 cmd_stat, uint32 esize,
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cio_entry *cqe, uint8 *app_data)
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{
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uint32 i, cqp, top;
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uint16 lp;
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/* Apply the CMD/STAT bit */
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cqe->subdevice |= (cmd_stat << 7);
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/* Get the physical address of the completion queue
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* in main memory */
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cqp = cio[slot].cqp;
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/* Get the physical address of the first entry in
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* the completion queue */
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top = cqp + esize + LUSIZE;
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/* Get the load pointer. This is a 16-bit absolute offset
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* from the top of the queue to the start of the entry. */
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lp = pread_h(cqp + esize, BUS_PER);
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/* Load the entry at the supplied address */
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pwrite_h(top + lp, cqe->byte_count, BUS_PER);
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pwrite_b(top + lp + 2, cqe->subdevice, BUS_PER);
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pwrite_b(top + lp + 3, cqe->opcode, BUS_PER);
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pwrite_w(top + lp + 4, cqe->address, BUS_PER);
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/* Write application-specific data. */
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for (i = 0; i < (esize - QESIZE); i++) {
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pwrite_b(top + lp + 8 + i, app_data[i], BUS_PER);
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}
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/* Increment the load pointer to the next queue location.
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* If we go past the end of the queue, wrap around to the
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* start of the queue */
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if (cio[slot].cqs > 0) {
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lp = (lp + esize) % (esize * cio[slot].cqs);
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/* Store it back to the correct location */
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pwrite_h(cqp + esize, lp, BUS_PER);
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}
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}
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/*
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* Retrieve the Express Entry from the Request Queue
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*/
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void cio_rexpress(uint8 slot, uint32 esize, cio_entry *rqe, uint8 *app_data)
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{
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uint32 i;
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uint32 rqp;
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rqp = cio[slot].rqp;
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/* Unload the express entry from the request queue */
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rqe->byte_count = pread_h(rqp, BUS_PER);
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rqe->subdevice = pread_b(rqp + 2, BUS_PER);
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rqe->opcode = pread_b(rqp + 3, BUS_PER);
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rqe->address = pread_w(rqp + 4, BUS_PER);
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for (i = 0; i < (esize - QESIZE); i++) {
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app_data[i] = pread_b(rqp + 8 + i, BUS_PER);
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}
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}
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/*
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* Retrieve an entry from the Request Queue. This function
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* returns the load pointer that points to the NEXT available slot.
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* This may be used by callers to determine which queue(s) need to
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* be serviced.
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*
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* Returns SCPE_OK on success, or SCPE_NXM if no entry was found.
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*
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*/
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t_stat cio_rqueue(uint8 slot, uint32 qnum, uint32 esize,
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cio_entry *rqe, uint8 *app_data)
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{
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uint32 i, rqp, top;
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uint16 lp, ulp;
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/* Get the physical address of the request queue in main memory */
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rqp = cio[slot].rqp +
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esize +
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(qnum * (LUSIZE + (esize * cio[slot].rqs)));
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lp = pread_h(rqp, BUS_PER);
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ulp = pread_h(rqp + 2, BUS_PER);
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/* Check to see if the request queue is empty. If it is, there's
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* nothing to take. */
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if (lp == ulp) {
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return SCPE_NXM;
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}
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top = rqp + LUSIZE;
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/* Retrieve the entry at the supplied address */
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rqe->byte_count = pread_h(top + ulp, BUS_PER);
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rqe->subdevice = pread_b(top + ulp + 2, BUS_PER);
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rqe->opcode = pread_b(top + ulp + 3, BUS_PER);
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rqe->address = pread_w(top + ulp + 4, BUS_PER);
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/* Read application-specific data. */
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for (i = 0; i < (esize - QESIZE); i++) {
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app_data[i] = pread_b(top + ulp + 8 + i, BUS_PER);
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}
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/* Increment the unload pointer to the next queue location. If we
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* go past the end of the queue, wrap around to the start of the
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* queue */
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if (cio[slot].rqs > 0) {
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ulp = (ulp + esize) % (esize * cio[slot].rqs);
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pwrite_h(rqp + 2, ulp, BUS_PER);
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}
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return SCPE_OK;
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}
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/*
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* Return the Load Pointer for the given request queue
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*/
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uint16 cio_r_lp(uint8 slot, uint32 qnum, uint32 esize)
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{
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uint32 rqp;
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rqp = cio[slot].rqp +
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esize +
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(qnum * (LUSIZE + (esize * cio[slot].rqs)));
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return pread_h(rqp, BUS_PER);
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}
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/*
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* Return the Unload Pointer for the given request queue
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*/
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uint16 cio_r_ulp(uint8 slot, uint32 qnum, uint32 esize)
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{
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uint32 rqp;
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rqp = cio[slot].rqp +
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esize +
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(qnum * (LUSIZE + (esize * cio[slot].rqs)));
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return pread_h(rqp + 2, BUS_PER);
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}
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uint16 cio_c_lp(uint8 slot, uint32 esize)
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{
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uint32 cqp;
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cqp = cio[slot].cqp + esize;
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return pread_h(cqp, BUS_PER);
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}
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uint16 cio_c_ulp(uint8 slot, uint32 esize)
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{
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uint32 cqp;
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cqp = cio[slot].cqp + esize;
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return pread_h(cqp + 2, BUS_PER);
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}
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/*
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* Returns true if there is room in the completion queue
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* for a new entry.
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*/
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t_bool cio_cqueue_avail(uint8 slot, uint32 esize)
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{
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uint32 lp, ulp;
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lp = pread_h(cio[slot].cqp + esize, BUS_PER);
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ulp = pread_h(cio[slot].cqp + esize + 2, BUS_PER);
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return(((lp + esize) % (cio[slot].cqs * esize)) != ulp);
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}
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t_bool cio_rqueue_avail(uint8 slot, uint32 qnum, uint32 esize)
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{
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uint32 rqp, lp, ulp;
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/* Get the physical address of the request queue in main memory */
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rqp = cio[slot].rqp +
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esize +
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(qnum * (LUSIZE + (esize * cio[slot].rqs)));
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lp = pread_h(rqp, BUS_PER);
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ulp = pread_h(rqp + 2, BUS_PER);
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return(lp != ulp);
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}
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uint32 io_read(uint32 pa, size_t size)
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{
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iolink *p;
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uint8 slot, reg, data;
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#if defined (REV3)
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if (pa >= VCACHE_BOTTOM && pa < VCACHE_TOP) {
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sim_debug(EXECUTE_MSG, &cpu_dev,
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"[UBUB] (VCACHE) Read addr %08x\n", pa);
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CSRBIT(CSRTIMO, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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return 0;
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}
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if (pa >= BUB_BOTTOM && pa < BUB_TOP) {
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sim_debug(EXECUTE_MSG, &cpu_dev,
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"[BUB] Read addr %08x\n", pa);
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CSRBIT(CSRTIMO, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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return 0;
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}
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#else
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if (pa == MEMSIZE_REG) {
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/* The following values map to memory sizes:
|
|
0x00: 512KB ( 524,288 B)
|
|
0x01: 2MB (2,097,152 B)
|
|
0x02: 1MB (1,048,576 B)
|
|
0x03: 4MB (4,194,304 B)
|
|
*/
|
|
switch(MEM_SIZE) {
|
|
case 0x80000: /* 512KB */
|
|
return 0;
|
|
case 0x100000: /* 1MB */
|
|
return 2;
|
|
case 0x200000: /* 2MB */
|
|
return 1;
|
|
case 0x400000: /* 4MB */
|
|
return 3;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* CIO board area */
|
|
if (pa >= CIO_BOTTOM && pa < CIO_TOP) {
|
|
slot = SLOT(pa);
|
|
reg = pa - CADDR(slot);
|
|
|
|
if (!cio[slot].populated) {
|
|
/* Nothing lives here */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[READ] No card at slot=%d reg=%d\n",
|
|
slot, reg);
|
|
CSRBIT(CSRTIMO, TRUE);
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return 0;
|
|
}
|
|
|
|
/* A normal SYSGEN sequence is: RESET -> INT0 -> INT1.
|
|
* However, there's a bug in the 3B2/400 DGMON test suite that
|
|
* runs on every startup. This diagnostic code performs a
|
|
* SYSGEN by calling RESET -> INT1 -> INT0. So, we must handle
|
|
* both orders. */
|
|
|
|
switch (reg) {
|
|
case IOF_ID:
|
|
case IOF_VEC:
|
|
switch(cio[slot].sysgen_s) {
|
|
case CIO_INT_NONE: /* We've never seen an INT0 or INT1 */
|
|
case CIO_INT0: /* We've seen an INT0 but not an INT1. */
|
|
cio[slot].sysgen_s |= CIO_INT0;
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d INT0) ID\n",
|
|
cio[slot].name, slot);
|
|
/* Return the correct byte of our board ID */
|
|
if (reg == IOF_ID) {
|
|
data = (cio[slot].id >> 8) & 0xff;
|
|
} else {
|
|
data = (cio[slot].id & 0xff);
|
|
}
|
|
break;
|
|
case CIO_INT1: /* We've seen an INT1 but not an INT0. Time to sysgen */
|
|
cio[slot].sysgen_s |= CIO_INT0;
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d INT0) SYSGEN\n",
|
|
cio[slot].name, slot);
|
|
cio_sysgen(slot);
|
|
data = cio[slot].ivec;
|
|
break;
|
|
case CIO_SYSGEN: /* We've already sysgen'ed */
|
|
cio[slot].sysgen_s |= CIO_INT0; /* This must come BEFORE the exp_handler */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d INT0) EXPRESS JOB\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].exp_handler(slot);
|
|
data = cio[slot].ivec;
|
|
break;
|
|
default:
|
|
/* This should never happen */
|
|
stop_reason = STOP_ERR;
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d INT0) ERROR IN STATE MACHINE sysgen_s=%02x\n",
|
|
cio[slot].name, slot, cio[slot].sysgen_s);
|
|
data = 0;
|
|
break;
|
|
}
|
|
|
|
return data;
|
|
case IOF_CTRL:
|
|
switch(cio[slot].sysgen_s) {
|
|
case CIO_INT_NONE: /* We've never seen an INT0 or INT1 */
|
|
case CIO_INT1: /* We've seen an INT1 but not an INT0 */
|
|
/* There's nothing to do in this instance */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d INT1) IGNORED\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT1;
|
|
break;
|
|
case CIO_INT0: /* We've seen an INT0 but not an INT1. Time to sysgen */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d INT1) SYSGEN\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT1;
|
|
cio_sysgen(slot);
|
|
break;
|
|
case CIO_SYSGEN: /* We've already sysgen'ed */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d INT1) FULL\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT1; /* This must come BEFORE the full handler */
|
|
cio[slot].full_handler(slot);
|
|
break;
|
|
default:
|
|
/* This should never happen */
|
|
stop_reason = STOP_ERR;
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d INT1) ERROR IN STATE MACHINE sysgen_s=%02x\n",
|
|
cio[slot].name, slot, cio[slot].sysgen_s);
|
|
break;
|
|
}
|
|
|
|
return 0; /* Data returned is arbitrary */
|
|
case IOF_STAT:
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] [%s] (%d RESET)\n",
|
|
cio[slot].name, slot);
|
|
if (cio[slot].reset_handler) {
|
|
cio[slot].reset_handler(slot);
|
|
}
|
|
cio[slot].sysgen_s = 0;
|
|
return 0; /* Data returned is arbitrary */
|
|
default:
|
|
/* We should never reach here, but if we do, there's
|
|
* nothing listening. */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[READ] No card at slot=%d reg=%d\n",
|
|
slot, reg);
|
|
CSRBIT(CSRTIMO, TRUE);
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* Memory-mapped IO devices */
|
|
for (p = &iotable[0]; p->low != 0; p++) {
|
|
if ((pa >= p->low) && (pa < p->high) && p->read) {
|
|
return p->read(pa, size);
|
|
}
|
|
}
|
|
|
|
/* Not found. */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[io_read] ADDR=%08x: No device found.\n",
|
|
pa);
|
|
CSRBIT(CSRTIMO, TRUE);
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return 0;
|
|
}
|
|
|
|
void io_write(uint32 pa, uint32 val, size_t size)
|
|
{
|
|
iolink *p;
|
|
uint8 slot, reg;
|
|
|
|
#if defined(REV3)
|
|
if (pa >= VCACHE_BOTTOM && pa < VCACHE_TOP) {
|
|
sim_debug(EXECUTE_MSG, &cpu_dev,
|
|
"[UBUB] (VCACHE) Write addr %08x val 0x%x\n",
|
|
pa, val);
|
|
CSRBIT(CSRTIMO, TRUE);
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return;
|
|
}
|
|
|
|
if (pa >= BUB_BOTTOM && pa < BUB_TOP) {
|
|
sim_debug(EXECUTE_MSG, &cpu_dev,
|
|
"[BUB] Write addr %08x val 0x%x\n",
|
|
pa, val);
|
|
CSRBIT(CSRTIMO, TRUE);
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
/* Feature Card Area */
|
|
if (pa >= CIO_BOTTOM && pa < CIO_TOP) {
|
|
slot = SLOT(pa);
|
|
reg = pa - CADDR(slot);
|
|
|
|
if (!cio[slot].populated) {
|
|
/* Nothing lives here */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] No card at slot=%d reg=%d\n",
|
|
slot, reg);
|
|
CSRBIT(CSRTIMO, TRUE);
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return;
|
|
}
|
|
|
|
/* A normal SYSGEN sequence is: RESET -> INT0 -> INT1.
|
|
* However, there's a bug in the 3B2/400 DGMON test suite that
|
|
* runs on every startup. This diagnostic code performs a
|
|
* SYSGEN by calling RESET -> INT1 -> INT0. So, we must handle
|
|
* both orders. */
|
|
|
|
switch (reg) {
|
|
case IOF_ID:
|
|
case IOF_VEC:
|
|
switch(cio[slot].sysgen_s) {
|
|
case CIO_INT_NONE: /* We've never seen an INT0 or INT1 */
|
|
case CIO_INT0: /* We've seen an INT0 but not an INT1. */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d INT0) ID\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT0;
|
|
break;
|
|
case CIO_INT1: /* We've seen an INT1 but not an INT0. Time to sysgen */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d INT0) SYSGEN\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT0;
|
|
cio_sysgen(slot);
|
|
break;
|
|
case CIO_SYSGEN: /* We've already sysgen'ed */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d INT0) EXPRESS JOB\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT0;
|
|
cio[slot].exp_handler(slot);
|
|
break;
|
|
default:
|
|
/* This should never happen */
|
|
stop_reason = STOP_ERR;
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d INT0) ERROR IN STATE MACHINE sysgen_s=%02x\n",
|
|
cio[slot].name, slot, cio[slot].sysgen_s);
|
|
break;
|
|
}
|
|
|
|
return;
|
|
case IOF_CTRL:
|
|
switch(cio[slot].sysgen_s) {
|
|
case CIO_INT_NONE: /* We've never seen an INT0 or INT1 */
|
|
case CIO_INT1: /* We've seen an INT1 but not an INT0 */
|
|
/* There's nothing to do in this instance */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d INT1) IGNORED\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT1;
|
|
break;
|
|
case CIO_INT0: /* We've seen an INT0 but not an INT1. Time to sysgen */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d INT1) SYSGEN\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT1;
|
|
cio_sysgen(slot);
|
|
break;
|
|
case CIO_SYSGEN: /* We've already sysgen'ed */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d INT1) FULL\n",
|
|
cio[slot].name, slot);
|
|
cio[slot].sysgen_s |= CIO_INT1;
|
|
cio[slot].full_handler(slot);
|
|
break;
|
|
default:
|
|
/* This should never happen */
|
|
stop_reason = STOP_ERR;
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d INT1) ERROR IN STATE MACHINE sysgen_s=%02x\n",
|
|
cio[slot].name, slot, cio[slot].sysgen_s);
|
|
break;
|
|
}
|
|
|
|
return;
|
|
case IOF_STAT:
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] [%s] (%d RESET)\n",
|
|
cio[slot].name, slot);
|
|
if (cio[slot].reset_handler) {
|
|
cio[slot].reset_handler(slot);
|
|
}
|
|
cio[slot].sysgen_s = 0;
|
|
return;
|
|
default:
|
|
/* We should never reach here, but if we do, there's
|
|
* nothing listening. */
|
|
sim_debug(CIO_DBG, &cpu_dev,
|
|
"[WRITE] No card at slot=%d reg=%d\n",
|
|
slot, reg);
|
|
CSRBIT(CSRTIMO, TRUE);
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Memory-mapped IO devices */
|
|
for (p = &iotable[0]; p->low != 0; p++) {
|
|
if ((pa >= p->low) && (pa < p->high) && p->write) {
|
|
p->write(pa, val, size);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Not found. */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[io_write] ADDR=%08x: No device found.\n",
|
|
pa);
|
|
CSRBIT(CSRTIMO, TRUE);
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
}
|