169 lines
7.8 KiB
C
169 lines
7.8 KiB
C
/* pdp11_uqssp.h: Unibus/Qbus storage systems port definitions file
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Copyright (c) 2001-2008, Robert M Supnik
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Derived from work by Stephen F. Shirron
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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30-Aug-02 RMS Added TMSCP support
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*/
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#ifndef PDP11_UQSSP_H_
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#define PDP11_UQSSP_H_ 0
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/* IP register - initialization and polling
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read - controller polls command queue
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write - controller re-initializes
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*/
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/* SA register - status, address, and purge
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read - data and error information
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write - host startup information, purge complete
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*/
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#define SA_ER 0x8000 /* error */
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#define SA_S4 0x4000 /* init step 4 */
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#define SA_S3 0x2000 /* init step 3 */
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#define SA_S2 0x1000 /* init step 2 */
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#define SA_S1 0x0800 /* init step 1 */
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/* Init step 1, controller to host */
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#define SA_S1C_NV 0x0400 /* fixed vec NI */
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#define SA_S1C_Q22 0x0200 /* Q22 device */
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#define SA_S1C_DI 0x0100 /* ext diags */
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#define SA_S1C_OD 0x0080 /* odd addrs NI */
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#define SA_S1C_MP 0x0040 /* mapping */
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#define SA_S1C_SM 0x0020 /* spec fncs NI */
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#define SA_S1C_CN 0x0010 /* node name NI */
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/* Init step 1, host to controller */
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#define SA_S1H_VL 0x8000 /* valid */
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#define SA_S1H_WR 0x4000 /* wrap mode */
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#define SA_S1H_V_CQ 11 /* cmd q len */
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#define SA_S1H_M_CQ 0x7
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#define SA_S1H_V_RQ 8 /* resp q len */
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#define SA_S1H_M_RQ 0x7
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#define SA_S1H_IE 0x0080 /* int enb */
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#define SA_S1H_VEC 0x007F /* vector */
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#define SA_S1H_CQ(x) (1 << (((x) >> SA_S1H_V_CQ) & SA_S1H_M_CQ))
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#define SA_S1H_RQ(x) (1 << (((x) >> SA_S1H_V_RQ) & SA_S1H_M_RQ))
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/* Init step 2, controller to host */
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#define SA_S2C_PT 0x0000 /* port type */
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#define SA_S2C_V_EC 8 /* info to echo */
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#define SA_S2C_M_EC 0xFF
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#define SA_S2C_EC(x) (((x) >> SA_S2C_V_EC) & SA_S2C_M_EC)
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/* Init step 2, host to controller */
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#define SA_S2H_CLO 0xFFFE /* comm addr lo */
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#define SA_S2H_PI 0x0001 /* adp prg int */
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/* Init step 3, controller to host */
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#define SA_S3C_V_EC 0 /* info to echo */
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#define SA_S3C_M_EC 0xFF
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#define SA_S3C_EC(x) (((x) >> SA_S3C_V_EC) & SA_S3C_M_EC)
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/* Init step 3, host to controller */
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#define SA_S3H_PP 0x8000 /* purge, poll test */
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#define SA_S3H_CHI 0x7FFF /* comm addr hi */
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/* Init step 4, controller to host */
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#define SA_S4C_V_MOD 4 /* adapter # */
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#define SA_S4C_V_VER 0 /* version # */
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/* Init step 4, host to controller */
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#define SA_S4H_CS 0x0400 /* host scrpad NI */
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#define SA_S4H_NN 0x0200 /* snd node name NI */
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#define SA_S4H_SF 0x0100 /* spec fnc NI */
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#define SA_S4H_LF 0x0002 /* send last fail */
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#define SA_S4H_GO 0x0001 /* go */
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/* Fatal error codes (generic through 32) */
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#define PE_PRE 1 /* packet read err */
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#define PE_PWE 2 /* packet write err */
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#define PE_QRE 6 /* queue read err */
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#define PE_QWE 7 /* queue write err */
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#define PE_HAT 9 /* host access tmo */
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#define PE_ICI 14 /* inv conn ident */
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#define PE_PIE 20 /* prot incompat */
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#define PE_PPF 21 /* prg/poll err */
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#define PE_MRE 22 /* map reg rd err */
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#define PE_T11 475 /* T11 err NI */
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#define PE_SND 476 /* SND err NI */
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#define PE_RCV 477 /* RCV err NI */
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#define PE_NSR 478 /* no such rsrc */
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/* Comm region offsets */
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#define SA_COMM_QQ -8 /* unused */
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#define SA_COMM_PI -6 /* purge int */
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#define SA_COMM_CI -4 /* cmd int */
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#define SA_COMM_RI -2 /* resp int */
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#define SA_COMM_MAX ((4 << SA_S1H_M_CQ) + (4 << SA_S1H_M_RQ) - SA_COMM_QQ)
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/* Command/response rings */
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struct uq_ring {
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int32 ioff; /* intr offset */
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uint32 ba; /* base addr */
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uint32 lnt; /* size in bytes */
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uint32 idx; /* current index */
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};
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/* Ring descriptor entry */
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#define UQ_DESC_OWN 0x80000000 /* ownership */
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#define UQ_DESC_F 0x40000000 /* flag */
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#define UQ_ADDR 0x003FFFFE /* addr, word aligned */
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/* Packet header */
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#define UQ_HDR_OFF -4 /* offset */
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#define UQ_HLNT 0 /* length */
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#define UQ_HCTC 1 /* credits, type, CID */
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#define UQ_HCTC_V_CR 0 /* credits */
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#define UQ_HCTC_M_CR 0xF
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#define UQ_HCTC_V_TYP 4 /* type */
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#define UQ_HCTC_M_TYP 0xF
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#define UQ_TYP_SEQ 0 /* sequential */
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#define UQ_TYP_DAT 1 /* datagram */
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#define UQ_HCTC_V_CID 8 /* conn ID */
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#define UQ_HCTC_M_CID 0xFF
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#define UQ_CID_MSCP 0 /* MSCP */
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#define UQ_CID_TMSCP 1 /* TMSCP */
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#define UQ_CID_DUP 2 /* DUP */
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#define UQ_CID_DIAG 0xFF /* diagnostic */
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#endif
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