d76bd81491
This commit fixes several issues with code hygine and eliminates warnings in the Windows build.
622 lines
21 KiB
C
622 lines
21 KiB
C
/* 3b2_cpu.h: AT&T 3B2 Model 400 IO and CIO feature cards
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Copyright (c) 2017, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#include "3b2_io.h"
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CIO_STATE cio[CIO_SLOTS] = { 0 };
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struct iolink iotable[] = {
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{ MMUBASE, MMUBASE+MMUSIZE, &mmu_read, &mmu_write },
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{ IFBASE, IFBASE+IFSIZE, &if_read, &if_write },
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{ IDBASE, IDBASE+IDSIZE, &id_read, &id_write },
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{ TIMERBASE, TIMERBASE+TIMERSIZE, &timer_read, &timer_write },
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{ NVRAMBASE, NVRAMBASE+NVRAMSIZE, &nvram_read, &nvram_write },
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{ CSRBASE, CSRBASE+CSRSIZE, &csr_read, &csr_write },
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{ IUBASE, IUBASE+IUSIZE, &iu_read, &iu_write },
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{ DMAIDBASE, DMAIDBASE+DMAIDSIZE, &dmac_read, &dmac_write },
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{ DMAIUABASE, DMAIUABASE+DMAIUASIZE, &dmac_read, &dmac_write },
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{ DMAIUBBASE, DMAIUBBASE+DMAIUBSIZE, &dmac_read, &dmac_write },
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{ DMACBASE, DMACBASE+DMACSIZE, &dmac_read, &dmac_write },
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{ DMAIFBASE, DMAIFBASE+DMAIFSIZE, &dmac_read, &dmac_write },
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{ TODBASE, TODBASE+TODSIZE, &tod_read, &tod_write },
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{ 0, 0, NULL, NULL}
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};
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void cio_clear(uint8 cid)
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{
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cio[cid].id = 0;
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cio[cid].exp_handler = NULL;
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cio[cid].full_handler = NULL;
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cio[cid].sysgen = NULL;
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cio[cid].rqp = 0;
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cio[cid].cqp = 0;
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cio[cid].rqs = 0;
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cio[cid].cqs = 0;
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cio[cid].ivec = 0;
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cio[cid].no_rque = 0;
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cio[cid].ipl = 0;
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cio[cid].intr = FALSE;
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cio[cid].sysgen_s = 0;
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cio[cid].seqbit = 0;
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cio[cid].op = 0;
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}
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void cio_sysgen(uint8 cid)
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{
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uint32 sysgen_p;
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sysgen_p = pread_w(SYSGEN_PTR);
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sim_debug(IO_DBG, &cpu_dev,
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"[%08x] [SYSGEN] Starting sysgen for card %d. sysgen_p=%08x\n",
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R[NUM_PC], cid, sysgen_p);
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/* seqbit is always reset to 0 on completion */
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cio[cid].seqbit = 0;
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cio[cid].rqp = pread_w(sysgen_p);
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cio[cid].cqp = pread_w(sysgen_p + 4);
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cio[cid].rqs = pread_b(sysgen_p + 8);
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cio[cid].cqs = pread_b(sysgen_p + 9);
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cio[cid].ivec = pread_b(sysgen_p + 10);
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cio[cid].no_rque = pread_b(sysgen_p + 11);
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sim_debug(IO_DBG, &cpu_dev,
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"[SYSGEN] sysgen rqp = %08x\n",
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cio[cid].rqp);
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sim_debug(IO_DBG, &cpu_dev,
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"[SYSGEN] sysgen cqp = %08x\n",
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cio[cid].cqp);
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sim_debug(IO_DBG, &cpu_dev,
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"[SYSGEN] sysgen rqs = %02x\n",
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cio[cid].rqs);
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sim_debug(IO_DBG, &cpu_dev,
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"[SYSGEN] sysgen cqs = %02x\n",
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cio[cid].cqs);
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sim_debug(IO_DBG, &cpu_dev,
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"[SYSGEN] sysgen ivec = %02x\n",
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cio[cid].ivec);
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sim_debug(IO_DBG, &cpu_dev,
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"[SYSGEN] sysgen no_rque = %02x\n",
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cio[cid].no_rque);
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/* If the card has a custom sysgen handler, run it */
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if (cio[cid].sysgen != NULL) {
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cio[cid].sysgen(cid);
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} else {
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sim_debug(IO_DBG, &cpu_dev,
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"[%08x] [cio_sysgen] Not running custom sysgen.\n",
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R[NUM_PC]);
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}
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}
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void cio_cexpress(uint8 cid, uint16 esize, cio_entry *cqe, uint8 *app_data)
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{
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int32 i;
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uint32 cqp;
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cqp = cio[cid].cqp;
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sim_debug(IO_DBG, &cpu_dev,
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"[%08x] [cio_cexpress] cqp = %08x seqbit = %d\n",
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R[NUM_PC], cqp, cio[cid].seqbit);
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cio[cid].seqbit ^= 1;
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cqe->subdevice |= (cio[cid].seqbit << 6);
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pwrite_h(cqp, cqe->byte_count);
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pwrite_b(cqp + 2, cqe->subdevice);
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pwrite_b(cqp + 3, cqe->opcode);
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pwrite_w(cqp + 4, cqe->address);
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/* Write application-specific data. */
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for (i = 0; i < (esize - QESIZE); i++) {
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pwrite_b(cqp + 8 + i, app_data[i]);
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}
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}
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void cio_cqueue(uint8 cid, uint8 cmd_stat, uint16 esize,
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cio_entry *cqe, uint8 *app_data)
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{
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int32 i;
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uint32 cqp, top;
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uint16 lp, ulp;
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/* Apply the CMD/STAT bit */
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cqe->subdevice |= (cmd_stat << 7);
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/* Get the physical address of the completion queue
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* in main memory */
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cqp = cio[cid].cqp;
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/* Get the physical address of the first entry in
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* the completion queue */
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top = cqp + esize + LUSIZE;
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/* Get the load pointer. This is a 16-bit absolute offset
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* from the top of the queue to the start of the entry. */
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lp = pread_h(cqp + esize);
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ulp = pread_h(cqp + esize + 2);
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/* Load the entry at the supplied address */
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pwrite_h(top + lp, cqe->byte_count);
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pwrite_b(top + lp + 2, cqe->subdevice);
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pwrite_b(top + lp + 3, cqe->opcode);
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pwrite_w(top + lp + 4, cqe->address);
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/* Write application-specific data. */
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for (i = 0; i < (esize - QESIZE); i++) {
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pwrite_b(top + lp + 8 + i, app_data[i]);
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}
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/* Increment the load pointer to the next queue location.
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* If we go past the end of the queue, wrap around to the
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* start of the queue */
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if (cio[cid].cqs > 0) {
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lp = (lp + esize) % (esize * cio[cid].cqs);
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/* Store it back to the correct location */
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pwrite_h(cqp + esize, lp);
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} else {
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sim_debug(IO_DBG, &cpu_dev,
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"[%08x] [cio_cqueue] ERROR! Completion Queue Size is 0!",
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R[NUM_PC]);
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}
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}
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/*
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* Retrieve the Express Entry from the Request Queue
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*/
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void cio_rexpress(uint8 cid, uint16 esize, cio_entry *rqe, uint8 *app_data)
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{
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int32 i;
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uint32 rqp;
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rqp = cio[cid].rqp;
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/* Unload the express entry from the request queue */
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rqe->byte_count = pread_h(rqp);
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rqe->subdevice = pread_b(rqp + 2);
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rqe->opcode = pread_b(rqp + 3);
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rqe->address = pread_w(rqp + 4);
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for (i = 0; i < (esize - QESIZE); i++) {
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app_data[i] = pread_b(rqp + 8 + i);
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}
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}
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/*
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* Retrieve an entry from the Request Queue. This function
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* returns the load pointer that points to the NEXT available slot.
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* This may be used by callers to determine which queue(s) need to
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* be serviced.
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*
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* Returns SCPE_OK on success, or SCPE_NXM if no entry was found.
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*/
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t_stat cio_rqueue(uint8 cid, uint8 qnum, uint16 esize,
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cio_entry *rqe, uint8 *app_data)
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{
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int32 i;
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uint32 rqp, top;
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uint16 lp, ulp;
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/* Get the physical address of the request queue in main memory */
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rqp = cio[cid].rqp +
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esize +
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(qnum * (LUSIZE + (esize * cio[cid].rqs)));
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lp = pread_h(rqp);
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ulp = pread_h(rqp + 2);
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if (lp == ulp) {
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return SCPE_NXM;
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}
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top = rqp + LUSIZE;
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/* Retrieve the entry at the supplied address */
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rqe->byte_count = pread_h(top + ulp);
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rqe->subdevice = pread_b(top + ulp + 2);
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rqe->opcode = pread_b(top + ulp + 3);
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rqe->address = pread_w(top + ulp + 4);
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/* Read application-specific data. */
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for (i = 0; i < (esize - QESIZE); i++) {
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app_data[i] = pread_b(top + ulp + 8 + i);
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}
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/* Increment the unload pointer to the next queue location. If we
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* go past the end of the queue, wrap around to the start of the
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* queue */
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if (cio[cid].rqs > 0) {
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ulp = (ulp + esize) % (esize * cio[cid].rqs);
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pwrite_h(rqp + 2, ulp);
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}
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return SCPE_OK;
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}
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/*
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* Return the Load Pointer for the given request queue
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*/
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uint16 cio_r_lp(uint8 cid, uint8 qnum, uint16 esize)
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{
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uint32 rqp;
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rqp = cio[cid].rqp +
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esize +
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(qnum * (LUSIZE + (esize * cio[cid].rqs)));
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return pread_h(rqp);
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}
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/*
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* Return the Unload Pointer for the given request queue
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*/
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uint16 cio_r_ulp(uint8 cid, uint8 qnum, uint16 esize)
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{
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uint32 rqp;
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rqp = cio[cid].rqp +
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esize +
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(qnum * (LUSIZE + (esize * cio[cid].rqs)));
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return pread_h(rqp + 2);
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}
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uint16 cio_c_lp(uint8 cid, uint16 esize)
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{
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uint32 cqp;
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cqp = cio[cid].cqp + esize;
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return pread_h(cqp);
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}
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uint16 cio_c_ulp(uint8 cid, uint16 esize)
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{
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uint32 cqp;
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cqp = cio[cid].cqp + esize;
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return pread_h(cqp + 2);
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}
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/*
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* Returns true if there is room in the completion queue
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* for a new entry.
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*/
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t_bool cio_cqueue_avail(uint8 cid, uint16 esize)
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{
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uint32 lp, ulp;
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lp = pread_h(cio[cid].cqp + esize);
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ulp = pread_h(cio[cid].cqp + esize + 2);
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return(((lp + esize) % (cio[cid].cqs * esize)) != ulp);
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}
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uint32 io_read(uint32 pa, size_t size)
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{
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struct iolink *p;
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uint8 cid, reg, data;
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/* Special devices */
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if (pa == MEMSIZE_REG) {
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/* The following values map to memory sizes:
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0x00: 512KB ( 524,288 B)
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0x01: 2MB (2,097,152 B)
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0x02: 1MB (1,048,576 B)
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0x03: 4MB (4,194,304 B)
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*/
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switch(MEM_SIZE) {
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case 0x80000: /* 512KB */
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return 0;
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case 0x100000: /* 1MB */
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return 2;
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case 0x200000: /* 2MB */
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return 1;
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case 0x400000: /* 4MB */
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return 3;
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default:
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return 0;
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}
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}
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/* CIO board area */
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if (pa >= CIO_BOTTOM && pa < CIO_TOP) {
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cid = CID(pa);
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reg = pa - CADDR(cid);
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if (cio[cid].id == 0) {
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/* Nothing lives here */
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] No card at cid=%d reg=%d\n",
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R[NUM_PC], cid, reg);
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csr_data |= CSRTIMO;
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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return 0;
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}
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/* A normal SYSGEN sequence is: RESET -> INT0 -> INT1.
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* However, there's a bug in the 3B2/400 DGMON test suite that
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* runs on every startup. This diagnostic code performs a
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* SYSGEN by calling RESET -> INT1 -> INT0. So, we must handle
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* both orders. */
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switch (reg) {
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case IOF_ID:
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case IOF_VEC:
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switch(cio[cid].sysgen_s) {
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case CIO_INT_NONE: /* We've never seen an INT0 or INT1 */
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case CIO_INT0: /* We've seen an INT0 but not an INT1. */
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cio[cid].sysgen_s |= CIO_INT0;
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d INT0) ID\n",
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R[NUM_PC], cid);
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/* Return the correct byte of our board ID */
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if (reg == IOF_ID) {
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data = (cio[cid].id >> 8) & 0xff;
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} else {
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data = (cio[cid].id & 0xff);
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}
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break;
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case CIO_INT1: /* We've seen an INT1 but not an INT0. Time to sysgen */
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cio[cid].sysgen_s |= CIO_INT0;
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d INT0) SYSGEN\n",
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R[NUM_PC], cid);
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cio_sysgen(cid);
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data = cio[cid].ivec;
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break;
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case CIO_SYSGEN: /* We've already sysgen'ed */
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cio[cid].sysgen_s |= CIO_INT0; /* This must come BEFORE the exp_handler */
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d INT0) EXPRESS JOB\n",
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R[NUM_PC], cid);
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cio[cid].exp_handler(cid);
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data = cio[cid].ivec;
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break;
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default:
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/* This should never happen */
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stop_reason = STOP_ERR;
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d INT0) ERROR IN STATE MACHINE sysgen_s=%02x\n",
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R[NUM_PC], cid, cio[cid].sysgen_s);
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data = 0;
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break;
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}
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return data;
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case IOF_CTRL:
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switch(cio[cid].sysgen_s) {
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case CIO_INT_NONE: /* We've never seen an INT0 or INT1 */
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case CIO_INT1: /* We've seen an INT1 but not an INT0 */
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/* There's nothing to do in this instance */
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d INT1) IGNORED\n",
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R[NUM_PC], cid);
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cio[cid].sysgen_s |= CIO_INT1;
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break;
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case CIO_INT0: /* We've seen an INT0 but not an INT1. Time to sysgen */
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d INT1) SYSGEN\n",
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R[NUM_PC], cid);
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cio[cid].sysgen_s |= CIO_INT1;
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cio_sysgen(cid);
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break;
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case CIO_SYSGEN: /* We've already sysgen'ed */
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d INT1) FULL\n",
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R[NUM_PC], cid);
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cio[cid].sysgen_s |= CIO_INT1; /* This must come BEFORE the full handler */
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cio[cid].full_handler(cid);
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break;
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default:
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/* This should never happen */
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stop_reason = STOP_ERR;
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d INT1) ERROR IN STATE MACHINE sysgen_s=%02x\n",
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R[NUM_PC], cid, cio[cid].sysgen_s);
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break;
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}
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return 0; /* Data returned is arbitrary */
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case IOF_STAT:
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] (%d RESET)\n",
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R[NUM_PC], cid);
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cio[cid].sysgen_s = 0;
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return 0; /* Data returned is arbitrary */
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default:
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/* We should never reach here, but if we do, there's
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* nothing listening. */
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sim_debug(IO_DBG, &cpu_dev,
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"[READ] [%08x] No card at cid=%d reg=%d\n",
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R[NUM_PC], cid, reg);
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csr_data |= CSRTIMO;
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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|
return 0;
|
|
}
|
|
}
|
|
|
|
/* Memory-mapped IO devices */
|
|
for (p = &iotable[0]; p->low != 0; p++) {
|
|
if ((pa >= p->low) && (pa < p->high) && p->read) {
|
|
return p->read(pa, size);
|
|
}
|
|
}
|
|
|
|
/* Not found. */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[%08x] [io_read] ADDR=%08x: No device found.\n",
|
|
R[NUM_PC], pa);
|
|
csr_data |= CSRTIMO;
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return 0;
|
|
}
|
|
|
|
void io_write(uint32 pa, uint32 val, size_t size)
|
|
{
|
|
struct iolink *p;
|
|
uint8 cid, reg;
|
|
|
|
/* Feature Card Area */
|
|
if (pa >= CIO_BOTTOM && pa < CIO_TOP) {
|
|
cid = CID(pa);
|
|
reg = pa - CADDR(cid);
|
|
|
|
if (cio[cid].id == 0) {
|
|
/* Nothing lives here */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] No card at cid=%d reg=%d\n",
|
|
R[NUM_PC], cid, reg);
|
|
csr_data |= CSRTIMO;
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return;
|
|
}
|
|
|
|
/* A normal SYSGEN sequence is: RESET -> INT0 -> INT1.
|
|
* However, there's a bug in the 3B2/400 DGMON test suite that
|
|
* runs on every startup. This diagnostic code performs a
|
|
* SYSGEN by calling RESET -> INT1 -> INT0. So, we must handle
|
|
* both orders. */
|
|
|
|
switch (reg) {
|
|
case IOF_ID:
|
|
case IOF_VEC:
|
|
switch(cio[cid].sysgen_s) {
|
|
case CIO_INT_NONE: /* We've never seen an INT0 or INT1 */
|
|
case CIO_INT0: /* We've seen an INT0 but not an INT1. */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d INT0) ID\n",
|
|
R[NUM_PC], cid);
|
|
cio[cid].sysgen_s |= CIO_INT0;
|
|
break;
|
|
case CIO_INT1: /* We've seen an INT1 but not an INT0. Time to sysgen */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d INT0) SYSGEN\n",
|
|
R[NUM_PC], cid);
|
|
cio[cid].sysgen_s |= CIO_INT0;
|
|
cio_sysgen(cid);
|
|
break;
|
|
case CIO_SYSGEN: /* We've already sysgen'ed */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d INT0) EXPRESS JOB\n",
|
|
R[NUM_PC], cid);
|
|
cio[cid].sysgen_s |= CIO_INT0;
|
|
cio[cid].exp_handler(cid);
|
|
break;
|
|
default:
|
|
/* This should never happen */
|
|
stop_reason = STOP_ERR;
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d INT0) ERROR IN STATE MACHINE sysgen_s=%02x\n",
|
|
R[NUM_PC], cid, cio[cid].sysgen_s);
|
|
break;
|
|
}
|
|
|
|
return;
|
|
case IOF_CTRL:
|
|
switch(cio[cid].sysgen_s) {
|
|
case CIO_INT_NONE: /* We've never seen an INT0 or INT1 */
|
|
case CIO_INT1: /* We've seen an INT1 but not an INT0 */
|
|
/* There's nothing to do in this instance */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d INT1) IGNORED\n",
|
|
R[NUM_PC], cid);
|
|
cio[cid].sysgen_s |= CIO_INT1;
|
|
break;
|
|
case CIO_INT0: /* We've seen an INT0 but not an INT1. Time to sysgen */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d INT1) SYSGEN\n",
|
|
R[NUM_PC], cid);
|
|
cio[cid].sysgen_s |= CIO_INT1;
|
|
cio_sysgen(cid);
|
|
break;
|
|
case CIO_SYSGEN: /* We've already sysgen'ed */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d INT1) FULL\n",
|
|
R[NUM_PC], cid);
|
|
cio[cid].sysgen_s |= CIO_INT1;
|
|
cio[cid].full_handler(cid);
|
|
break;
|
|
default:
|
|
/* This should never happen */
|
|
stop_reason = STOP_ERR;
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d INT1) ERROR IN STATE MACHINE sysgen_s=%02x\n",
|
|
R[NUM_PC], cid, cio[cid].sysgen_s);
|
|
break;
|
|
}
|
|
|
|
return;
|
|
case IOF_STAT:
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] (%d RESET)\n",
|
|
R[NUM_PC], cid);
|
|
cio[cid].sysgen_s = 0;
|
|
return;
|
|
default:
|
|
/* We should never reach here, but if we do, there's
|
|
* nothing listening. */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[WRITE] [%08x] No card at cid=%d reg=%d\n",
|
|
R[NUM_PC], cid, reg);
|
|
csr_data |= CSRTIMO;
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Memory-mapped IO devices */
|
|
for (p = &iotable[0]; p->low != 0; p++) {
|
|
if ((pa >= p->low) && (pa < p->high) && p->write) {
|
|
p->write(pa, val, size);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Not found. */
|
|
sim_debug(IO_DBG, &cpu_dev,
|
|
"[%08x] [io_write] ADDR=%08x: No device found.\n",
|
|
R[NUM_PC], pa);
|
|
csr_data |= CSRTIMO;
|
|
cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
|
|
}
|
|
|
|
|
|
/* For debugging only */
|
|
void dump_entry(uint32 dbits, DEVICE *dev, CONST char *type,
|
|
uint16 esize, cio_entry *entry, uint8 *app_data)
|
|
{
|
|
sim_debug(dbits, dev,
|
|
"*** %s ENTRY: byte_count=%04x, subdevice=%02x, opcode=%d, address=%08x\n",
|
|
type, entry->byte_count, entry->subdevice,
|
|
entry->opcode, entry->address);
|
|
}
|