1430 lines
34 KiB
C
1430 lines
34 KiB
C
/* disasm.c where all the _work_ gets done in the Netwide Disassembler
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*
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* The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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* Julian Hall. All rights reserved. The software is
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* redistributable under the licence given in the file "Licence"
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* distributed in the NASM archive.
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*
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* initial version 27/iii/95 by Simon Tatham
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*/
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#include <stdio.h>
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#include <string.h>
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#include "nasm.h"
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#include "insns.h"
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/* names.c included source file defining instruction and register
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* names for the Netwide [Dis]Assembler
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*
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* The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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* Julian Hall. All rights reserved. The software is
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* redistributable under the licence given in the file "Licence"
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* distributed in the NASM archive.
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*/
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static const char *conditions[] = { /* condition code names */
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"a", "ae", "b", "be", "c", "e", "g", "ge", "l", "le", "na", "nae",
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"nb", "nbe", "nc", "ne", "ng", "nge", "nl", "nle", "no", "np",
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"ns", "nz", "o", "p", "pe", "po", "s", "z"
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};
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/* Register names automatically generated from regs.dat */
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/* automatically generated from ./regs.dat - do not edit */
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static const char *reg_names[] = {
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"ah",
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"al",
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"ax",
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"bh",
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"bl",
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"bp",
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"bx",
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"ch",
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"cl",
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"cr0",
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"cr1",
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"cr2",
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"cr3",
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"cr4",
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"cr5",
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"cr6",
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"cr7",
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"cs",
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"cx",
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"dh",
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"di",
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"dl",
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"dr0",
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"dr1",
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"dr2",
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"dr3",
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"dr4",
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"dr5",
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"dr6",
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"dr7",
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"ds",
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"dx",
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"eax",
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"ebp",
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"ebx",
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"ecx",
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"edi",
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"edx",
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"es",
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"esi",
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"esp",
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"fs",
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"gs",
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"mm0",
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"mm1",
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"mm2",
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"mm3",
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"mm4",
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"mm5",
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"mm6",
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"mm7",
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"segr6",
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"segr7",
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"si",
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"sp",
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"ss",
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"st0",
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"st1",
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"st2",
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"st3",
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"st4",
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"st5",
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"st6",
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"st7",
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"tr0",
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"tr1",
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"tr2",
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"tr3",
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"tr4",
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"tr5",
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"tr6",
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"tr7",
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"xmm0",
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"xmm1",
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"xmm2",
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"xmm3",
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"xmm4",
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"xmm5",
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"xmm6",
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"xmm7"
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};
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/* Instruction names automatically generated from insns.dat */
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/* This file is auto-generated from insns.dat by insns.pl - don't edit it */
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/* This file in included by names.c */
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static const char *insn_names[] = {
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"aaa",
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"aad",
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"aam",
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"aas",
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"adc",
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"add",
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"addpd",
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"addps",
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"addsd",
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"addss",
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"addsubpd",
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"addsubps",
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"and",
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"andnpd",
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"andnps",
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"andpd",
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"andps",
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"arpl",
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"bound",
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"bsf",
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"bsr",
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"bswap",
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"bt",
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"btc",
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"btr",
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"bts",
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"call",
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"cbw",
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"cdq",
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"clc",
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"cld",
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"clflush",
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"cli",
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"clts",
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"cmc",
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"cmp",
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"cmpeqpd",
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"cmpeqps",
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"cmpeqsd",
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"cmpeqss",
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"cmplepd",
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"cmpleps",
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"cmplesd",
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"cmpless",
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"cmpltpd",
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"cmpltps",
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"cmpltsd",
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"cmpltss",
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"cmpneqpd",
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"cmpneqps",
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"cmpneqsd",
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"cmpneqss",
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"cmpnlepd",
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"cmpnleps",
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"cmpnlesd",
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"cmpnless",
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"cmpnltpd",
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"cmpnltps",
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"cmpnltsd",
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"cmpnltss",
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"cmpordpd",
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"cmpordps",
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"cmpordsd",
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"cmpordss",
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"cmppd",
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"cmpps",
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"cmpsb",
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"cmpsd",
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"cmpss",
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"cmpsw",
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"cmpunordpd",
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"cmpunordps",
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"cmpunordsd",
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"cmpunordss",
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"cmpxchg",
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"cmpxchg486",
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"cmpxchg8b",
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"comisd",
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"comiss",
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"cpuid",
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"cvtdq2pd",
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"cvtdq2ps",
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"cvtpd2dq",
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"cvtpd2pi",
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"cvtpd2ps",
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"cvtpi2pd",
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"cvtpi2ps",
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"cvtps2dq",
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"cvtps2pd",
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"cvtps2pi",
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"cvtsd2si",
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"cvtsd2ss",
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"cvtsi2sd",
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"cvtsi2ss",
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"cvtss2sd",
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"cvtss2si",
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"cvttpd2dq",
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"cvttpd2pi",
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"cvttps2dq",
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"cvttps2pi",
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"cvttsd2si",
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"cvttss2si",
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"cwd",
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"cwde",
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"daa",
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"das",
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"db",
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"dd",
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"dec",
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"div",
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"divpd",
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"divps",
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"divsd",
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"divss",
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"dq",
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"dt",
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"dw",
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"emms",
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"enter",
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"equ",
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"f2xm1",
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"fabs",
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"fadd",
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"faddp",
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"fbld",
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"fbstp",
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"fchs",
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"fclex",
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"fcmovb",
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"fcmovbe",
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"fcmove",
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"fcmovnb",
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"fcmovnbe",
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"fcmovne",
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"fcmovnu",
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"fcmovu",
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"fcom",
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"fcomi",
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"fcomip",
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"fcomp",
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"fcompp",
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"fcos",
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"fdecstp",
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"fdisi",
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"fdiv",
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"fdivp",
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"fdivr",
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"fdivrp",
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"femms",
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"feni",
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"ffree",
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"ffreep",
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"fiadd",
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"ficom",
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"ficomp",
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"fidiv",
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"fidivr",
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"fild",
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"fimul",
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"fincstp",
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"finit",
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"fist",
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"fistp",
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"fisttp",
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"fisub",
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"fisubr",
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"fld",
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"fld1",
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"fldcw",
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"fldenv",
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"fldl2e",
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"fldl2t",
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"fldlg2",
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"fldln2",
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"fldpi",
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"fldz",
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"fmul",
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"fmulp",
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"fnclex",
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"fndisi",
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"fneni",
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"fninit",
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"fnop",
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"fnsave",
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"fnstcw",
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"fnstenv",
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"fnstsw",
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"fpatan",
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"fprem",
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"fprem1",
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"fptan",
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"frndint",
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"frstor",
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"fsave",
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"fscale",
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"fsetpm",
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"fsin",
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"fsincos",
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"fsqrt",
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"fst",
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"fstcw",
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"fstenv",
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"fstp",
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"fstsw",
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"fsub",
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"fsubp",
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"fsubr",
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"fsubrp",
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"ftst",
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"fucom",
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"fucomi",
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"fucomip",
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"fucomp",
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"fucompp",
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"fwait",
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"fxam",
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"fxch",
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"fxrstor",
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"fxsave",
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"fxtract",
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"fyl2x",
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"fyl2xp1",
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"haddpd",
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"haddps",
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"hlt",
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"hsubpd",
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"hsubps",
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"ibts",
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"icebp",
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"idiv",
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"imul",
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"in",
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"inc",
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"incbin",
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"insb",
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"insd",
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"insw",
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"int",
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"int01",
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"int03",
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"int1",
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"int3",
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"into",
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"invd",
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"invlpg",
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"iret",
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"iretd",
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"iretw",
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"jcxz",
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"jecxz",
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"jmp",
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"jmpe",
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"lahf",
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"lar",
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"lddqu",
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"ldmxcsr",
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"lds",
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"lea",
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"leave",
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"les",
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"lfence",
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"lfs",
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"lgdt",
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"lgs",
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"lidt",
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"lldt",
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"lmsw",
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"loadall",
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"loadall286",
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"lodsb",
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"lodsd",
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"lodsw",
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"loop",
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"loope",
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"loopne",
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"loopnz",
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"loopz",
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"lsl",
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"lss",
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"ltr",
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"maskmovdqu",
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"maskmovq",
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"maxpd",
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"maxps",
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"maxsd",
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"maxss",
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"mfence",
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"minpd",
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"minps",
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"minsd",
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"minss",
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"monitor",
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"mov",
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"movapd",
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"movaps",
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"movd",
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"movddup",
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"movdq2q",
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"movdqa",
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"movdqu",
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"movhlps",
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"movhpd",
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"movhps",
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"movlhps",
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"movlpd",
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"movlps",
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"movmskpd",
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"movmskps",
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"movntdq",
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"movnti",
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"movntpd",
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"movntps",
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"movntq",
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"movq",
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"movq2dq",
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"movsb",
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"movsd",
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"movshdup",
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"movsldup",
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"movss",
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"movsw",
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"movsx",
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"movupd",
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"movups",
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"movzx",
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"mul",
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"mulpd",
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"mulps",
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"mulsd",
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"mulss",
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"mwait",
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"neg",
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"nop",
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"not",
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"or",
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"orpd",
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"orps",
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"out",
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"outsb",
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"outsd",
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"outsw",
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"packssdw",
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"packsswb",
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"packuswb",
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"paddb",
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"paddd",
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"paddq",
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"paddsb",
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"paddsiw",
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"paddsw",
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"paddusb",
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"paddusw",
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"paddw",
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"pand",
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"pandn",
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"pause",
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"paveb",
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"pavgb",
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"pavgusb",
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"pavgw",
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"pcmpeqb",
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"pcmpeqd",
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"pcmpeqw",
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"pcmpgtb",
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"pcmpgtd",
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"pcmpgtw",
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"pdistib",
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"pextrw",
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"pf2id",
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"pf2iw",
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"pfacc",
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"pfadd",
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"pfcmpeq",
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"pfcmpge",
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"pfcmpgt",
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"pfmax",
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"pfmin",
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"pfmul",
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"pfnacc",
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"pfpnacc",
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"pfrcp",
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"pfrcpit1",
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"pfrcpit2",
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"pfrsqit1",
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"pfrsqrt",
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"pfsub",
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"pfsubr",
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"pi2fd",
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"pi2fw",
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"pinsrw",
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"pmachriw",
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"pmaddwd",
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"pmagw",
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"pmaxsw",
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"pmaxub",
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"pminsw",
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"pminub",
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"pmovmskb",
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"pmulhriw",
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"pmulhrwa",
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"pmulhrwc",
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"pmulhuw",
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"pmulhw",
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"pmullw",
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"pmuludq",
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"pmvgezb",
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"pmvlzb",
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"pmvnzb",
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"pmvzb",
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"pop",
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"popa",
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"popad",
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"popaw",
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"popf",
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"popfd",
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"popfw",
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"por",
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"prefetch",
|
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"prefetchnta",
|
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"prefetcht0",
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"prefetcht1",
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"prefetcht2",
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"prefetchw",
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"psadbw",
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"pshufd",
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"pshufhw",
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"pshuflw",
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"pshufw",
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"pslld",
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"pslldq",
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"psllq",
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"psllw",
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"psrad",
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"psraw",
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"psrld",
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"psrldq",
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"psrlq",
|
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"psrlw",
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"psubb",
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"psubd",
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"psubq",
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"psubsb",
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"psubsiw",
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"psubsw",
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"psubusb",
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"psubusw",
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"psubw",
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"pswapd",
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"punpckhbw",
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"punpckhdq",
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"punpckhqdq",
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"punpckhwd",
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"punpcklbw",
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"punpckldq",
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"punpcklqdq",
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"punpcklwd",
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"push",
|
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"pusha",
|
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"pushad",
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"pushaw",
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"pushf",
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"pushfd",
|
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"pushfw",
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"pxor",
|
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"rcl",
|
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"rcpps",
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"rcpss",
|
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"rcr",
|
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"rdmsr",
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"rdpmc",
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"rdshr",
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"rdtsc",
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"resb",
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"resd",
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"resq",
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"rest",
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"resw",
|
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"ret",
|
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"retf",
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"retn",
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"rol",
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"ror",
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"rsdc",
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"rsldt",
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"rsm",
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"rsqrtps",
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"rsqrtss",
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"rsts",
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"sahf",
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"sal",
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"salc",
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"sar",
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"sbb",
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"scasb",
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"scasd",
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"scasw",
|
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"sfence",
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"sgdt",
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"shl",
|
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"shld",
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"shr",
|
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"shrd",
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"shufpd",
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"shufps",
|
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"sidt",
|
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"sldt",
|
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"smi",
|
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"smint",
|
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"smintold",
|
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"smsw",
|
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"sqrtpd",
|
|
"sqrtps",
|
|
"sqrtsd",
|
|
"sqrtss",
|
|
"stc",
|
|
"std",
|
|
"sti",
|
|
"stmxcsr",
|
|
"stosb",
|
|
"stosd",
|
|
"stosw",
|
|
"str",
|
|
"sub",
|
|
"subpd",
|
|
"subps",
|
|
"subsd",
|
|
"subss",
|
|
"svdc",
|
|
"svldt",
|
|
"svts",
|
|
"syscall",
|
|
"sysenter",
|
|
"sysexit",
|
|
"sysret",
|
|
"test",
|
|
"ucomisd",
|
|
"ucomiss",
|
|
"ud0",
|
|
"ud1",
|
|
"ud2",
|
|
"umov",
|
|
"unpckhpd",
|
|
"unpckhps",
|
|
"unpcklpd",
|
|
"unpcklps",
|
|
"verr",
|
|
"verw",
|
|
"wait",
|
|
"wbinvd",
|
|
"wrmsr",
|
|
"wrshr",
|
|
"xadd",
|
|
"xbts",
|
|
"xchg",
|
|
"xlat",
|
|
"xlatb",
|
|
"xor",
|
|
"xorpd",
|
|
"xorps",
|
|
"xstore"
|
|
};
|
|
|
|
/* Conditional instructions */
|
|
static const char *icn[] = {
|
|
"cmov",
|
|
"j",
|
|
"set"
|
|
};
|
|
|
|
/* and the corresponding opcodes */
|
|
static int ico[] = {
|
|
I_CMOVcc,
|
|
I_Jcc,
|
|
I_SETcc
|
|
};
|
|
|
|
#define INSN_MAX 32 /* one instruction can't be longer than this */
|
|
long disasm (unsigned char *data, char *output, int segsize, long offset);
|
|
extern struct itemplate **itable[];
|
|
|
|
/*
|
|
* Flags that go into the `segment' field of `insn' structures
|
|
* during disassembly.
|
|
*/
|
|
#define SEG_RELATIVE 1
|
|
#define SEG_32BIT 2
|
|
#define SEG_RMREG 4
|
|
#define SEG_DISP8 8
|
|
#define SEG_DISP16 16
|
|
#define SEG_DISP32 32
|
|
#define SEG_NODISP 64
|
|
#define SEG_SIGNED 128
|
|
|
|
static int whichreg(long regflags, int regval)
|
|
{
|
|
/* automatically generated from ./regs.dat - do not edit */
|
|
static const int creg [] = {R_CR0,R_CR1,R_CR2,R_CR3,R_CR4,R_CR5,R_CR6,R_CR7};
|
|
static const int dreg [] = {R_DR0,R_DR1,R_DR2,R_DR3,R_DR4,R_DR5,R_DR6,R_DR7};
|
|
static const int fpureg [] = {R_ST0,R_ST1,R_ST2,R_ST3,R_ST4,R_ST5,R_ST6,R_ST7};
|
|
static const int mmxreg [] = {R_MM0,R_MM1,R_MM2,R_MM3,R_MM4,R_MM5,R_MM6,R_MM7};
|
|
static const int reg16 [] = {R_AX,R_CX,R_DX,R_BX,R_SP,R_BP,R_SI,R_DI};
|
|
static const int reg32 [] = {R_EAX,R_ECX,R_EDX,R_EBX,R_ESP,R_EBP,R_ESI,R_EDI};
|
|
static const int reg8 [] = {R_AL,R_CL,R_DL,R_BL,R_AH,R_CH,R_DH,R_BH};
|
|
static const int sreg [] = {R_ES,R_CS,R_SS,R_DS,R_FS,R_GS,R_SEGR6,R_SEGR7};
|
|
static const int treg [] = {R_TR0,R_TR1,R_TR2,R_TR3,R_TR4,R_TR5,R_TR6,R_TR7};
|
|
static const int xmmreg [] = {R_XMM0,R_XMM1,R_XMM2,R_XMM3,R_XMM4,R_XMM5,R_XMM6,R_XMM7};
|
|
|
|
if (!(REG_AL & ~regflags))
|
|
return R_AL;
|
|
if (!(REG_AX & ~regflags))
|
|
return R_AX;
|
|
if (!(REG_EAX & ~regflags))
|
|
return R_EAX;
|
|
if (!(REG_DL & ~regflags))
|
|
return R_DL;
|
|
if (!(REG_DX & ~regflags))
|
|
return R_DX;
|
|
if (!(REG_EDX & ~regflags))
|
|
return R_EDX;
|
|
if (!(REG_CL & ~regflags))
|
|
return R_CL;
|
|
if (!(REG_CX & ~regflags))
|
|
return R_CX;
|
|
if (!(REG_ECX & ~regflags))
|
|
return R_ECX;
|
|
if (!(FPU0 & ~regflags))
|
|
return R_ST0;
|
|
if (!(REG_CS & ~regflags))
|
|
return (regval == 1) ? R_CS : 0;
|
|
if (!(REG_DESS & ~regflags))
|
|
return (regval == 0 || regval == 2 || regval == 3 ? sreg[regval] : 0);
|
|
if (!(REG_FSGS & ~regflags))
|
|
return (regval == 4 || regval == 5 ? sreg[regval] : 0);
|
|
if (!(REG_SEG67 & ~regflags))
|
|
return (regval == 6 || regval == 7 ? sreg[regval] : 0);
|
|
|
|
/* All the entries below look up regval in an 8-entry array */
|
|
if (regval < 0 || regval > 7)
|
|
return 0;
|
|
|
|
if (!((REGMEM|BITS8) & ~regflags))
|
|
return reg8[regval];
|
|
if (!((REGMEM|BITS16) & ~regflags))
|
|
return reg16[regval];
|
|
if (!((REGMEM|BITS32) & ~regflags))
|
|
return reg32[regval];
|
|
if (!(REG_SREG & ~regflags))
|
|
return sreg[regval];
|
|
if (!(REG_CREG & ~regflags))
|
|
return creg[regval];
|
|
if (!(REG_DREG & ~regflags))
|
|
return dreg[regval];
|
|
if (!(REG_TREG & ~regflags))
|
|
return treg[regval];
|
|
if (!(FPUREG & ~regflags))
|
|
return fpureg[regval];
|
|
if (!(MMXREG & ~regflags))
|
|
return mmxreg[regval];
|
|
if (!(XMMREG & ~regflags))
|
|
return xmmreg[regval];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const char *whichcond(int condval)
|
|
{
|
|
static int conds[] = {
|
|
C_O, C_NO, C_C, C_NC, C_Z, C_NZ, C_NA, C_A,
|
|
C_S, C_NS, C_PE, C_PO, C_L, C_NL, C_NG, C_G
|
|
};
|
|
return conditions[conds[condval]];
|
|
}
|
|
|
|
/*
|
|
* Process an effective address (ModRM) specification.
|
|
*/
|
|
static unsigned char *do_ea (unsigned char *data, int modrm, int asize,
|
|
int segsize, operand *op)
|
|
{
|
|
int mod, rm, scale, index, base;
|
|
|
|
mod = (modrm >> 6) & 03;
|
|
rm = modrm & 07;
|
|
|
|
if (mod == 3) { /* pure register version */
|
|
op->basereg = rm;
|
|
op->segment |= SEG_RMREG;
|
|
return data;
|
|
}
|
|
|
|
op->addr_size = 0;
|
|
|
|
if (asize == 16) {
|
|
/*
|
|
* <mod> specifies the displacement size (none, byte or
|
|
* word), and <rm> specifies the register combination.
|
|
* Exception: mod=0,rm=6 does not specify [BP] as one might
|
|
* expect, but instead specifies [disp16].
|
|
*/
|
|
op->indexreg = op->basereg = -1;
|
|
op->scale = 1; /* always, in 16 bits */
|
|
switch (rm) {
|
|
case 0: op->basereg = R_BX; op->indexreg = R_SI; break;
|
|
case 1: op->basereg = R_BX; op->indexreg = R_DI; break;
|
|
case 2: op->basereg = R_BP; op->indexreg = R_SI; break;
|
|
case 3: op->basereg = R_BP; op->indexreg = R_DI; break;
|
|
case 4: op->basereg = R_SI; break;
|
|
case 5: op->basereg = R_DI; break;
|
|
case 6: op->basereg = R_BP; break;
|
|
case 7: op->basereg = R_BX; break;
|
|
}
|
|
if (rm == 6 && mod == 0) { /* special case */
|
|
op->basereg = -1;
|
|
if (segsize != 16)
|
|
op->addr_size = 16;
|
|
mod = 2; /* fake disp16 */
|
|
}
|
|
switch (mod) {
|
|
case 0:
|
|
op->segment |= SEG_NODISP;
|
|
break;
|
|
case 1:
|
|
op->segment |= SEG_DISP8;
|
|
op->offset = (signed char) *data++;
|
|
break;
|
|
case 2:
|
|
op->segment |= SEG_DISP16;
|
|
op->offset = *data++;
|
|
op->offset |= ((unsigned) *data++) << 8;
|
|
break;
|
|
}
|
|
return data;
|
|
} else {
|
|
/*
|
|
* Once again, <mod> specifies displacement size (this time
|
|
* none, byte or *dword*), while <rm> specifies the base
|
|
* register. Again, [EBP] is missing, replaced by a pure
|
|
* disp32 (this time that's mod=0,rm=*5*). However, rm=4
|
|
* indicates not a single base register, but instead the
|
|
* presence of a SIB byte...
|
|
*/
|
|
op->indexreg = -1;
|
|
switch (rm) {
|
|
case 0: op->basereg = R_EAX; break;
|
|
case 1: op->basereg = R_ECX; break;
|
|
case 2: op->basereg = R_EDX; break;
|
|
case 3: op->basereg = R_EBX; break;
|
|
case 5: op->basereg = R_EBP; break;
|
|
case 6: op->basereg = R_ESI; break;
|
|
case 7: op->basereg = R_EDI; break;
|
|
}
|
|
if (rm == 5 && mod == 0) {
|
|
op->basereg = -1;
|
|
if (segsize != 32)
|
|
op->addr_size = 32;
|
|
mod = 2; /* fake disp32 */
|
|
}
|
|
if (rm == 4) { /* process SIB */
|
|
scale = (*data >> 6) & 03;
|
|
index = (*data >> 3) & 07;
|
|
base = *data & 07;
|
|
data++;
|
|
|
|
op->scale = 1 << scale;
|
|
switch (index) {
|
|
case 0: op->indexreg = R_EAX; break;
|
|
case 1: op->indexreg = R_ECX; break;
|
|
case 2: op->indexreg = R_EDX; break;
|
|
case 3: op->indexreg = R_EBX; break;
|
|
case 4: op->indexreg = -1; break;
|
|
case 5: op->indexreg = R_EBP; break;
|
|
case 6: op->indexreg = R_ESI; break;
|
|
case 7: op->indexreg = R_EDI; break;
|
|
}
|
|
|
|
switch (base) {
|
|
case 0: op->basereg = R_EAX; break;
|
|
case 1: op->basereg = R_ECX; break;
|
|
case 2: op->basereg = R_EDX; break;
|
|
case 3: op->basereg = R_EBX; break;
|
|
case 4: op->basereg = R_ESP; break;
|
|
case 6: op->basereg = R_ESI; break;
|
|
case 7: op->basereg = R_EDI; break;
|
|
case 5:
|
|
if (mod == 0) {
|
|
mod = 2;
|
|
op->basereg = -1;
|
|
} else
|
|
op->basereg = R_EBP;
|
|
break;
|
|
}
|
|
}
|
|
switch (mod) {
|
|
case 0:
|
|
op->segment |= SEG_NODISP;
|
|
break;
|
|
case 1:
|
|
op->segment |= SEG_DISP8;
|
|
op->offset = (signed char) *data++;
|
|
break;
|
|
case 2:
|
|
op->segment |= SEG_DISP32;
|
|
op->offset = *data++;
|
|
op->offset |= ((unsigned) *data++) << 8;
|
|
op->offset |= ((long) *data++) << 16;
|
|
op->offset |= ((long) *data++) << 24;
|
|
break;
|
|
}
|
|
return data;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Determine whether the instruction template in t corresponds to the data
|
|
* stream in data. Return the number of bytes matched if so.
|
|
*/
|
|
static int matches (struct itemplate *t, unsigned char *data, int asize,
|
|
int osize, int segsize, int rep, insn *ins)
|
|
{
|
|
unsigned char * r = (unsigned char *)(t->code);
|
|
unsigned char * origdata = data;
|
|
int a_used = FALSE, o_used = FALSE;
|
|
int drep = 0;
|
|
|
|
if ( rep == 0xF2 )
|
|
drep = P_REPNE;
|
|
else if ( rep == 0xF3 )
|
|
drep = P_REP;
|
|
|
|
while (*r)
|
|
{
|
|
int c = *r++;
|
|
if (c >= 01 && c <= 03) {
|
|
while (c--)
|
|
if (*r++ != *data++)
|
|
return FALSE;
|
|
}
|
|
if (c == 04) {
|
|
switch (*data++) {
|
|
case 0x07: ins->oprs[0].basereg = 0; break;
|
|
case 0x17: ins->oprs[0].basereg = 2; break;
|
|
case 0x1F: ins->oprs[0].basereg = 3; break;
|
|
default: return FALSE;
|
|
}
|
|
}
|
|
if (c == 05) {
|
|
switch (*data++) {
|
|
case 0xA1: ins->oprs[0].basereg = 4; break;
|
|
case 0xA9: ins->oprs[0].basereg = 5; break;
|
|
default: return FALSE;
|
|
}
|
|
}
|
|
if (c == 06) {
|
|
switch (*data++) {
|
|
case 0x06: ins->oprs[0].basereg = 0; break;
|
|
case 0x0E: ins->oprs[0].basereg = 1; break;
|
|
case 0x16: ins->oprs[0].basereg = 2; break;
|
|
case 0x1E: ins->oprs[0].basereg = 3; break;
|
|
default: return FALSE;
|
|
}
|
|
}
|
|
if (c == 07) {
|
|
switch (*data++) {
|
|
case 0xA0: ins->oprs[0].basereg = 4; break;
|
|
case 0xA8: ins->oprs[0].basereg = 5; break;
|
|
default: return FALSE;
|
|
}
|
|
}
|
|
if (c >= 010 && c <= 012) {
|
|
int t = *r++, d = *data++;
|
|
if (d < t || d > t+7)
|
|
return FALSE;
|
|
else {
|
|
ins->oprs[c-010].basereg = d-t;
|
|
ins->oprs[c-010].segment |= SEG_RMREG;
|
|
}
|
|
}
|
|
if (c == 017)
|
|
if (*data++)
|
|
return FALSE;
|
|
if (c >= 014 && c <= 016) {
|
|
ins->oprs[c-014].offset = (signed char) *data++;
|
|
ins->oprs[c-014].segment |= SEG_SIGNED;
|
|
}
|
|
if (c >= 020 && c <= 022)
|
|
ins->oprs[c-020].offset = *data++;
|
|
if (c >= 024 && c <= 026)
|
|
ins->oprs[c-024].offset = *data++;
|
|
if (c >= 030 && c <= 032) {
|
|
ins->oprs[c-030].offset = *data++;
|
|
ins->oprs[c-030].offset |= (((unsigned) *data++) << 8);
|
|
}
|
|
if (c >= 034 && c <= 036) {
|
|
ins->oprs[c-034].offset = *data++;
|
|
ins->oprs[c-034].offset |= (((unsigned) *data++) << 8);
|
|
if (osize == 32) {
|
|
ins->oprs[c-034].offset |= (((long) *data++) << 16);
|
|
ins->oprs[c-034].offset |= (((long) *data++) << 24);
|
|
}
|
|
if (segsize != asize)
|
|
ins->oprs[c-034].addr_size = asize;
|
|
}
|
|
if (c >= 040 && c <= 042) {
|
|
ins->oprs[c-040].offset = *data++;
|
|
ins->oprs[c-040].offset |= (((unsigned) *data++) << 8);
|
|
ins->oprs[c-040].offset |= (((long) *data++) << 16);
|
|
ins->oprs[c-040].offset |= (((long) *data++) << 24);
|
|
}
|
|
if (c >= 044 && c <= 046) {
|
|
ins->oprs[c-044].offset = *data++;
|
|
ins->oprs[c-044].offset |= (((unsigned) *data++) << 8);
|
|
if (asize == 32) {
|
|
ins->oprs[c-044].offset |= (((long) *data++) << 16);
|
|
ins->oprs[c-044].offset |= (((long) *data++) << 24);
|
|
}
|
|
if (segsize != asize)
|
|
ins->oprs[c-044].addr_size = asize;
|
|
}
|
|
if (c >= 050 && c <= 052) {
|
|
ins->oprs[c-050].offset = (signed char) *data++;
|
|
ins->oprs[c-050].segment |= SEG_RELATIVE;
|
|
}
|
|
if (c >= 060 && c <= 062) {
|
|
ins->oprs[c-060].offset = *data++;
|
|
ins->oprs[c-060].offset |= (((unsigned) *data++) << 8);
|
|
ins->oprs[c-060].segment |= SEG_RELATIVE;
|
|
ins->oprs[c-060].segment &= ~SEG_32BIT;
|
|
}
|
|
if (c >= 064 && c <= 066) {
|
|
ins->oprs[c-064].offset = *data++;
|
|
ins->oprs[c-064].offset |= (((unsigned) *data++) << 8);
|
|
if (osize == 32) {
|
|
ins->oprs[c-064].offset |= (((long) *data++) << 16);
|
|
ins->oprs[c-064].offset |= (((long) *data++) << 24);
|
|
ins->oprs[c-064].segment |= SEG_32BIT;
|
|
} else
|
|
ins->oprs[c-064].segment &= ~SEG_32BIT;
|
|
ins->oprs[c-064].segment |= SEG_RELATIVE;
|
|
if (segsize != osize) {
|
|
ins->oprs[c-064].type =
|
|
(ins->oprs[c-064].type & NON_SIZE)
|
|
| ((osize == 16) ? BITS16 : BITS32);
|
|
}
|
|
}
|
|
if (c >= 070 && c <= 072) {
|
|
ins->oprs[c-070].offset = *data++;
|
|
ins->oprs[c-070].offset |= (((unsigned) *data++) << 8);
|
|
ins->oprs[c-070].offset |= (((long) *data++) << 16);
|
|
ins->oprs[c-070].offset |= (((long) *data++) << 24);
|
|
ins->oprs[c-070].segment |= SEG_32BIT | SEG_RELATIVE;
|
|
}
|
|
if (c >= 0100 && c < 0130) {
|
|
int modrm = *data++;
|
|
ins->oprs[c & 07].basereg = (modrm >> 3) & 07;
|
|
ins->oprs[c & 07].segment |= SEG_RMREG;
|
|
data = do_ea (data, modrm, asize, segsize,
|
|
&ins->oprs[(c >> 3) & 07]);
|
|
}
|
|
if (c >= 0130 && c <= 0132) {
|
|
ins->oprs[c-0130].offset = *data++;
|
|
ins->oprs[c-0130].offset |= (((unsigned) *data++) << 8);
|
|
}
|
|
if (c >= 0140 && c <= 0142) {
|
|
ins->oprs[c-0140].offset = *data++;
|
|
ins->oprs[c-0140].offset |= (((unsigned) *data++) << 8);
|
|
ins->oprs[c-0140].offset |= (((long) *data++) << 16);
|
|
ins->oprs[c-0140].offset |= (((long) *data++) << 24);
|
|
}
|
|
if (c >= 0200 && c <= 0277) {
|
|
int modrm = *data++;
|
|
if (((modrm >> 3) & 07) != (c & 07))
|
|
return FALSE; /* spare field doesn't match up */
|
|
data = do_ea (data, modrm, asize, segsize,
|
|
&ins->oprs[(c >> 3) & 07]);
|
|
}
|
|
if (c >= 0300 && c <= 0302) {
|
|
if (asize)
|
|
ins->oprs[c-0300].segment |= SEG_32BIT;
|
|
else
|
|
ins->oprs[c-0300].segment &= ~SEG_32BIT;
|
|
a_used = TRUE;
|
|
}
|
|
if (c == 0310) {
|
|
if (asize == 32)
|
|
return FALSE;
|
|
else
|
|
a_used = TRUE;
|
|
}
|
|
if (c == 0311) {
|
|
if (asize == 16)
|
|
return FALSE;
|
|
else
|
|
a_used = TRUE;
|
|
}
|
|
if (c == 0312) {
|
|
if (asize != segsize)
|
|
return FALSE;
|
|
else
|
|
a_used = TRUE;
|
|
}
|
|
if (c == 0320) {
|
|
if (osize == 32)
|
|
return FALSE;
|
|
else
|
|
o_used = TRUE;
|
|
}
|
|
if (c == 0321) {
|
|
if (osize == 16)
|
|
return FALSE;
|
|
else
|
|
o_used = TRUE;
|
|
}
|
|
if (c == 0322) {
|
|
if (osize != segsize)
|
|
return FALSE;
|
|
else
|
|
o_used = TRUE;
|
|
}
|
|
if (c == 0330) {
|
|
int t = *r++, d = *data++;
|
|
if (d < t || d > t+15)
|
|
return FALSE;
|
|
else
|
|
ins->condition = d - t;
|
|
}
|
|
if (c == 0331) {
|
|
if ( rep )
|
|
return FALSE;
|
|
}
|
|
if (c == 0332) {
|
|
if (drep == P_REP)
|
|
drep = P_REPE;
|
|
}
|
|
if (c == 0333) {
|
|
if ( rep != 0xF3 )
|
|
return FALSE;
|
|
drep = 0;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Check for unused rep or a/o prefixes.
|
|
*/
|
|
ins->nprefix = 0;
|
|
if (drep)
|
|
ins->prefixes[ins->nprefix++] = drep;
|
|
if (!a_used && asize != segsize)
|
|
ins->prefixes[ins->nprefix++] = (asize == 16 ? P_A16 : P_A32);
|
|
if (!o_used && osize != segsize)
|
|
ins->prefixes[ins->nprefix++] = (osize == 16 ? P_O16 : P_O32);
|
|
|
|
return data - origdata;
|
|
}
|
|
|
|
long disasm (unsigned char *data, char *output, int segsize, long offset)
|
|
{
|
|
struct itemplate **p, **best_p;
|
|
int length, best_length = 0;
|
|
const char *segover;
|
|
int rep, lock, asize, osize, i, slen, colon;
|
|
unsigned char *origdata;
|
|
int works;
|
|
insn tmp_ins = { NULL }, ins;
|
|
unsigned long goodness, best;
|
|
|
|
/*
|
|
* Scan for prefixes.
|
|
*/
|
|
asize = osize = segsize;
|
|
segover = NULL;
|
|
ins.condition = ins.nprefix = rep = lock = 0;
|
|
origdata = data;
|
|
for (;;) {
|
|
if (*data == 0xF3 || *data == 0xF2)
|
|
rep = *data++;
|
|
else if (*data == 0xF0)
|
|
lock = *data++;
|
|
else if (*data == 0x2E || *data == 0x36 || *data == 0x3E ||
|
|
*data == 0x26 || *data == 0x64 || *data == 0x65) {
|
|
switch (*data++) {
|
|
case 0x2E: segover = "cs"; break;
|
|
case 0x36: segover = "ss"; break;
|
|
case 0x3E: segover = "ds"; break;
|
|
case 0x26: segover = "es"; break;
|
|
case 0x64: segover = "fs"; break;
|
|
case 0x65: segover = "gs"; break;
|
|
}
|
|
} else if (*data == 0x66) {
|
|
osize = 48 - segsize;
|
|
data++;
|
|
}
|
|
else if (*data == 0x67) {
|
|
asize = 48 - segsize;
|
|
data++;
|
|
}
|
|
else
|
|
break;
|
|
}
|
|
|
|
tmp_ins.oprs[0].segment = tmp_ins.oprs[1].segment =
|
|
tmp_ins.oprs[2].segment =
|
|
tmp_ins.oprs[0].addr_size = tmp_ins.oprs[1].addr_size =
|
|
tmp_ins.oprs[2].addr_size = (segsize == 16 ? 0 : SEG_32BIT);
|
|
tmp_ins.condition = -1;
|
|
best = ~0UL; /* Worst possible */
|
|
best_p = NULL;
|
|
for (p = itable[*data]; *p; p++) {
|
|
if ( (length = matches(*p, data, asize, osize,
|
|
segsize, rep, &tmp_ins)) ) {
|
|
works = TRUE;
|
|
/*
|
|
* Final check to make sure the types of r/m match up.
|
|
*/
|
|
for (i = 0; i < (*p)->operands; i++) {
|
|
if (
|
|
/* If it's a mem-only EA but we have a register, die. */
|
|
((tmp_ins.oprs[i].segment & SEG_RMREG) &&
|
|
!(MEMORY & ~(*p)->opd[i])) ||
|
|
|
|
/* If it's a reg-only EA but we have a memory ref, die. */
|
|
(!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
|
|
!(REGNORM & ~(*p)->opd[i]) &&
|
|
!((*p)->opd[i] & REG_SMASK)) ||
|
|
|
|
/* Register type mismatch (eg FS vs REG_DESS): die. */
|
|
((((*p)->opd[i] & (REGISTER | FPUREG)) ||
|
|
(tmp_ins.oprs[i].segment & SEG_RMREG)) &&
|
|
!whichreg ((*p)->opd[i], tmp_ins.oprs[i].basereg))) {
|
|
works = FALSE;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (works) {
|
|
goodness = (*p)->flags & IF_PFMASK;
|
|
if ( goodness < best ) {
|
|
/* This is the best one found so far */
|
|
best = goodness;
|
|
best_p = p;
|
|
best_length = length;
|
|
ins = tmp_ins;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!best_p) { /* no instruction was matched */
|
|
sprintf(output, "db 0%02xh", data[0]);
|
|
return 1;
|
|
}
|
|
|
|
/* Pick the best match */
|
|
p = best_p;
|
|
length = best_length;
|
|
|
|
slen = 0;
|
|
|
|
if (lock)
|
|
slen += sprintf(output+slen, "lock ");
|
|
for (i = 0; i < ins.nprefix; i++)
|
|
switch (ins.prefixes[i]) {
|
|
case P_REP: slen += sprintf(output+slen, "rep "); break;
|
|
case P_REPE: slen += sprintf(output+slen, "repe "); break;
|
|
case P_REPNE: slen += sprintf(output+slen, "repne "); break;
|
|
case P_A16: slen += sprintf(output+slen, "a16 "); break;
|
|
case P_A32: slen += sprintf(output+slen, "a32 "); break;
|
|
case P_O16: slen += sprintf(output+slen, "o16 "); break;
|
|
case P_O32: slen += sprintf(output+slen, "o32 "); break;
|
|
}
|
|
|
|
for (i = 0; i < (int)elements(ico); i++)
|
|
if ((*p)->opcode == ico[i]) {
|
|
slen += sprintf(output+slen, "%s%s", icn[i],
|
|
whichcond(ins.condition));
|
|
break;
|
|
}
|
|
if (i >= (int)elements(ico))
|
|
slen += sprintf(output+slen, "%s", insn_names[(*p)->opcode]);
|
|
colon = FALSE;
|
|
length += data - origdata; /* fix up for prefixes */
|
|
for (i=0; i<(*p)->operands; i++) {
|
|
output[slen++] = (colon ? ':' : i==0 ? ' ' : ',');
|
|
|
|
if (ins.oprs[i].segment & SEG_RELATIVE) {
|
|
ins.oprs[i].offset += offset + length;
|
|
/*
|
|
* sort out wraparound
|
|
*/
|
|
if (!(ins.oprs[i].segment & SEG_32BIT))
|
|
ins.oprs[i].offset &= 0xFFFF;
|
|
}
|
|
|
|
if ((*p)->opd[i] & COLON)
|
|
colon = TRUE;
|
|
else
|
|
colon = FALSE;
|
|
|
|
if (((*p)->opd[i] & (REGISTER | FPUREG)) ||
|
|
(ins.oprs[i].segment & SEG_RMREG))
|
|
{
|
|
ins.oprs[i].basereg = whichreg ((*p)->opd[i],
|
|
ins.oprs[i].basereg);
|
|
if ( (*p)->opd[i] & TO )
|
|
slen += sprintf(output+slen, "to ");
|
|
slen += sprintf(output+slen, "%s",
|
|
reg_names[ins.oprs[i].basereg-EXPR_REG_START]);
|
|
} else if (!(UNITY & ~(*p)->opd[i])) {
|
|
output[slen++] = '1';
|
|
} else if ( (*p)->opd[i] & IMMEDIATE ) {
|
|
if ( (*p)->opd[i] & BITS8 ) {
|
|
slen += sprintf(output+slen, "byte ");
|
|
if (ins.oprs[i].segment & SEG_SIGNED) {
|
|
if (ins.oprs[i].offset < 0) {
|
|
ins.oprs[i].offset *= -1;
|
|
output[slen++] = '-';
|
|
} else
|
|
output[slen++] = '+';
|
|
}
|
|
} else if ( (*p)->opd[i] & BITS16 ) {
|
|
slen += sprintf(output+slen, "word ");
|
|
} else if ( (*p)->opd[i] & BITS32 ) {
|
|
slen += sprintf(output+slen, "dword ");
|
|
} else if ( (*p)->opd[i] & NEAR ) {
|
|
slen += sprintf(output+slen, "near ");
|
|
} else if ( (*p)->opd[i] & SHORT ) {
|
|
slen += sprintf(output+slen, "short ");
|
|
}
|
|
slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
|
|
} else if ( !(MEM_OFFS & ~(*p)->opd[i]) ) {
|
|
slen += sprintf(output+slen, "[%s%s%s0x%lx]",
|
|
(segover ? segover : ""),
|
|
(segover ? ":" : ""),
|
|
(ins.oprs[i].addr_size == 32 ? "dword " :
|
|
ins.oprs[i].addr_size == 16 ? "word " : ""),
|
|
ins.oprs[i].offset);
|
|
segover = NULL;
|
|
} else if ( !(REGMEM & ~(*p)->opd[i]) ) {
|
|
int started = FALSE;
|
|
if ( (*p)->opd[i] & BITS8 )
|
|
slen += sprintf(output+slen, "byte ");
|
|
if ( (*p)->opd[i] & BITS16 )
|
|
slen += sprintf(output+slen, "word ");
|
|
if ( (*p)->opd[i] & BITS32 )
|
|
slen += sprintf(output+slen, "dword ");
|
|
if ( (*p)->opd[i] & BITS64 )
|
|
slen += sprintf(output+slen, "qword ");
|
|
if ( (*p)->opd[i] & BITS80 )
|
|
slen += sprintf(output+slen, "tword ");
|
|
if ( (*p)->opd[i] & FAR )
|
|
slen += sprintf(output+slen, "far ");
|
|
if ( (*p)->opd[i] & NEAR )
|
|
slen += sprintf(output+slen, "near ");
|
|
output[slen++] = '[';
|
|
if (ins.oprs[i].addr_size)
|
|
slen += sprintf(output+slen, "%s",
|
|
(ins.oprs[i].addr_size == 32 ? "dword " :
|
|
ins.oprs[i].addr_size == 16 ? "word " : ""));
|
|
if (segover) {
|
|
slen += sprintf(output+slen, "%s:", segover);
|
|
segover = NULL;
|
|
}
|
|
if (ins.oprs[i].basereg != -1) {
|
|
slen += sprintf(output+slen, "%s",
|
|
reg_names[(ins.oprs[i].basereg -
|
|
EXPR_REG_START)]);
|
|
started = TRUE;
|
|
}
|
|
if (ins.oprs[i].indexreg != -1) {
|
|
if (started)
|
|
output[slen++] = '+';
|
|
slen += sprintf(output+slen, "%s",
|
|
reg_names[(ins.oprs[i].indexreg -
|
|
EXPR_REG_START)]);
|
|
if (ins.oprs[i].scale > 1)
|
|
slen += sprintf(output+slen, "*%d", ins.oprs[i].scale);
|
|
started = TRUE;
|
|
}
|
|
if (ins.oprs[i].segment & SEG_DISP8) {
|
|
int sign = '+';
|
|
if (ins.oprs[i].offset & 0x80) {
|
|
ins.oprs[i].offset = - (signed char) ins.oprs[i].offset;
|
|
sign = '-';
|
|
}
|
|
slen += sprintf(output+slen, "%c0x%lx", sign,
|
|
ins.oprs[i].offset);
|
|
} else if (ins.oprs[i].segment & SEG_DISP16) {
|
|
if (started)
|
|
output[slen++] = '+';
|
|
slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
|
|
} else if (ins.oprs[i].segment & SEG_DISP32) {
|
|
if (started)
|
|
output[slen++] = '+';
|
|
slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
|
|
}
|
|
output[slen++] = ']';
|
|
} else {
|
|
slen += sprintf(output+slen, "<operand%d>", i);
|
|
}
|
|
}
|
|
output[slen] = '\0';
|
|
if (segover) { /* unused segment override */
|
|
char *p = output;
|
|
int count = slen+1;
|
|
while (count--)
|
|
p[count+3] = p[count];
|
|
strncpy (output, segover, 2);
|
|
output[2] = ' ';
|
|
}
|
|
return length;
|
|
}
|