209 lines
6.3 KiB
C
209 lines
6.3 KiB
C
/* i8253.c: Intel i8253 PIT adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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?? ??? 10 - Original file.
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16 Dec 12 - Modified to use isbc_80_10.cfg file to set baseport and size.
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24 Apr 15 -- Modified to use simh_debug
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NOTES:
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*/
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#include "system_defs.h"
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/* external globals */
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
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/* globals */
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/* function prototypes */
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t_stat i8253_cfg(uint8 base, uint8 devnum);
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t_stat i8253_svc (UNIT *uptr);
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t_stat i8253_reset (DEVICE *dptr);
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uint8 i8253t0(t_bool io, uint8 data, uint8 devnum);
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uint8 i8253t1(t_bool io, uint8 data, uint8 devnum);
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uint8 i8253t2(t_bool io, uint8 data, uint8 devnum);
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uint8 i8253c(t_bool io, uint8 data, uint8 devnum);
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/* i8253 Standard I/O Data Structures */
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/* up to 4 i8253 devices */
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UNIT i8253_unit[] = {
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{ UDATA (&i8253_svc, 0, 0), 20 },
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{ UDATA (&i8253_svc, 0, 0), 20 },
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{ UDATA (&i8253_svc, 0, 0), 20 },
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{ UDATA (&i8253_svc, 0, 0), 20 }
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};
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REG i8253_reg[] = {
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{ HRDATA (T0, i8253_unit[0].u3, 8) },
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{ HRDATA (T1, i8253_unit[0].u4, 8) },
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{ HRDATA (T2, i8253_unit[0].u5, 8) },
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{ HRDATA (CMD, i8253_unit[0].u6, 8) },
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{ HRDATA (T0, i8253_unit[1].u3, 8) },
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{ HRDATA (T1, i8253_unit[1].u4, 8) },
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{ HRDATA (T2, i8253_unit[1].u5, 8) },
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{ HRDATA (CMD, i8253_unit[1].u6, 8) },
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{ NULL }
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};
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DEBTAB i8253_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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MTAB i8253_mod[] = {
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE i8253_dev = {
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"I8253", //name
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i8253_unit, //units
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i8253_reg, //registers
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i8253_mod, //modifiers
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I8253_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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i8253_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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i8253_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* Service routines to handle simulator functions */
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// i8253 configuration
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t_stat i8253_cfg(uint8 base, uint8 devnum)
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{
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sim_printf(" i8253[%d]: at base port 0%02XH\n",
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devnum, base & 0xFF);
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reg_dev(i8253t0, base, devnum);
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reg_dev(i8253t1, base + 1, devnum);
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reg_dev(i8253t2, base + 2, devnum);
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reg_dev(i8253c, base + 3, devnum);
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return SCPE_OK;
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}
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/* i8253_svc - actually gets char & places in buffer */
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t_stat i8253_svc (UNIT *uptr)
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{
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sim_activate (&i8253_unit[0], i8253_unit[0].wait); /* continue poll */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat i8253_reset (DEVICE *dptr)
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{
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uint8 devnum;
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for (devnum=0; devnum<I8253_NUM; devnum++) {
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i8253_unit[devnum].u3 = 0; /* status */
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i8253_unit[devnum].u4 = 0; /* mode instruction */
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i8253_unit[devnum].u5 = 0; /* command instruction */
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i8253_unit[devnum].u6 = 0;
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}
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return SCPE_OK;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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uint8 i8253t0(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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return i8253_unit[devnum].u3;
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} else { /* write data port */
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i8253_unit[devnum].u3 = data;
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//sim_activate_after (&i8253_unit[devnum], );
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return 0;
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}
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return 0;
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}
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//read routine:
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//sim_activate_time(&i8253_unit[devnum])/sim_inst_per_second()
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uint8 i8253t1(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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return i8253_unit[devnum].u4;
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} else { /* write data port */
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i8253_unit[devnum].u4 = data;
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return 0;
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}
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return 0;
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}
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uint8 i8253t2(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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return i8253_unit[devnum].u5;
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} else { /* write data port */
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i8253_unit[devnum].u5 = data;
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return 0;
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}
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return 0;
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}
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uint8 i8253c(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read status port */
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return i8253_unit[devnum].u6;
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} else { /* write data port */
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i8253_unit[devnum].u6 = data;
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return 0;
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}
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return 0;
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}
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/* end of i8253.c */
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