9d849283a4
- This change introduces a full refactor of the interrupt subsystem
for the system board (SBD) and the I/O bus (CIO). Interrupt decode
should now be significantly faster, and not require an expensive
calculation on every step.
- The TIMER device has been split into Rev 2 and Rev 3
implementations.
- The optional 3B2/400 Debug Monitor ROMs can now be booted by passing
the "DEMON" argument to the 3B2/400 simulator BOOT command. Any
of the following will cause the Debug Monitor ROM to be booted
instead of the standard 3B2/400 ROM:
sim> BOOT DEMON
sim> BOOT CPU DEMON
sim> BOOT DEMON CPU
299 lines
7.6 KiB
C
299 lines
7.6 KiB
C
/* 3b2_rev3_csr.c: AT&T 3B2/600G Control and Status Register
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Copyright (c) 2020, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#include "3b2_cpu.h"
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#include "3b2_csr.h"
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#include "3b2_if.h"
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#include "3b2_timer.h"
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uint32 csr_data;
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BITFIELD csr_bits[] = {
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BIT(UTIM),
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BIT(PWDN),
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BIT(OI15),
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BIT(IUINT),
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BIT(IUDMA),
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BIT(PIR9),
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BIT(PIR8),
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BIT(IUTIM),
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BIT(ISTY),
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BIT(IUBUS),
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BIT(IFLT),
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BIT(ISBER),
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BIT(IBUS),
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BIT(IBUB),
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BIT(FECC),
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BIT(THERM),
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BIT(FLED),
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BIT(PSPWR),
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BIT(FLSPD),
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BIT(FLSD1),
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BIT(FLMOT),
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BIT(FLDEN),
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BIT(FLSZ),
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BIT(SBER),
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BIT(MBER),
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BIT(UBFL),
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BIT(TIMO),
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BIT(FLTFR),
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BIT(DALGN),
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BIT(STTIM),
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BIT(ABRT),
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BIT(RSTR),
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ENDBITS
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};
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UNIT csr_unit = {
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UDATA(NULL, UNIT_FIX, CSRSIZE)
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};
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REG csr_reg[] = {
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{ HRDATADF(DATA, csr_data, 32, "CSR Data", csr_bits) },
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{ NULL }
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};
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DEVICE csr_dev = {
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"CSR", &csr_unit, csr_reg, NULL,
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1, 16, 8, 4, 16, 32,
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&csr_ex, &csr_dep, &csr_reset,
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NULL, NULL, NULL, NULL,
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DEV_DEBUG, 0, sys_deb_tab
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};
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t_stat csr_ex(t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
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{
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return SCPE_OK;
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}
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t_stat csr_dep(t_value val, t_addr exta, UNIT *uptr, int32 sw)
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{
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return SCPE_OK;
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}
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t_stat csr_reset(DEVICE *dptr)
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{
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/* Accordig to the technical reference manual, the CSR is NOT
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cleared on reset */
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return SCPE_OK;
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}
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uint32 csr_read(uint32 pa, size_t size)
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{
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uint32 reg = (pa - CSRBASE) & 0xff;
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switch (reg & 0xf0) {
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case 0x00:
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return csr_data & 0xff;
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case 0x20:
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return (csr_data >> 8) & 0xff;
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case 0x40:
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return (csr_data >> 16) & 0xff;
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case 0x60:
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return (csr_data >> 24) & 0xff;
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default:
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sim_debug(WRITE_MSG, &csr_dev,
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"[%08x] CSR READ. Warning, unexpected register = %02x)\n",
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R[NUM_PC], reg);
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return 0;
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}
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}
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#define SET_INT(flag, val) { \
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if (val) { \
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CPU_SET_INT(flag); \
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} else { \
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CPU_CLR_INT(flag); \
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} \
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}
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void csr_write(uint32 pa, uint32 val, size_t size)
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{
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uint32 reg = pa - CSRBASE;
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switch (reg) {
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case 0x00:
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CSRBIT(CSRCLK, val);
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SET_INT(INT_CLOCK, val);
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break;
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case 0x04:
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CSRBIT(CSRPWRDN, val);
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SET_INT(INT_PWRDWN, val);
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break;
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case 0x08:
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CSRBIT(CSROPINT15, val);
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SET_INT(INT_BUS_OP, val);
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break;
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case 0x0c:
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CSRBIT(CSRUART, val);
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SET_INT(INT_UART, val);
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break;
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case 0x10:
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CSRBIT(CSRDMA, val);
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SET_INT(INT_UART_DMA, val);
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break;
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case 0x14:
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CSRBIT(CSRPIR9, val);
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SET_INT(INT_PIR9, val);
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break;
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case 0x18:
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CSRBIT(CSRPIR8, val);
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SET_INT(INT_PIR8, val);
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break;
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case 0x1c:
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CSRBIT(CSRITIM, val);
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sim_debug(WRITE_MSG, &csr_dev,
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"[%08x] CSR WRITE. Inhibit Interval Timer = %d\n",
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R[NUM_PC], val);
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if (csr_data & CSRITIM) {
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timer_disable(TIMER_INTERVAL);
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} else {
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timer_enable(TIMER_INTERVAL);
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}
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break;
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case 0x20:
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CSRBIT(CSRISTIM, val);
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sim_debug(WRITE_MSG, &csr_dev,
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"[%08x] CSR WRITE. Inhibit Sanity Timer = %d\n",
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R[NUM_PC], val);
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if (csr_data & CSRISTIM) {
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timer_disable(TIMER_SANITY);
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} else {
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timer_enable(TIMER_SANITY);
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}
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break;
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case 0x24:
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CSRBIT(CSRITIMO, val);
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sim_debug(WRITE_MSG, &csr_dev,
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"[%08x] CSR WRITE. Inhibit Bus Timer = %d\n",
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R[NUM_PC], val);
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if (csr_data & CSRITIMO) {
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timer_disable(TIMER_BUS);
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} else {
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timer_enable(TIMER_BUS);
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}
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break;
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case 0x28:
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CSRBIT(CSRICPUFLT, val);
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break;
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case 0x2c:
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CSRBIT(CSRISBERR, val);
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break;
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case 0x30:
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CSRBIT(CSRIIOBUS, val);
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break;
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case 0x34:
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CSRBIT(CSRIBUB, val);
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break;
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case 0x38:
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CSRBIT(CSRFECC, val);
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break;
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case 0x3c:
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CSRBIT(CSRTHERM, val);
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cpu_nmi = val ? TRUE : FALSE; /* Immediate NMI */
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break;
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case 0x40:
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CSRBIT(CSRLED, val);
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break;
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case 0x44:
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CSRBIT(CSRPWRSPDN, val);
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break;
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case 0x48:
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CSRBIT(CSRFLPFST, val);
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break;
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case 0x4c: /* Floppy Side 1: Set when Cleared */
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if_state.side = (val & 1) ? 0 : 1;
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CSRBIT(CSRFLPS1, val & 1);
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break;
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case 0x50:
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CSRBIT(CSRFLPMO, val);
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break;
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case 0x54:
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CSRBIT(CSRFLPDEN, val);
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break;
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case 0x58:
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CSRBIT(CSRFLPSZ, val);
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break;
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case 0x5c:
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CSRBIT(CSRSBERR, val);
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if (val) {
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if (!(csr_data & CSRISBERR)) {
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SET_INT(INT_SBERR, TRUE);
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}
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} else {
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SET_INT(INT_SBERR, FALSE);
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}
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break;
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case 0x60:
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CSRBIT(CSRMBERR, val);
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SET_INT(INT_MBERR, val);
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break;
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case 0x64:
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CSRBIT(CSRUBUBF, val);
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SET_INT(INT_BUS_RXF, val);
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break;
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case 0x68:
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CSRBIT(CSRTIMO, val);
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if (val) {
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if (!(csr_data & CSRITIMO)) {
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SET_INT(INT_BUS_TMO, TRUE);
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}
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} else {
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SET_INT(INT_BUS_TMO, FALSE);
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}
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break;
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case 0x6c:
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CSRBIT(CSRFRF, val);
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break;
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case 0x70:
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CSRBIT(CSRALGN, val);
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break;
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case 0x74:
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CSRBIT(CSRSTIMO, val);
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cpu_nmi = val ? TRUE : FALSE; /* Immediate NMI */
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break;
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case 0x78:
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CSRBIT(CSRABRT, val);
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cpu_nmi = val ? TRUE : FALSE; /* Immediate NMI */
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break;
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case 0x7c:
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/* System reset request */
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cpu_boot(0, &cpu_dev);
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break;
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default:
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/* Do nothing */
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break;
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}
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}
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