9d849283a4
- This change introduces a full refactor of the interrupt subsystem
for the system board (SBD) and the I/O bus (CIO). Interrupt decode
should now be significantly faster, and not require an expensive
calculation on every step.
- The TIMER device has been split into Rev 2 and Rev 3
implementations.
- The optional 3B2/400 Debug Monitor ROMs can now be booted by passing
the "DEMON" argument to the 3B2/400 simulator BOOT command. Any
of the following will cause the Debug Monitor ROM to be booted
instead of the standard 3B2/400 ROM:
sim> BOOT DEMON
sim> BOOT CPU DEMON
sim> BOOT DEMON CPU
149 lines
6.5 KiB
C
149 lines
6.5 KiB
C
/* 3b2_rev3_defs.h: AT&T 3B2 Rev 3 (Model 600G) Simulator Definitions
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Copyright (c) 2021, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#ifndef _3B2_REV3_DEFS_H_
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#define _3B2_REV3_DEFS_H_
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#define NUM_REGISTERS 32
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#define DEFMEMSIZE MSIZ_16M
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#define MAXMEMSIZE MSIZ_64M
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#define HWORD_OP_COUNT 12
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#define CPU_VERSION 0x1F /* Version encoded in WE32200 */
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/* CSR Flags */
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#define CSRCLK 1u /* UNIX Interval Timer Timeout */
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#define CSRPWRDN (1u << 1) /* Power Down Request */
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#define CSROPINT15 (1u << 2) /* Oper. Interrupt Level 15 */
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#define CSRUART (1u << 3) /* DUART Interrupt */
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#define CSRDMA (1u << 4) /* DUART DMA Complete Interrupt */
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#define CSRPIR9 (1u << 5) /* Programmed Interrupt 9 */
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#define CSRPIR8 (1u << 6) /* Programmed Interrupt 8 */
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#define CSRITIM (1u << 7) /* Inhibit UNIX Interval Timer */
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#define CSRISTIM (1u << 8) /* Inhibit System Sanity Timer */
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#define CSRITIMO (1u << 9) /* Inhibit Bus Timer */
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#define CSRICPUFLT (1u << 10) /* Inhibit Faults to CPU */
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#define CSRISBERR (1u << 11) /* Inhibit Single Bit Error Rpt */
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#define CSRIIOBUS (1u << 12) /* Inhibit Integral 3B2 I/O Bus */
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#define CSRIBUB (1u << 13) /* Inhibit 4 BUB Slots */
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#define CSRFECC (1u << 14) /* Force ECC Syndrome */
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#define CSRTHERM (1u << 15) /* Thermal Shutdown Request */
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#define CSRLED (1u << 16) /* Failure LED */
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#define CSRPWRSPDN (1u << 17) /* Power Down -- Power Supply */
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#define CSRFLPFST (1u << 18) /* Floppy Speed Fast */
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#define CSRFLPS1 (1u << 19) /* Floppy Side 1 */
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#define CSRFLPMO (1u << 20) /* Floppy Motor On */
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#define CSRFLPDEN (1u << 21) /* Floppy Density */
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#define CSRFLPSZ (1u << 22) /* Floppy Size */
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#define CSRSBERR (1u << 23) /* Single Bit Error */
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#define CSRMBERR (1u << 24) /* Multiple Bit Error */
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#define CSRUBUBF (1u << 25) /* Ubus/BUB Received Fail */
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#define CSRTIMO (1u << 26) /* Bus Timer Timeout */
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#define CSRFRF (1u << 27) /* Fault Registers Frozen */
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#define CSRALGN (1u << 28) /* Data Alignment Error */
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#define CSRSTIMO (1u << 29) /* Sanity Timer Timeout */
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#define CSRABRT (1u << 30) /* Abort Switch Activated */
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#define CSRRRST (1u << 31) /* System Reset Request */
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/* Interrupt Sources */
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#define INT_CLOCK 0x0001 /* UNIX Interval Timer Timeout - IPL 15 */
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#define INT_PWRDWN 0x0002 /* Power Down Request - IPL 15 */
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#define INT_BUS_OP 0x0004 /* UBUS or BUB Operational Interrupt - IPL 15 */
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#define INT_SBERR 0x0008 /* Single Bit Memory Error - IPL 15 */
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#define INT_MBERR 0x0010 /* Multiple Bit Memory Error - IPL 15 */
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#define INT_BUS_RXF 0x0020 /* UBUS, BUB, EIO Bus Received Fail - IPL 15 */
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#define INT_BUS_TMO 0x0040 /* UBUS Timer Timeout - IPL 15 */
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#define INT_UART_DMA 0x0080 /* UART DMA Complete - IPL 13 */
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#define INT_UART 0x0100 /* UART Interrupt - IPL 13 */
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#define INT_FLOPPY_DMA 0x0200 /* Floppy DMA Complete - IPL 11 */
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#define INT_FLOPPY 0x0400 /* Floppy Interrupt - IPL 11 */
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#define INT_PIR9 0x0800 /* PIR-9 (from CSER) - IPL 9 */
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#define INT_PIR8 0x1000 /* PIR-8 (from CSER) - IPL 8 */
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#define INT_MAP_LEN 0x2000
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/* Memory */
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#define MEMID_4M 6
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#define MEMID_16M 7
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#define MADDR_SLOT_0 0x4d000
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#define MADDR_SLOT_1 0x4d004
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#define MADDR_SLOT_2 0x4d008
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#define MADDR_SLOT_3 0x4d00c
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#define IFCSRBASE 0x40000
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#define IFCSRSIZE 0x100
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#define TIMERBASE 0x41000
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#define TIMERSIZE 0x20
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#define NVRBASE 0x42000
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#define NVRSIZE 0x2000
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#define CSRBASE 0x44000
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#define CSRSIZE 0x100
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#define DMAIFBASE 0x45000
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#define DMAIFSIZE 0x5
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#define DMAIUABASE 0x46000
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#define DMAIUASIZE 0x5
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#define DMAIUBBASE 0x47000
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#define DMAIUBSIZE 0x5
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#define DMACBASE 0x48000
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#define DMACSIZE 0x11
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#define IFBASE 0x4a000
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#define IFSIZE 0x10
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#define TODBASE 0x4e000
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#define TODSIZE 0x40
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#define MMUBASE 0x4f000
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#define MMUSIZE 0x1000
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#define FLTLBASE 0x4c000
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#define FLTLSIZE 0x10
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#define FLTHBASE 0x4d000
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#define FLTHSIZE 0x10
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#define VCACHE_BOTTOM 0x1c00000
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#define VCACHE_TOP 0x2000000
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#define BUB_BOTTOM 0x6000000
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#define BUB_TOP 0x1a000000
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#define IF_STATUS_REG 0
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#define IF_CMD_REG 0
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#define IF_TRACK_REG 1
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#define IF_SECTOR_REG 2
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#define IF_DATA_REG 3
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#define DMA_IF_CHAN 1
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#define DMA_IUA_CHAN 2
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#define DMA_IUB_CHAN 3
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#define DMA_IF 0x45
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#define DMA_IUA 0x46
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#define DMA_IUB 0x47
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#define DMA_C 0x48
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#endif
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