301 lines
13 KiB
C
301 lines
13 KiB
C
/* sel32_iop.c: SEL-32 Model 8000/8001/8002 IOP processor controller
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Copyright (c) 2018-2022, James C. Bevier
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JAMES C. BEVIER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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This channel is the interrupt fielder for all of the IOP sub channels. It's
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channel address is 7E00. This code handles the INCH command for the IOP
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devices and controls the status FIFO for the iop devices on interrupts and
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TIO instructions..
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Possible devices:
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The f8iop communication controller (TY7EA0), (TY7EB0), (TY7EC0)
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The ctiop console communications controller (CT7EFC & CT7EFD)
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The lpiop line printer controller (LP7EF8), (LP7EF9)
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*/
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#include "sel32_defs.h"
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#if NUM_DEVS_IOP > 0
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#define UNIT_IOP UNIT_IDLE | UNIT_DISABLE
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/* forward definitions */
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t_stat iop_preio(UNIT *uptr, uint16 chan);
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t_stat iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd);
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void iop_ini(UNIT *uptr, t_bool f);
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t_stat iop_rschnlio(UNIT *uptr);
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t_stat iop_srv(UNIT *uptr);
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t_stat iop_reset(DEVICE *dptr);
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t_stat iop_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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const char *iop_desc(DEVICE *dptr);
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/* Held in u3 is the device command and status */
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#define IOP_INCH 0x00 /* Initialize channel command */
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#define IOP_INCH2 0xf0 /* Initialize channel command after start */
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#define IOP_NOP 0x03 /* NOP command */
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#define IOP_MSK 0xff /* Command mask */
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/* Status held in u3 */
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/* controller/unit address in upper 16 bits */
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#define CON_INPUT 0x100 /* Input ready for unit */
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#define CON_CR 0x200 /* Output at beginning of line */
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#define CON_REQ 0x400 /* Request key pressed */
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#define CON_EKO 0x800 /* Echo input character */
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#define CON_OUTPUT 0x1000 /* Output ready for unit */
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#define CON_READ 0x2000 /* Read mode selected */
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/* not used u4 */
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/* in u5 packs sense byte 0,1 and 3 */
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/* Sense byte 0 */
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#define SNS_CMDREJ 0x80000000 /* Command reject */
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#define SNS_INTVENT 0x40000000 /* Unit intervention required */
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/* sense byte 3 */
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#define SNS_RDY 0x80 /* device ready */
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#define SNS_ONLN 0x40 /* device online */
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/* std devices. data structures
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iop_dev Console device descriptor
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iop_unit Console unit descriptor
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iop_reg Console register list
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iop_mod Console modifiers list
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*/
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struct _iop_data
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{
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uint8 ibuff[145]; /* Input line buffer */
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uint8 incnt; /* char count */
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}
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iop_data[NUM_UNITS_IOP];
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/* channel program information */
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CHANP iop_chp[NUM_UNITS_IOP] = {0};
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MTAB iop_mod[] = {
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{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "DEV", "DEV",
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&set_dev_addr, &show_dev_addr, NULL, "Controller Channel address"},
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{0}
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};
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UNIT iop_unit[] = {
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{UDATA(&iop_srv, UNIT_IOP, 0), 0, UNIT_ADDR(0x7E00)}, /* Channel controller */
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};
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DIB iop_dib = {
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iop_preio, /* t_stat (*pre_io)(UNIT *uptr, uint16 chan)*/ /* Pre Start I/O */
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iop_startcmd, /* t_stat (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd)*/ /* Start command SIO */
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NULL, /* t_stat (*halt_io)(UNIT *uptr) */ /* Halt I/O HIO */
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NULL, /* t_stat (*stop_io)(UNIT *uptr) */ /* Stop I/O HIO */
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NULL, /* t_stat (*test_io)(UNIT *uptr) */ /* Test I/O TIO */
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NULL, /* t_stat (*rsctl_io)(UNIT *uptr) */ /* Reset Controller */
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iop_rschnlio, /* t_stat (*rschnl_io)(UNIT *uptr) */ /* Reset Channel */
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NULL, /* t_stat (*iocl_io)(CHANP *chp, int32 tic_ok)) */ /* Process IOCL */
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iop_ini, /* void (*dev_ini)(UNIT *, t_bool) */ /* init function */
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iop_unit, /* UNIT* units */ /* Pointer to units structure */
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iop_chp, /* CHANP* chan_prg */ /* Pointer to chan_prg structure */
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NULL, /* IOCLQ *ioclq_ptr */ /* IOCL entries, 1 per UNIT */
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NUM_UNITS_IOP, /* uint8 numunits */ /* number of units defined */
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0xff, /* uint8 mask */ /* 16 devices - device mask */
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0x7e00, /* uint16 chan_addr */ /* parent channel address */
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0, /* uint32 chan_fifo_in */ /* fifo input index */
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0, /* uint32 chan_fifo_out */ /* fifo output index */
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{0} /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
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};
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DEVICE iop_dev = {
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"IOP", iop_unit, NULL, iop_mod,
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NUM_UNITS_IOP, 8, 15, 1, 8, 8,
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NULL, NULL, &iop_reset, /* examine, deposit, reset */
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NULL, NULL, NULL, /* boot, attach, detach */
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/* dib ptr, dev flags, debug flags, debug */
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&iop_dib, DEV_CHAN|DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
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};
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/* IOP controller routines */
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/* initialize the console chan/unit */
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void iop_ini(UNIT *uptr, t_bool f)
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{
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int unit = (uptr - iop_unit); /* unit 0 */
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DEVICE *dptr = &iop_dev; /* one and only dummy device */
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iop_data[unit].incnt = 0; /* no input data */
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uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
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sim_cancel(uptr); /* stop any timers */
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sim_debug(DEBUG_CMD, &iop_dev,
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"IOP init device %s controller/device %04x\n",
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dptr->name, GET_UADDR(uptr->u3));
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}
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/* handle rschnlio cmds for iop */
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t_stat iop_rschnlio(UNIT *uptr) {
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DEVICE *dptr = get_dev(uptr);
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uint16 chsa = GET_UADDR(uptr->u3);
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int cmd = uptr->u3 & IOP_MSK;
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sim_debug(DEBUG_EXP, dptr,
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"iop_rschnl chsa %04x cmd = %02x\n", chsa, cmd);
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iop_ini(uptr, 0); /* reset the unit */
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return SCPE_OK;
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}
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/* start an iop operation */
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t_stat iop_preio(UNIT *uptr, uint16 chan) {
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DEVICE *dptr = get_dev(uptr);
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int unit = (uptr - dptr->units);
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uint16 chsa = GET_UADDR(uptr->u3);
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sim_debug(DEBUG_CMD, dptr, "iop_preio CMD %08x unit %02x chsa %04x\n",
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uptr->u3, unit, chsa);
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if ((uptr->u3 & IOP_MSK) != 0) { /* is unit busy */
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sim_debug(DEBUG_CMD, dptr,
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"iop_preio unit %02x chsa %04x BUSY\n", unit, chsa);
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return SNS_BSY; /* yes, return busy */
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}
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sim_debug(DEBUG_CMD, dptr, "iop_preio unit %02x chsa %04x OK\n", unit, chsa);
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return SCPE_OK; /* good to go */
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}
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/* start an I/O operation */
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t_stat iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
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{
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sim_debug(DEBUG_CMD, &iop_dev,
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"IOP startcmd %02x controller/device %04x\n",
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cmd, GET_UADDR(uptr->u3));
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if ((uptr->u3 & IOP_MSK) != 0) /* is unit busy */
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return SNS_BSY; /* yes, return busy */
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/* process the commands */
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switch (cmd & 0xFF) {
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/* UTX uses the INCH cmd to detect the IOP or MFP */
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/* IOP has INCH cmd of 0, while MFP uses 0x80 */
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case IOP_INCH: /* INCH command */
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uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
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uptr->u3 &= LMASK; /* leave only chsa */
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sim_debug(DEBUG_CMD, &iop_dev,
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"iop_startcmd %04x: Cmd INCH iptr %06x INCHa %06x\n",
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chan, iop_chp[0].ccw_addr, /* set inch buffer addr */
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iop_chp[0].chan_inch_addr); /* set inch buffer addr */
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iop_chp[0].chan_inch_addr = iop_chp[0].ccw_addr; /* set inch buffer addr */
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iop_chp[0].base_inch_addr = iop_chp[0].ccw_addr; /* set inch buffer addr */
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iop_chp[0].max_inch_addr = iop_chp[0].ccw_addr + (128 * 8); /* set last inch buffer addr */
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uptr->u3 |= IOP_INCH2; /* save INCH command as 0xf0 */
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sim_activate(uptr, 40); /* go on */
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return 0; /* no status change */
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break;
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case IOP_NOP: /* NOP command */
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sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %04x: Cmd NOP\n", chan);
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uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
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uptr->u3 &= LMASK; /* leave only chsa */
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uptr->u3 |= (cmd & IOP_MSK); /* save NOP command */
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sim_activate(uptr, 40); /* TRY 07-13-19 */
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return 0; /* no status change */
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break;
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default: /* invalid command */
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uptr->u5 |= SNS_CMDREJ; /* command rejected */
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sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %04x: Cmd Invalid %02x status %02x\n",
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chan, cmd, uptr->u5);
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uptr->u3 &= LMASK; /* leave only chsa */
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uptr->u3 |= (cmd & IOP_MSK); /* save command */
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sim_activate(uptr, 40); /* force interrupt */
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return 0; /* no status change */
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break;
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}
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return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* not reachable for now */
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}
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/* Handle transfers for other sub-channels on IOP */
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t_stat iop_srv(UNIT *uptr)
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{
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uint16 chsa = GET_UADDR(uptr->u3);
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int cmd = uptr->u3 & IOP_MSK;
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CHANP *chp = &iop_chp[0]; /* find the chanp pointer */
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uint32 mema = chp->ccw_addr; /* get inch or buffer addr */
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uint32 tstart;
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/* test for NOP or INCH cmds */
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if ((cmd != IOP_NOP) && (cmd != IOP_INCH2)) { /* NOP or INCH */
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uptr->u3 &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &iop_dev,
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"iop_srv Unknown cmd %02x chan %02x: chnend|devend|unitexp\n", cmd, chsa);
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP); /* done */
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return SCPE_OK;
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} else
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if (cmd == IOP_NOP) { /* NOP do nothing */
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uptr->u3 &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &iop_dev, "iop_srv INCH/NOP chan %02x: chnend|devend\n", chsa);
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
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return SCPE_OK;
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} else
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/* test for INCH cmd */
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if (cmd == IOP_INCH2) { /* INCH */
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sim_debug(DEBUG_CMD, &iop_dev,
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"iop_srv starting INCH %06x cmd, chsa %04x MemBuf %06x cnt %04x\n",
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mema, chsa, chp->ccw_addr, chp->ccw_count);
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/* now call set_inch() function to write and test inch buffer addresses */
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/* the chp->ccw_addr location contains the inch address */
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/* 1-256 wd buffer is provided for 128 status dbl words */
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tstart = set_inch(uptr, mema, 128); /* new address of 128 entries */
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if ((tstart == SCPE_MEM) || (tstart == SCPE_ARG)) { /* any error */
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/* we have error, bail out */
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uptr->u5 |= SNS_CMDREJ;
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uptr->u3 &= LMASK; /* nothing left, command complete */
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
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return SCPE_OK;
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}
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uptr->u3 &= LMASK; /* clear the cmd */
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */
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}
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return SCPE_OK;
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}
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t_stat iop_reset(DEVICE *dptr)
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{
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/* add reset code here */
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return SCPE_OK;
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}
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/* sho help iop */
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t_stat iop_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, CONST char *cptr)
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{
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fprintf(st, "SEL-32 IOP Model 8000 Channel Controller at 0x7E00\r\n");
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fprintf(st, "The IOP fields all interrupts and status posting\r\n");
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fprintf(st, "for each of the controllers on the system.\r\n");
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fprintf(st, "Nothing can be configured for this Channel.\r\n");
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return SCPE_OK;
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}
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const char *iop_desc(DEVICE *dptr)
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{
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return("SEL-32 IOP Model 8000 Channel Controller @ 0x7E00");
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}
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#endif
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