183 lines
9.6 KiB
C
183 lines
9.6 KiB
C
/* vax_bi.h: VAXBI Standard Definitions
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Copyright (c) 2019, Matt Burke
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of the author shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author.
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This file covers the VAXBI registers that are contained in the BIIC chip
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on each VAXBI node.
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*/
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#ifndef _VAXBI_DEFS_H_
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#define _VAXBI_DEFS_H_ 1
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/* Register Offsets */
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#define BI_DTYPE 0 /* device type */
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#define BI_CSR 1 /* control/status */
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#define BI_BER 2 /* bus error */
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#define BI_EICR 3 /* error interrupt control */
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#define BI_IDEST 4 /* interrupt destination */
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#define BI_IMSK 5 /* IPINTR mask */
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#define BI_FIDEST 6 /* force IPINTR destination */
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#define BI_ISRC 7 /* IPINTR source */
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#define BI_SA 8 /* start address */
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#define BI_EA 9 /* end address */
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#define BI_BCIC 10 /* BCI control */
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#define BI_WSTS 11 /* write status */
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#define BI_FICMD 12 /* force IPINTR command */
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#define BI_UIIC 16 /* user interface interrupt control */
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#define BI_GPR0 60 /* general purpose register 0 */
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#define BI_GPR1 61 /* general purpose register 1 */
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#define BI_GPR2 62 /* general purpose register 2 */
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#define BI_GPR3 63 /* general purpose register 3 */
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#define BI_SOSR 64 /* slave only status register */
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#define BI_RXCD 128 /* receive console data register */
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/* VAXBI device types */
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#define DTYPE_MS820 0x0001 /* MS820 MOS Memory */
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#define DTYPE_DWBUA 0x0102 /* DWBUA Unibus Adapter */
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#define DTYPE_KA820 0x0105 /* KA820 CPU */
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#define DTYPE_CIBCA 0x0105 /* CI Adapter */
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#define DTYPE_KDB50 0x010E /* Disk Adapter */
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#define DTYPE_DEBNA 0x410F /* Ethernet Adapter */
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/* VAXBI control/status register */
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#define BICSR_V_IR 24 /* interface revision */
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#define BICSR_M_IR 0xFF
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#define BICSR_V_IF 16 /* interface type */
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#define BICSR_M_IF 0xFF
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#define BICSR_HES 0x00004000 /* hard error summary */
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#define BICSR_SES 0x00004000 /* soft error summary */
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#define BICSR_INI 0x00002000 /* initialise */
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#define BICSR_BRK 0x00001000 /* broke - NI */
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#define BICSR_STS 0x00000800 /* self test status */
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#define BICSR_RST 0x00000400 /* node reset */
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#define BICSR_UWP 0x00000100 /* unlock write pending */
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#define BICSR_HIE 0x00000080 /* hard error interrupt en */
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#define BICSR_SIE 0x00000040 /* soft error interrupt en */
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#define BICSR_AC 0x00000030 /* arbitration control */
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#define BICSR_NODE 0x0000000F /* BI node ID */
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#define BICSR_RW (BICSR_HIE | BICSR_SIE | BICSR_AC)
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#define BICSR_RD 0xFFFFFDFF
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/* VAXBI bus error register */
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#define BIBER_NMR 0x40000000 /* no ACK to multi resp command */
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#define BIBER_MTCE 0x20000000 /* master transmit check error */
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#define BIBER_CTE 0x10000000 /* control transmit error */
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#define BIBER_MPE 0x08000000 /* master parity error */
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#define BIBER_ISE 0x04000000 /* interlock sequence error */
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#define BIBER_TDF 0x02000000 /* transmitter during fault */
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#define BIBER_IVE 0x01000000 /* ident vector error */
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#define BIBER_CPE 0x00800000 /* command parity error */
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#define BIBER_SPE 0x00400000 /* slave parity error */
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#define BIBER_RDS 0x00200000 /* read data substitute */
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#define BIBER_RTO 0x00100000 /* retry timeout */
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#define BIBER_STO 0x00080000 /* stall timeout */
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#define BIBER_BTO 0x00040000 /* bus timeout */
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#define BIBER_NEX 0x00020000 /* nonexistant address */
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#define BIBER_ICE 0x00010000 /* illegal confirmation error */
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#define BIBER_UPE 0x00000008 /* user parity enable */
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#define BIBER_IPE 0x00000004 /* ID parity error */
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#define BIBER_CRD 0x00000002 /* corrected read data */
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#define BIBER_NPE 0x00000001 /* null bus parity error */
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#define BIBER_RD 0xFFFF000F
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#define BIBER_W1C 0xFFFF0007
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/* VAXBI error interrupt control register */
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#define BIECR_ABO 0x01000000 /* interrupt abort */
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#define BIECR_COM 0x00800000 /* interrupt complete */
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#define BIECR_SNT 0x00200000 /* interrupt sent */
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#define BIECR_FRC 0x00100000 /* force */
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#define BIECR_LVL 0x000F0000 /* interrupt level */
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#define BIECR_V_LVL 16
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#define BIECR_M_LVL 0xF
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#define BIECR_VEC 0x00003FFC /* vector */
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#define BIECR_RW 0x001F3FFC
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#define BIECR_W1C 0x01A00000
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#define BIECR_RD (BIECR_RW | BIECR_W1C)
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/* VAXBI interrupt destination register */
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#define BIID_RW 0x0000FFFF
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#define BIID_RD BIID_RW
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/* VAXBI BCI control and status register */
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#define BIBCI_BE 0x00020000 /* burst enable */
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#define BIBCI_IPI 0x00010000 /* IPINTR/STOP */
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#define BIBCI_MCS 0x00008000 /* multicast enable */
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#define BIBCI_BDC 0x00004000 /* BDCST enable */
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#define BIBCI_STP 0x00002000 /* STOP enable */
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#define BIBCI_RSE 0x00001000 /* RESERVED enable */
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#define BIBCI_IDE 0x00000800 /* IDENT enable */
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#define BIBCI_IVE 0x00000400 /* INVAL enable */
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#define BIBCI_WRI 0x00000200 /* WRITE invalidate enable */
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#define BIBCI_UCE 0x00000100 /* user CSR space enable */
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#define BIBCI_BIE 0x00000080 /* BIIC CSR space enable */
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#define BIBCI_INE 0x00000040 /* INTR enable */
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#define BIBCI_IPE 0x00000020 /* IPINTR enable */
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#define BIBCI_PEN 0x00000010 /* pipeline next enable */
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#define BIBCI_RTO 0x00000008 /* RTO EV enable */
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#define BIBCI_RW 0x0003FFF8
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#define BIBCI_RD (BIBCI_RW)
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/* VAXBI user interface interrupt control register */
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#define BIICR_ABO 0xF0000000 /* interrupt abort */
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#define BIICR_ITC 0x0F000000 /* interrupt complete */
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#define BIICR_SNT 0x00F00000 /* interrupt sent */
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#define BIICR_FRC 0x000F0000 /* force */
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#define BIICR_EXV 0x00008000 /* external vector */
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#define BIICR_VEC 0x00003FFC /* vector */
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#define BIICR_RW 0x000FBFFC
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#define BIICR_W1C 0xFFF00000
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#define BIICR_RD (BIICR_RW | BIICR_W1C)
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typedef struct {
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uint32 dtype;
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uint32 csr;
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uint32 ber;
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uint32 eicr;
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uint32 idest;
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uint32 imsk;
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uint32 fidest;
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uint32 isrc;
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uint32 sa;
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uint32 ea;
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uint32 bcic;
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uint32 wsts;
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uint32 ficmd;
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uint32 uiic;
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uint32 gpr0;
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uint32 gpr1;
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uint32 gpr2;
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uint32 gpr3;
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uint32 sosr;
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uint32 rxcd;
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} BIIC;
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#endif
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