428 lines
16 KiB
C
428 lines
16 KiB
C
/* alpha_ev5_defs.h: Alpha EV5 chip definitions file
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Copyright (c) 2003-2005, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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Respectfully dedicated to the great people of the Alpha chip, systems, and
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software development projects; and to the memory of Peter Conklin, of the
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Alpha Program Office.
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*/
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#ifndef ALPHA_EV5_DEFS_H_
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#define ALPHA_EV5_DEFS_H_ 0
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/* Address limits */
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#define VA_SIZE 43 /* VA size */
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#define NTVA_WIDTH 32 /* VA width for NT */
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#define VA_MASK 0x000007FFFFFFFFFF
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#define EV5_PA_SIZE 40 /* PA size */
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#define EV5_PA_MASK 0x000000FFFFFFFFFF
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/* Virtual address */
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#define VA_N_OFF 13 /* offset size */
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#define VA_PAGSIZE (1u << VA_N_OFF) /* page size */
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#define VA_M_OFF ((1u << VA_N_OFF) - 1) /* offset mask */
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#define VA_N_LVL 10 /* width per level */
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#define VA_M_LVL ((1u << VA_N_LVL) - 1) /* level mask */
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#define VA_V_VPN VA_N_OFF /* vpn start */
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#define VA_N_VPN (VA_N_LVL * 3) /* vpn size */
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#define VA_M_VPN ((1u << VA_N_VPN) - 1) /* vpn mask */
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#define VA_WIDTH (VA_N_VPN + VA_N_OFF) /* total VA size */
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#define VA_V_SEXT (VA_WIDTH - 1) /* sext start */
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#define VA_M_SEXT ((1u << (64 - VA_V_SEXT)) - 1) /* sext mask */
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#define VA_GETOFF(x) (((uint32) (x)) & VA_M_OFF)
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#define VA_GETVPN(x) (((uint32) ((x) >> VA_V_VPN)) & VA_M_VPN)
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#define VA_GETSEXT(x) (((uint32) ((x) >> VA_V_SEXT)) & VA_M_SEXT)
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#define PHYS_ADDR(p,v) (((((t_uint64) (p)) < VA_N_OFF) | VA_GETOFF (v)) & EV5_PA_MASK)
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/* 43b and 32b superpages - present in all implementations */
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#define SPEN_43 0x2
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#define SPEN_32 0x1
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#define SP43_MASK (EV5_PA_MASK)
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#define SP32_MASK 0x000000003FFFFFFF
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#define VPN_GETSP43(x) ((uint32) (((x) >> (VA_WIDTH - VA_N_OFF - 2)) & 3))
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#define VPN_GETSP32(x) ((uint32) (((x) >> (NTVA_WIDTH - VA_N_OFF - 2)) & 0x1FFF))
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/* TLBs */
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#define INV_TAG M32
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#define ITLB_SIZE 48
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#define DTLB_SIZE 64
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#define ITLB_WIDTH 6
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#define DTLB_WIDTH 6
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#define TLB_CI 0x1 /* clear I */
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#define TLB_CD 0x2 /* clear D */
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#define TLB_CA 0x4 /* clear all */
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typedef struct {
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uint32 tag; /* tag */
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uint8 asn; /* addr space # */
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uint8 idx; /* entry # */
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uint16 gh_mask; /* gh mask */
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uint32 pfn; /* pfn */
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uint32 pte; /* swre/pte */
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} TLBENT;
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/* Register shadow */
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#define PALSHAD_SIZE 8
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#define PAL_USE_SHADOW \
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ev5_palsave[0] = R[8]; ev5_palsave[1] = R[9]; \
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ev5_palsave[2] = R[10]; ev5_palsave[3] = R[11]; \
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ev5_palsave[4] = R[12]; ev5_palsave[5] = R[13]; \
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ev5_palsave[6] = R[14]; ev5_palsave[7] = R[25]; \
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R[8] = ev5_palshad[0]; R[9] = ev5_palshad[1]; \
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R[10] = ev5_palshad[2]; R[11] = ev5_palshad[3]; \
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R[12] = ev5_palshad[4]; R[13] = ev5_palshad[5]; \
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R[14] = ev5_palshad[6]; R[25] = ev5_palshad[7]
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#define PAL_USE_MAIN \
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ev5_palshad[0] = R[8]; ev5_palshad[1] = R[9]; \
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ev5_palshad[2] = R[10]; ev5_palshad[3] = R[11]; \
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ev5_palshad[4] = R[12]; ev5_palshad[5] = R[13]; \
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ev5_palshad[6] = R[14]; ev5_palshad[7] = R[25]; \
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R[8] = ev5_palsave[0]; R[9] = ev5_palsave[1]; \
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R[10] = ev5_palsave[2]; R[11] = ev5_palsave[3]; \
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R[12] = ev5_palsave[4]; R[13] = ev5_palsave[5]; \
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R[14] = ev5_palsave[6]; R[25] = ev5_palsave[7]
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/* PAL instructions */
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#define HW_MFPR 0x19
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#define HW_LD 0x1B
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#define HW_MTPR 0x1D
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#define HW_REI 0x1E
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#define HW_ST 0x1F
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#define HW_LD_V 0x8000
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#define HW_LD_ALT 0x4000
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#define HW_LD_WCH 0x2000
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#define HW_LD_Q 0x1000
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#define HW_LD_PTE 0x0800
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#define HW_LD_LCK 0x0400
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#define HW_LD_DSP 0x03FF
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#define SIGN_HW_LD_DSP 0x0200
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#define HW_LD_GETDSP(x) ((x) & HW_LD_DSP)
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#define SEXT_HW_LD_DSP(x) (((x) & SIGN_HW_LD_DSP)? \
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((x) | ~((t_uint64) HW_LD_DSP)): ((x) & HW_LD_DSP))
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#define HW_REI_S 0x4000
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/* PAL entry offsets */
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#define PALO_RESET 0x0000
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#define PALO_IACV 0x0080
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#define PALO_INTR 0x0100
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#define PALO_ITBM 0x0180
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#define PALO_DTBM 0x0200
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#define PALO_DTBM_D 0x0280
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#define PALO_ALGN 0x0300
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#define PALO_DFLT 0x0380
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#define PALO_MCHK 0x0400
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#define PALO_RSVI 0x0480
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#define PALO_TRAP 0x0500
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#define PALO_FDIS 0x0580
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#define PALO_CALLPR 0x2000
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#define PALO_CALLUNPR 0x3000
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/* Special (above 1F) and normal interrupt levels */
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#define IPL_HALT 0x40
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#define IPL_SLI 0x20
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#define IPL_1F 0x1F /* highest level */
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#define IPL_CRD 0x1F /* corrected read data */
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#define IPL_PWRFL 0x1E /* power fail */
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#define IPL_AST 0x02 /* AST interrupt level */
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/* Internal registers */
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#define PALTEMP_SIZE 24
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enum ev5_internal_reg {
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ISR = 0x100, ITB_TAG, ITB_PTE, ITB_ASN,
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ITB_PTE_TEMP, ITB_IA, ITB_IAP, ITB_IS,
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SIRR, ASTRR, ASTEN, EXC_ADDR,
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EXC_SUMM, EXC_MASK, PAL_BASE, ICM,
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IPLR, INTID, IFAULT_VA_FORM, IVPTBR,
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HWINT_CLR = 0x115, SL_XMIT, SL_RCV,
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ICSR, IC_FLUSH_CTL, ICPERR_STAT, PMCTR = 0x11C,
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PALTEMP = 0x140,
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DTB_ASN = 0x200, DTB_CM, DTB_TAG, DTB_PTE,
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DTB_PTE_TEMP, MM_STAT, VA, VA_FORM,
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MVPTBR, DTB_IAP, DTB_IA, DTB_IS,
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ALTMODE, CC, CC_CTL, MCSR,
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DC_FLUSH, DC_PERR_STAT = 0x212, DC_TEST_CTL,
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DC_TEST_TAG, DC_TEST_TAG_TEMP, DC_MODE, MAF_MODE
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};
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/* Ibox registers */
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/* ISR - instruction summary register - read only */
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#define ISR_V_AST 0
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#define ISR_V_SIRR 4
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#define ISR_V_ATR 19
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#define ISR_V_IRQ0 20
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#define ISR_V_IRQ1 21
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#define ISR_V_IRQ2 22
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#define ISR_V_IRQ3 23
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#define ISR_V_PFL 30
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#define ISR_V_MCHK 31
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#define ISR_V_CRD 32
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#define ISR_V_SLI 33
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#define ISR_V_HALT 34
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#define ISR_ATR (((t_uint64) 1u) << ISR_V_ATR)
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#define ISR_IRQ0 (((t_uint64) 1u) << ISR_V_IRQ0)
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#define ISR_IRQ1 (((t_uint64) 1u) << ISR_V_IRQ1)
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#define ISR_IRQ2 (((t_uint64) 1u) << ISR_V_IRQ2)
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#define ISR_IRQ3 (((t_uint64) 1u) << ISR_V_IRQ3)
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#define ISR_HALT (((t_uint64) 1u) << ISR_V_HALT)
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/* ITB_TAG - ITLB tag - write only - stores VPN (tag) of faulting address */
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/* ITB_PTE - ITLB pte - read and write in different formats */
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#define ITBR_PTE_V_ASM 13
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#define ITBR_PTE_ASM (1u << ITBR_PTE_V_ASM)
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#define ITBR_PTE_V_KRE 18
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#define ITBR_PTE_GH0 0x00000000
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#define ITBR_PTE_GH1 0x20000000
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#define ITBR_PTE_GH2 0x60000000
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#define ITBR_PTE_GH3 0xE0000000
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/* ITB_ASN - ITLB ASN - read write */
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#define ITB_ASN_V_ASN 4
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#define ITB_ASN_M_ASN 0x7F
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#define ITB_ASN_WIDTH 7
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/* ITB_PTE_TEMP - ITLB PTE readout - read only */
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/* ITB_IA, ITB_IAP, ITB_IS - ITLB invalidates - write only */
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/* SIRR - software interrupt request register - read/write */
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#define SIRR_V_SIRR 4
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#define SIRR_M_SIRR 0x7FFF
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/* ASTRR, ASTEN - AST request, enable registers - read/write */
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#define AST_MASK 0xF /* AST bits */
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/* EXC_ADDR - read/write */
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/* EXC_SUMM - read/cleared on write */
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/* EXC_MASK - read only */
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/* PAL_BASE - read/write */
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#define PAL_BASE_RW 0x000000FFFFFFFFC000
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/* ICM - ITLB current mode - read/write */
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#define ICM_V_CM 3
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#define ICM_M_CM 0x3
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/* IPLR - interrupt priority level - read/write */
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#define IPLR_V_IPL 0
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#define IPLR_M_IPL 0x1F
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/* INTID - interrupt ID - read only */
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#define INTID_MASK 0x1F
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/* IFAULT_VA_FORM - formated fault VA - read only */
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/* IVPTBR - virtual page table base - read/write */
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#define IVPTBR_VMS 0xFFFFFFF800000000
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#define IVPTBR_NT 0xFFFFFFFFC0000000
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#define FMT_IVA_VMS(x) (ev5_ivptbr | (((x) >> (VA_N_OFF - 3)) & 0x1FFFFFFF8))
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#define FMT_IVA_NT(x) (ev5_ivptbr | (((x) >> (VA_N_OFF - 3)) & 0x0003FFFF8))
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/* HWINT_CLR - hardware interrupt clear - write only */
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#define HWINT_CLR_W1C 0x00000003C8000000
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/* SL_XMIT - serial line transmit - write only */
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/* SL_RCV - real line receive - read only */
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/* ICSR - Ibox control/status - read/write */
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#define ICSR_V_PME 8
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#define ICSR_M_PME 0x3
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#define ICSR_V_BSE 17
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#define ICSR_V_MSK0 20
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#define ICSR_V_MSK1 21
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#define ICSR_V_MSK2 22
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#define ICSR_V_MSK3 23
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#define ICSR_V_TMM 24
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#define ICSR_V_TMD 25
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#define ICSR_V_FPE 26
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#define ICSR_V_HWE 27
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#define ICSR_V_SPE 28
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#define ICSR_M_SPE 0x3
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#define ICSR_V_SDE 30
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#define ICSR_V_CRDE 32
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#define ICSR_V_SLE 33
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#define ICSR_V_FMS 34
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#define ICSR_V_FBT 35
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#define ICSR_V_FBD 36
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#define ICSR_V_BIST 38
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#define ICSR_V_TEST 39
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#define ICSR_NT (((t_uint64) 1u) << ICSR_V_SPE)
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#define ICSR_BSE (((t_uint64) 1u) << ICSR_V_BSE)
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#define ICSR_MSK0 (((t_uint64) 1u) << ICSR_V_MSK0)
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#define ICSR_MSK1 (((t_uint64) 1u) << ICSR_V_MSK1)
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#define ICSR_MSK2 (((t_uint64) 1u) << ICSR_V_MSK2)
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#define ICSR_MSK3 (((t_uint64) 1u) << ICSR_V_MSK3)
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#define ICSR_HWE (((t_uint64) 1u) << ICSR_V_HWE)
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#define ICSR_SDE (((t_uint64) 1u) << ICSR_V_SDE)
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#define ICSR_CRDE (((t_uint64) 1u) << ICSR_V_CRDE)
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#define ICSR_SLE (((t_uint64) 1u) << ICSR_V_SLE)
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#define ICSR_RW 0x0000009F4BF00300
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#define ICSR_MBO 0x0000006000000000
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/* IC_FLUSH_CTL - Icache flush control - write only */
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/* ICPERR_STAT - Icache parity status - read/write 1 to clear */
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#define ICPERR_V_DPE 11
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#define ICPERR_V_TPE 12
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#define ICPERR_V_TMO 13
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#define ICPERR_DPE (1u << ICPERR_V_DPE)
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#define ICPERR_TPE (1u << ICPERR_V_TPE)
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#define ICPERR_TMO (1u << ICPERR_V_TMO)
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#define ICPERR_W1C (ICPERR_DPE|ICPERR_TPE|ICPERR_TMO)
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/* Mbox registers */
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/* DTB_ASN - DTLB ASN - write only */
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#define DTB_ASN_V_ASN 57
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#define DTB_ASN_M_ASN 0x7F
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#define DTB_ASN_WIDTH 7
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/* DTB_CM - DTLB current mode - write only */
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#define DCM_V_CM 3
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#define DCM_M_CM 0x3
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/* DTB_TAG - DTLB tag and update - write only */
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/* DTB_PTE - DTLB PTE - read/write */
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/* DTB_PTE_TEMP - DTLB PTE read out register - read only */
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/* MM_STAT - data fault status register - read only */
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#define MM_STAT_WR 0x00001
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#define MM_STAT_ACV 0x00002
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#define MM_STAT_FOR 0x00004
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#define MM_STAT_FOW 0x00008
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#define MM_STAT_TBM 0x00010
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#define MM_STAT_BVA 0x00020
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#define MM_STAT_V_RA 6
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#define MM_STAT_IMASK 0x1FFC0
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/* VA - data fault virtual address - read only */
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/* VA_FORM - data fault formated virtual address - read only */
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#define FMT_MVA_VMS(x) (ev5_mvptbr | (((x) >> (VA_N_OFF - 3)) & 0x1FFFFFFF8))
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#define FMT_MVA_NT(x) (ev5_mvptbr | (((x) >> (VA_N_OFF - 3)) & 0x0003FFFF8))
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/* MVPTBR - DTB virtual page table base - write only */
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#define MVPTBR_MBZ ((t_uint64) 0x3FFFFFFF)
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/* DTB_IAP, DTB_IA, DTB_IS - DTB invalidates - write only */
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/* ALT_MODE - DTLB current mode - write only */
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#define ALT_V_CM 3
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#define ALT_M_CM 0x3
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/* CC - cycle counter - upper half is RW, lower half is RO */
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/* CC_CTL - cycle counter control - write only */
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#define CC_CTL_ENB 0x100000000
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#define CC_CTL_MBZ 0xF
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/* MCSR - Mbox control/status register - read/write */
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#define MCSR_RW 0x11
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#define MCSR_V_SPE 1
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#define MCSR_M_SPE 0x3
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#define MCSR_NT 0x02
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/* DC_PERR_STAT - data cache parity error status - read/write */
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#define DC_PERR_W1C 0x3
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#define DC_PERR_ERR 0x1C
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/* DC_MODE - data cache mode - read/write */
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#define DC_MODE_RW 0xF
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/* MAF_MODE - miss address file mode - read/write */
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#define MAF_MODE_RW 0xFF
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/* DC_TEST_CTL - data cache test control - read/write */
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#define DC_TEST_CTL_RW 0x1FFFB
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/* DC_TEST_TAG - data cache test tag - read/write */
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#define DC_TEST_TAG_RW 0x0000007FFFFFFF04
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/* Function prototypes (TLB interface) */
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void tlb_ia (uint32 flags);
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void tlb_is (t_uint64 va, uint32 flags);
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void itlb_set_asn (uint32 asn);
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void itlb_set_cm (uint32 mode);
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void itlb_set_spage (uint32 spage);
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TLBENT *itlb_lookup (uint32 vpn);
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TLBENT *itlb_load (uint32 vpn, t_uint64 pte);
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t_uint64 itlb_read (void);
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void dtlb_set_asn (uint32 asn);
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void dtlb_set_cm (uint32 mode);
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void dtlb_set_spage (uint32 spage);
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TLBENT *dtlb_lookup (uint32 vpn);
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TLBENT *dtlb_load (uint32 vpn, t_uint64 pte);
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t_uint64 dtlb_read (void);
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#endif
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