b1766b6dcf
- Recent changes in vax_watch.c changed the input parameter from a physical address to a register address within the watch chip. - vax630_sysdev.c called the older wtc_wr() with the new parameter, but the length argument has been removed. - The watch chip never starts as valid. Make it valid when the TODR is attached (i.e. reflecting a connected battery). - 64 bytes of bus addresses for the watch chip can sometimes be dispatched to wtc_rd() and wtc_wr(). Make sure that reasonable memory is always referenced for all potential accesses. - restore vax8200 to makefile which got lost in a prior merge.
558 lines
16 KiB
C
558 lines
16 KiB
C
/* vax4xx_stddev.c: KA4xx standard devices
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Copyright (c) 2019, Matt Burke
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This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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rom bootstrap ROM (no registers)
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nvr non-volatile ROM (no registers)
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or option ROMs (no registers)
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clk 100Hz and TODR clock
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*/
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#include "vax_defs.h"
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#define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */
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#define UNIT_NODELAY (1u << UNIT_V_NODELAY)
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#define CLKCSR_IMP (CSR_IE) /* real-time clock */
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#define CLKCSR_RW (CSR_IE)
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#define CLK_DELAY 5000 /* 100 Hz */
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#define TMXR_MULT 1 /* 100 Hz */
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uint32 *rom = NULL; /* boot ROM */
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uint32 *nvr = NULL; /* non-volatile mem */
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int32 clk_csr = 0; /* control/status */
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int32 clk_tps = 100; /* ticks/second */
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int32 tmr_int = 0; /* interrupt */
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int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */
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int32 tmr_poll = CLK_DELAY; /* pgm timer poll */
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t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat rom_reset (DEVICE *dptr);
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t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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const char *rom_description (DEVICE *dptr);
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t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat nvr_reset (DEVICE *dptr);
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t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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t_stat nvr_attach (UNIT *uptr, CONST char *cptr);
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t_stat nvr_detach (UNIT *uptr);
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const char *nvr_description (DEVICE *dptr);
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t_stat or_reset (DEVICE *dptr);
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t_stat or_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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const char *or_description (DEVICE *dptr);
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t_stat clk_svc (UNIT *uptr);
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t_stat clk_reset (DEVICE *dptr);
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const char *clk_description (DEVICE *dptr);
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extern int32 sysd_hlt_enb (void);
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/* ROM data structures
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rom_dev ROM device descriptor
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rom_unit ROM units
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rom_reg ROM register list
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*/
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UNIT rom_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK, ROMSIZE) };
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REG rom_reg[] = {
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{ NULL }
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};
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MTAB rom_mod[] = {
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{ UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL, NULL, NULL, "Disable calibrated ROM access speed" },
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{ UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL, NULL, NULL, "Enable calibrated ROM access speed" },
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{ 0 }
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};
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DEVICE rom_dev = {
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"ROM", &rom_unit, rom_reg, rom_mod,
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1, 16, ROMAWIDTH, 4, 16, 32,
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&rom_ex, &rom_dep, &rom_reset,
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NULL, NULL, NULL,
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NULL, 0, 0, NULL, NULL, NULL, &rom_help, NULL, NULL,
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&rom_description
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};
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/* NVR data structures
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nvr_dev NVR device descriptor
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nvr_unit NVR units
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nvr_reg NVR register list
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*/
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UNIT nvr_unit =
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{ UDATA (NULL, UNIT_FIX+UNIT_BINK, NVRSIZE) };
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REG nvr_reg[] = {
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{ NULL }
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};
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DEVICE nvr_dev = {
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"NVR", &nvr_unit, nvr_reg, NULL,
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1, 16, NVRAWIDTH, 4, 16, 32,
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&nvr_ex, &nvr_dep, &nvr_reset,
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NULL, &nvr_attach, &nvr_detach,
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NULL, 0, 0, NULL, NULL, NULL, &nvr_help, NULL, NULL,
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&nvr_description
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};
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/* OR data structures
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or_dev OR device descriptor
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or_unit OR unit descriptor
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or_reg OR register list
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*/
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UNIT or_unit[] = {
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{ UDATA (NULL, UNIT_FIX+UNIT_RO+UNIT_BINK, ORSIZE) },
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{ UDATA (NULL, UNIT_FIX+UNIT_RO+UNIT_BINK, ORSIZE) },
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{ UDATA (NULL, UNIT_FIX+UNIT_RO+UNIT_BINK, ORSIZE) },
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{ UDATA (NULL, UNIT_FIX+UNIT_RO+UNIT_BINK, ORSIZE) }
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};
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REG or_reg[] = {
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{ NULL }
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};
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DEVICE or_dev = {
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"OR", or_unit, or_reg, NULL,
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OR_COUNT, 16, ORAWIDTH, 4, 16, 32,
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NULL, NULL, &or_reset,
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NULL, NULL, NULL,
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NULL, 0, 0, NULL, NULL, NULL, &or_help, NULL, NULL,
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&or_description
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};
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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*/
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UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };
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REG clk_reg[] = {
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{ HRDATAD (CSR, clk_csr, 16, "control/status register") },
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{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
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{ FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
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{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
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{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
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{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
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#if defined (SIM_ASYNCH_IO)
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{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
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{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
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{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
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#endif
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{ NULL }
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, NULL,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
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&clk_description
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};
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/* ROM: read only memory - stored in a buffered file
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Register space access routines see ROM twice
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ROM access has been 'regulated' to about 1Mhz to avoid issues
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with testing the interval timers in self-test. Specifically,
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the VAX boot ROM (ka4xx.bin) contains code which presumes that
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the VAX runs at a particular slower speed when code is running
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from ROM (which is not cached). These assumptions are built
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into instruction based timing loops. As the host platform gets
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much faster than the original VAX, the assumptions embedded in
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these code loops are no longer valid.
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Code has been added to the ROM implementation to limit CPU speed
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to about 500K instructions per second. This heads off any future
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issues with the embedded timing loops.
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*/
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int32 rom_rd (int32 pa)
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{
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int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2;
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int32 val = rom[rg];
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if (rom_unit.flags & UNIT_NODELAY)
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return val;
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return sim_rom_read_with_delay (val);
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}
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void rom_wr_B (int32 pa, int32 val)
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{
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int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2;
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int32 sc = (pa & 3) << 3;
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rom[rg] = ((val & 0xFF) << sc) | (rom[rg] & ~(0xFF << sc));
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return;
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}
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/* ROM examine */
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t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if ((vptr == NULL) || (addr & 03))
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return SCPE_ARG;
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if (addr >= ROMSIZE)
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return SCPE_NXM;
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*vptr = rom[addr >> 2];
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return SCPE_OK;
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}
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/* ROM deposit */
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t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if (addr & 03)
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return SCPE_ARG;
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if (addr >= ROMSIZE)
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return SCPE_NXM;
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rom[addr >> 2] = (uint32) val;
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return SCPE_OK;
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}
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/* ROM reset */
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t_stat rom_reset (DEVICE *dptr)
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{
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if (rom == NULL)
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rom = (uint32 *) calloc (ROMSIZE >> 2, sizeof (uint32));
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if (rom == NULL)
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return SCPE_MEM;
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return SCPE_OK;
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}
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t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf (st, "Read-only memory (ROM)\n\n");
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fprintf (st, "The boot ROM consists of a single unit, simulating the 256KB boot ROM. It has\n");
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fprintf (st, "no registers. The boot ROM is loaded with a binary byte stream using the \n");
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fprintf (st, "LOAD -r command:\n\n");
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fprintf (st, " LOAD -r KA410.BIN load ROM image KA410.BIN\n\n");
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fprintf (st, "When the simulator starts running (via the BOOT command), if the ROM has\n");
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fprintf (st, "not yet been loaded, an attempt will be made to automatically load the\n");
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fprintf (st, "ROM image from the file ka410.bin in the current working directory.\n");
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fprintf (st, "If that load attempt fails, then a copy of the missing ROM file is\n");
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fprintf (st, "written to the current directory and the load attempt is retried.\n\n");
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fprintf (st, "ROM accesses a use a calibrated delay that slows ROM-based execution to\n");
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fprintf (st, "about 500K instructions per second. This delay is required to make the\n");
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fprintf (st, "power-up self-test routines run correctly on very fast hosts.\n");
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fprint_set_help (st, dptr);
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return SCPE_OK;
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}
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const char *rom_description (DEVICE *dptr)
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{
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return "read-only memory";
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}
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/* NVR: non-volatile RAM - stored in a buffered file */
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int32 nvr_rd (int32 pa)
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{
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int32 rg = (pa - NVRBASE) >> 2;
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int32 val;
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if (rg < 14) /* watch chip */
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val = wtc_rd (rg);
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else
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val = nvr[rg];
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return (val << 2);
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}
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void nvr_wr (int32 pa, int32 val, int32 lnt)
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{
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int32 rg = (pa - NVRBASE) >> 2;
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val = val >> 2;
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if (rg < 14) /* watch chip */
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wtc_wr (rg, val);
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else {
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int32 sc = (pa & 3) << 3; /* merge */
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int32 mask = 0xFF;
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nvr[rg] = ((val & mask) << sc) | (nvr[rg] & ~(mask << sc));
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}
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}
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/* NVR examine */
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t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if ((vptr == NULL) || (addr & 03))
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return SCPE_ARG;
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if (addr >= NVRSIZE)
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return SCPE_NXM;
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*vptr = nvr[addr >> 2];
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return SCPE_OK;
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}
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/* NVR deposit */
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t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if (addr & 03)
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return SCPE_ARG;
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if (addr >= NVRSIZE)
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return SCPE_NXM;
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nvr[addr >> 2] = (uint32) val;
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return SCPE_OK;
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}
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/* NVR reset */
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t_stat nvr_reset (DEVICE *dptr)
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{
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if (nvr == NULL) {
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nvr = (uint32 *) calloc (NVRSIZE >> 2, sizeof (uint32));
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nvr_unit.filebuf = nvr;
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}
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if (nvr == NULL)
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return SCPE_MEM;
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return SCPE_OK;
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}
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t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf (st, "Non-volatile Memory (NVR)\n\n");
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fprintf (st, "The NVR simulates %d bytes of battery-backed up memory.\n", NVRSIZE);
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fprintf (st, "When the simulator starts, NVR is cleared to 0, and the battery-low indicator\n");
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fprintf (st, "is set. Alternately, NVR can be attached to a file. This allows the NVR\n");
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fprintf (st, "state to be preserved across simulator runs. Successfully attaching an NVR\n");
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fprintf (st, "image clears the battery-low indicator.\n\n");
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return SCPE_OK;
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}
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/* NVR attach */
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t_stat nvr_attach (UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE);
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r = attach_unit (uptr, cptr);
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if (r != SCPE_OK)
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uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE);
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else {
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uptr->hwmark = (uint32) uptr->capac;
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wtc_set_valid ();
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}
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return r;
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}
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/* NVR detach */
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t_stat nvr_detach (UNIT *uptr)
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{
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t_stat r;
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r = detach_unit (uptr);
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if ((uptr->flags & UNIT_ATT) == 0) {
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uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE);
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wtc_set_invalid ();
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}
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return r;
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}
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const char *nvr_description (DEVICE *dptr)
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{
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return "non-volatile memory";
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}
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/* OR routines
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or_rd I/O page read
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or_reset process reset
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*/
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int32 or_rd (int32 pa)
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{
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uint32 off = (pa - ORBASE); /* offset from start of option roms */
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uint32 rn = ((off >> 18) & 0x3); /* rom number (0 - 3) */
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UNIT *uptr = &or_dev.units[rn]; /* get unit */
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uint8 *opr = (uint8*) uptr->filebuf;
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int32 data = 0;
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uint32 rg;
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if ((uptr->flags & UNIT_ATT) && (opr != NULL)) {
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switch (opr[0]) { /* number of ROM chips */
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case 1:
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rg = (off >> 2) & (uptr->capac - 1);
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data = (0xFFFFFF00 | (opr[rg] & 0xFF));
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return sim_rom_read_with_delay (data);
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case 2:
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rg = (off >> 1) & (uptr->capac - 1);
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data = data | opr[rg++];
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data = data | (opr[rg] << 8);
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data = (0xFFFF0000 | data);
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return sim_rom_read_with_delay (data);
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case 4:
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rg = off & (uptr->capac - 1);
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data = data | opr[rg++];
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data = data | (opr[rg++] << 8);
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data = data | (opr[rg++] << 16);
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data = data | (opr[rg++] << 24);
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return sim_rom_read_with_delay (data);
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}
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}
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return sim_rom_read_with_delay (0xFFFFFFFF);
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}
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t_stat or_reset (DEVICE *dptr)
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{
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return SCPE_OK;
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}
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t_stat or_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf (st, "Option ROMs (OR)\n\n");
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fprintf (st, "The OR simulates the read only memory present on option boards.\n");
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fprintf (st, "These ROMs contain the self-test code that is called by the main\n");
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fprintf (st, "ROM during system power up. The system uses these ROMs to determine\n");
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fprintf (st, "which option boards are present.\n");
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return SCPE_OK;
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}
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t_stat or_map (uint32 index, uint8 *rom, t_addr size)
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{
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UNIT *uptr = &or_unit[index];
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uptr->filebuf = (void *)rom;
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uptr->capac = size;
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uptr->flags |= UNIT_ATT;
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return SCPE_OK;
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}
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t_stat or_unmap (uint32 index)
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{
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UNIT *uptr = &or_unit[index];
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uptr->filebuf = NULL;
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uptr->capac = 0;
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uptr->flags &= ~UNIT_ATT;
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return SCPE_OK;
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}
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|
const char *or_description (DEVICE *dptr)
|
|
{
|
|
return "option ROMs";
|
|
}
|
|
|
|
/* Clock MxPR routines
|
|
|
|
iccs_rd/wr interval timer
|
|
*/
|
|
|
|
int32 iccs_rd (void)
|
|
{
|
|
return (clk_csr & CLKCSR_IMP);
|
|
}
|
|
|
|
void iccs_wr (int32 data)
|
|
{
|
|
if ((data & CSR_IE) == 0)
|
|
tmr_int = 0;
|
|
if (data & CSR_DONE)
|
|
sim_rtcn_tick_ack (20, TMR_CLK);
|
|
clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
|
|
return;
|
|
}
|
|
|
|
/* Clock routines
|
|
|
|
clk_svc process event (clock tick)
|
|
clk_reset process reset
|
|
clk_description return device description
|
|
*/
|
|
|
|
t_stat clk_svc (UNIT *uptr)
|
|
{
|
|
int32 t;
|
|
|
|
if (clk_csr & CSR_IE)
|
|
tmr_int = 1;
|
|
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
|
|
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
|
|
tmr_poll = t; /* set tmr poll */
|
|
tmxr_poll = t * TMXR_MULT; /* set mux poll */
|
|
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat clk_reset (DEVICE *dptr)
|
|
{
|
|
int32 t;
|
|
|
|
clk_csr = 0;
|
|
tmr_int = 0;
|
|
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
|
|
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
|
|
tmr_poll = t; /* set tmr poll */
|
|
tmxr_poll = t * TMXR_MULT; /* set mux poll */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
const char *clk_description (DEVICE *dptr)
|
|
{
|
|
return "100hz clock tick";
|
|
}
|
|
|
|
/* Dummy I/O space functions */
|
|
|
|
int32 ReadIO (uint32 pa, int32 lnt)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void WriteIO (uint32 pa, int32 val, int32 lnt)
|
|
{
|
|
return;
|
|
}
|
|
|
|
int32 ReadIOU (uint32 pa, int32 lnt)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void WriteIOU (uint32 pa, int32 val, int32 lnt)
|
|
{
|
|
return;
|
|
}
|