9d849283a4
- This change introduces a full refactor of the interrupt subsystem
for the system board (SBD) and the I/O bus (CIO). Interrupt decode
should now be significantly faster, and not require an expensive
calculation on every step.
- The TIMER device has been split into Rev 2 and Rev 3
implementations.
- The optional 3B2/400 Debug Monitor ROMs can now be booted by passing
the "DEMON" argument to the 3B2/400 simulator BOOT command. Any
of the following will cause the Debug Monitor ROM to be booted
instead of the standard 3B2/400 ROM:
sim> BOOT DEMON
sim> BOOT CPU DEMON
sim> BOOT DEMON CPU
324 lines
7.5 KiB
C
324 lines
7.5 KiB
C
/* 3b2_mem.c: AT&T 3B2 memory access routines
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Copyright (c) 2021, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#include "3b2_mem.h"
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#include "3b2_cpu.h"
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#include "3b2_csr.h"
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#include "3b2_io.h"
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#include "3b2_mmu.h"
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t_bool addr_is_rom(uint32 pa)
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{
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return (pa < rom_size);
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}
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t_bool addr_is_mem(uint32 pa)
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{
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return (pa >= PHYS_MEM_BASE &&
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pa < (PHYS_MEM_BASE + MEM_SIZE));
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}
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t_bool addr_is_io(uint32 pa)
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{
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#if defined(REV3)
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return ((pa >= IO_BOTTOM && pa < IO_TOP) ||
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(pa >= CIO_BOTTOM && pa < CIO_TOP) ||
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(pa >= VCACHE_BOTTOM && pa < VCACHE_TOP) ||
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(pa >= BUB_BOTTOM && pa < BUB_TOP));
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#else
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return ((pa >= IO_BOTTOM && pa < IO_TOP) ||
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(pa >= CIO_BOTTOM && pa < CIO_TOP));
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#endif
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}
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/* Read Word (Physical Address) */
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uint32 pread_w(uint32 pa)
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{
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uint32 *m;
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uint32 index;
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if (pa & 3) {
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sim_debug(READ_MSG, &mmu_dev,
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"[%08x] Cannot read physical address. ALIGNMENT ISSUE: %08x\n",
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R[NUM_PC], pa);
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CSRBIT(CSRALGN, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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if (addr_is_io(pa)) {
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return io_read(pa, 32);
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}
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if (addr_is_rom(pa)) {
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m = ROM;
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index = pa >> 2;
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} else if (addr_is_mem(pa)) {
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m = RAM;
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index = (pa - PHYS_MEM_BASE) >> 2;
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} else {
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return 0;
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}
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return m[index];
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}
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/*
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* Write Word (Physical Address)
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*/
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void pwrite_w(uint32 pa, uint32 val)
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{
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if (pa & 3) {
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sim_debug(WRITE_MSG, &mmu_dev,
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"[%08x] Cannot write physical address. ALIGNMENT ISSUE: %08x\n",
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R[NUM_PC], pa);
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CSRBIT(CSRALGN, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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if (addr_is_io(pa)) {
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io_write(pa, val, 32);
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return;
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}
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if (addr_is_mem(pa)) {
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RAM[(pa - PHYS_MEM_BASE) >> 2] = val;
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return;
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}
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}
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/*
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* Read Halfword (Physical Address)
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*/
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uint16 pread_h(uint32 pa)
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{
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uint32 *m;
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uint32 index;
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if (pa & 1) {
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sim_debug(READ_MSG, &mmu_dev,
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"[%08x] Cannot read physical address. ALIGNMENT ISSUE %08x\n",
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R[NUM_PC], pa);
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CSRBIT(CSRALGN, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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if (addr_is_io(pa)) {
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return (uint16) io_read(pa, 16);
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}
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if (addr_is_rom(pa)) {
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m = ROM;
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index = pa >> 2;
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} else if (addr_is_mem(pa)) {
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m = RAM;
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index = (pa - PHYS_MEM_BASE) >> 2;
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} else {
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return 0;
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}
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if (pa & 2) {
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return m[index] & HALF_MASK;
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} else {
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return (m[index] >> 16) & HALF_MASK;
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}
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}
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/*
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* Write Halfword (Physical Address)
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*/
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void pwrite_h(uint32 pa, uint16 val)
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{
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uint32 *m;
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uint32 index;
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uint32 wval = (uint32)val;
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if (pa & 1) {
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sim_debug(WRITE_MSG, &mmu_dev,
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"[%08x] Cannot write physical address %08x, ALIGNMENT ISSUE\n",
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R[NUM_PC], pa);
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CSRBIT(CSRALGN, TRUE);
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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if (addr_is_io(pa)) {
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io_write(pa, val, 16);
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return;
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}
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if (addr_is_mem(pa)) {
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m = RAM;
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index = (pa - PHYS_MEM_BASE) >> 2;
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} else {
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return;
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}
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if (pa & 2) {
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m[index] = (m[index] & ~HALF_MASK) | wval;
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} else {
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m[index] = (m[index] & HALF_MASK) | (wval << 16);
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}
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}
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/*
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* Read Byte (Physical Address)
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*/
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uint8 pread_b(uint32 pa)
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{
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uint32 data;
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int32 sc = (~(pa & 3) << 3) & 0x1f;
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if (addr_is_io(pa)) {
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return (uint8)(io_read(pa, 8));
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}
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if (addr_is_rom(pa)) {
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data = ROM[pa >> 2];
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} else if (addr_is_mem(pa)) {
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data = RAM[(pa - PHYS_MEM_BASE) >> 2];
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} else {
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return 0;
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}
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return (data >> sc) & BYTE_MASK;
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}
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/* Write Byte (Physical Address) */
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void pwrite_b(uint32 pa, uint8 val)
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{
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uint32 *m;
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int32 index;
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int32 sc = (~(pa & 3) << 3) & 0x1f;
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uint32 mask = 0xffu << sc;
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if (addr_is_io(pa)) {
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io_write(pa, val, 8);
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return;
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}
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if (addr_is_mem(pa)) {
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m = RAM;
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index = (pa - PHYS_MEM_BASE) >> 2;
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m[index] = (m[index] & ~mask) | (uint32) (val << sc);
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return;
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}
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}
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/* Read Byte (Virtual Address) */
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uint8 read_b(uint32 va, uint8 r_acc)
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{
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return pread_b(mmu_xlate_addr(va, r_acc));
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}
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/* Write Byte (Virtual Address) */
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void write_b(uint32 va, uint8 val)
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{
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pwrite_b(mmu_xlate_addr(va, ACC_W), val);
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}
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/* Read Halfword (Virtual Address) */
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uint16 read_h(uint32 va, uint8 r_acc)
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{
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return pread_h(mmu_xlate_addr(va, r_acc));
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}
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/* Write Halfword (Virtual Address) */
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void write_h(uint32 va, uint16 val)
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{
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pwrite_h(mmu_xlate_addr(va, ACC_W), val);
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}
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/* Read Word (Virtual Address) */
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uint32 read_w(uint32 va, uint8 r_acc)
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{
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return pread_w(mmu_xlate_addr(va, r_acc));
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}
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/* Write Word (Virtual Address) */
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void write_w(uint32 va, uint32 val)
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{
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pwrite_w(mmu_xlate_addr(va, ACC_W), val);
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}
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t_stat read_operand(uint32 va, uint8 *val)
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{
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uint32 pa;
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t_stat succ;
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succ = mmu_decode_va(va, ACC_IF, TRUE, &pa);
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if (succ == SCPE_OK) {
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*val = pread_b(pa);
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} else {
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*val = 0;
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}
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return succ;
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}
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t_stat examine(uint32 va, uint8 *val)
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{
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uint32 pa;
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t_stat succ;
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succ = mmu_decode_va(va, 0, FALSE, &pa);
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if (succ == SCPE_OK) {
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if (addr_is_rom(pa) || addr_is_mem(pa)) {
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*val = pread_b(pa);
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return SCPE_OK;
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} else {
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*val = 0;
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return SCPE_NXM;
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}
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} else {
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*val = 0;
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return succ;
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}
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}
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t_stat deposit(uint32 va, uint8 val)
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{
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uint32 pa;
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t_stat succ;
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succ = mmu_decode_va(va, 0, FALSE, &pa);
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if (succ == SCPE_OK) {
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if (addr_is_mem(pa)) {
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pwrite_b(pa, val);
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return SCPE_OK;
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} else {
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return SCPE_NXM;
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}
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} else {
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return succ;
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}
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}
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