351 lines
No EOL
13 KiB
C
351 lines
No EOL
13 KiB
C
/* i8274.c: Intel i8274 MPSC adapter
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Copyright (c) 2011, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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These functions support a simulated i8274 interface device on an iSBC.
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The device had two physical I/O ports which could be connected
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to any serial I/O device that would connect to an RS232 interface.
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All I/O is via programmed I/O. The i8274 has a status port
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and a data port.
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The simulated device does not support synchronous mode. The simulated device
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supports a select from I/O space and two address lines. The data port is at the
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lower address and the status/command port is at the higher address for each
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channel.
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Minimum simulation is provided for this device. Channel A is used as a
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console port for the iSBC-88/45
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A write to the status port can select some options for the device:
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Asynchronous Mode Instruction
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+---+---+---+---+---+---+---+---+
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| S2 S1 EP PEN L2 L1 B2 B1|
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+---+---+---+---+---+---+---+---+
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Baud Rate Factor
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B2 0 1 0 1
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B1 0 0 1 1
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sync 1X 16X 64X
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mode
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Character Length
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L2 0 1 0 1
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L1 0 0 1 1
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5 6 7 8
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bits bits bits bits
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EP - A 1 in this bit position selects even parity.
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PEN - A 1 in this bit position enables parity.
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Number of Stop Bits
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S2 0 1 0 1
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S1 0 0 1 1
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invalid 1 1.5 2
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bit bits bits
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Command Instruction Format
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+---+---+---+---+---+---+---+---+
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| EH IR RTS ER SBRK RxE DTR TxE|
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+---+---+---+---+---+---+---+---+
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TxE - A 1 in this bit position enables transmit.
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DTR - A 1 in this bit position forces *DTR to zero.
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RxE - A 1 in this bit position enables receive.
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SBRK - A 1 in this bit position forces TxD to zero.
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ER - A 1 in this bit position resets the error bits
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RTS - A 1 in this bit position forces *RTS to zero.
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IR - A 1 in this bit position returns the 8251 to Mode Instruction Format.
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EH - A 1 in this bit position enables search for sync characters.
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A read of the status port gets the port status:
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Status Read Format
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+---+---+---+---+---+---+---+---+
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|DSR SD FE OE PE TxE RxR TxR|
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+---+---+---+---+---+---+---+---+
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TxR - A 1 in this bit position signals transmit ready to receive a character.
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RxR - A 1 in this bit position signals receiver has a character.
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TxE - A 1 in this bit position signals transmitter has no more characters to transmit.
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PE - A 1 in this bit signals a parity error.
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OE - A 1 in this bit signals an transmit overrun error.
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FE - A 1 in this bit signals a framing error.
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SD - A 1 in this bit position returns the 8251 to Mode Instruction Format.
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DSR - A 1 in this bit position signals *DSR is at zero.
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A read to the data port gets the buffered character, a write
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to the data port writes the character to the device.
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*/
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#include <stdio.h>
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#include "multibus_defs.h"
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#define UNIT_V_ANSI (UNIT_V_UF + 0) /* ANSI mode */
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#define UNIT_ANSI (1 << UNIT_V_ANSI)
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/* register definitions */
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/* channel A */
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uint8 wr0a = 0, /* command register */
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wr1a = 0, /* enable register */
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wr2a = 0, /* mode register */
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wr3a = 0, /* configuration register 1 */
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wr4a = 0, /* configuration register 2 */
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wr5a = 0, /* configuration register 3 */
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wr6a = 0, /* sync low byte */
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wr7a = 0, /* sync high byte */
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rr0a = 0, /* status register */
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rr1a = 0, /* error register */
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rr2a = 0; /* read interrupt vector */
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/* channel B */
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uint8 wr0b = 0, /* command register */
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wr1b = 0, /* enable register */
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wr2b = 0, /* CH B interrups vector */
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wr3b = 0, /* configuration register 1 */
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wr4b = 0, /* configuration register 2 */
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wr5b = 0, /* configuration register 3 */
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wr6b = 0, /* sync low byte */
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wr7b = 0, /* sync high byte */
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rr0b = 0, /* status register */
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rr1b = 0, /* error register */
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rr2b = 0; /* read interrupt vector */
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/* function prototypes */
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t_stat i8274_svc (UNIT *uptr);
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t_stat i8274_reset (DEVICE *dptr);
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int32 i8274As(int32 io, int32 data);
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int32 i8274Ad(int32 io, int32 data);
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int32 i8274Bs(int32 io, int32 data);
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int32 i8274Bd(int32 io, int32 data);
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/* i8274 Standard I/O Data Structures */
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UNIT i8274_unit = { UDATA (NULL, 0, 0), KBD_POLL_WAIT };
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REG i8274_reg[] = {
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{ HRDATA (WR0A, wr0a, 8) },
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{ HRDATA (WR1A, wr1a, 8) },
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{ HRDATA (WR2A, wr2a, 8) },
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{ HRDATA (WR3A, wr3a, 8) },
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{ HRDATA (WR4A, wr4a, 8) },
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{ HRDATA (WR5A, wr5a, 8) },
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{ HRDATA (WR6A, wr6a, 8) },
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{ HRDATA (WR7A, wr7a, 8) },
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{ HRDATA (RR0A, rr0a, 8) },
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{ HRDATA (RR0A, rr1a, 8) },
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{ HRDATA (RR0A, rr2a, 8) },
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{ HRDATA (WR0B, wr0b, 8) },
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{ HRDATA (WR1B, wr1b, 8) },
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{ HRDATA (WR2B, wr2b, 8) },
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{ HRDATA (WR3B, wr3b, 8) },
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{ HRDATA (WR4B, wr4b, 8) },
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{ HRDATA (WR5B, wr5b, 8) },
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{ HRDATA (WR6B, wr6b, 8) },
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{ HRDATA (WR7B, wr7b, 8) },
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{ HRDATA (RR0B, rr0b, 8) },
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{ HRDATA (RR0B, rr1b, 8) },
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{ HRDATA (RR0B, rr2b, 8) },
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{ NULL }
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};
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MTAB i8274_mod[] = {
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{ UNIT_ANSI, 0, "TTY", "TTY", NULL },
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{ UNIT_ANSI, UNIT_ANSI, "ANSI", "ANSI", NULL },
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{ 0 }
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};
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DEBTAB i8274_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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DEVICE i8274_dev = {
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"I8274", //name
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&i8274_unit, //units
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i8274_reg, //registers
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i8274_mod, //modifiers
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1, //numunits
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16, //aradix
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32, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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i8274_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG, //flags
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0, //dctrl
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i8274_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* Service routines to handle simulator functions */
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/* service routine - actually gets char & places in buffer in CH A*/
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t_stat i8274_svc (UNIT *uptr)
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{
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int32 temp;
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sim_activate (&i8274_unit, i8274_unit.wait); /* continue poll */
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if ((temp = sim_poll_kbd ()) < SCPE_KFLAG)
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return temp; /* no char or error? */
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i8274_unit.buf = temp & 0xFF; /* Save char */
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rr0a |= 0x01; /* Set rx char ready */
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/* Do any special character handling here */
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i8274_unit.pos++;
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat i8274_reset (DEVICE *dptr)
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{
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wr0a = wr1a = wr2a = wr3a = wr4a = wr5a = wr6a = wr7a = rr0a = rr1a = rr2a = 0;
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wr0b = wr1b = wr2b = wr3b = wr4b = wr5b = wr6b = wr7b = rr0b = rr1b = rr2b = 0;
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sim_printf(" 8274 Reset\n");
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return SCPE_OK;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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Each function is passed an 'io' flag, where 0 means a read from
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the port, and 1 means a write to the port. On input, the actual
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input is passed as the return value, on output, 'data' is written
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to the device.
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The 8274 contains 2 separate channels, A and B.
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*/
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/* channel A command/status */
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int32 i8274As(int32 io, int32 data)
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{
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if (io == 0) { /* read status port */
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switch(wr0a & 0x7) {
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case 0: /* rr0a */
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return rr0a;
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case 1: /* rr1a */
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return rr1a;
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case 2: /* rr1a */
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return rr2a;
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}
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return 0; /* bad register select */
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} else { /* write status port */
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switch(wr0a & 0x7) {
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case 0: /* wr0a */
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wr0a = data;
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if ((wr0a & 0x38) == 0x18) { /* channel reset */
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wr0a = wr1a = wr2a = wr3a = wr4a = wr5a = 0;
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wr6a = wr7a = rr0a = rr1a = rr2a = 0;
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sim_printf("8274 Channel A reset\n");
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}
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break;
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case 1: /* wr1a */
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wr1a = data;
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break;
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case 2: /* wr2a */
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wr2a = data;
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break;
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case 3: /* wr3a */
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wr3a = data;
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break;
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case 4: /* wr4a */
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wr4a = data;
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break;
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case 5: /* wr5a */
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wr5a = data;
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break;
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case 6: /* wr6a */
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wr6a = data;
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break;
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case 7: /* wr7a */
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wr7a = data;
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break;
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}
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sim_printf("8274 Command WR%dA=%02X\n", wr0a & 0x7, data);
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return 0;
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}
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}
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/* channel A data */
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int32 i8274Ad(int32 io, int32 data)
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{
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if (io == 0) { /* read data port */
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rr0a &= 0xFE;
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return (i8274_unit.buf);
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} else { /* write data port */
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sim_putchar(data);
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}
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return 0;
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}
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/* channel B command/status */
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int32 i8274Bs(int32 io, int32 data)
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{
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if (io == 0) { /* read status port */
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return i8274_unit.u3;
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} else { /* write status port */
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if (data == 0x40) { /* reset port! */
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sim_printf("8274 Reset\n");
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} else if (i8274_unit.u6) {
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i8274_unit.u5 = data;
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sim_printf("8274 Command Instruction=%02X\n", data);
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} else {
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i8274_unit.u4 = data;
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sim_printf("8274 Mode Instruction=%02X\n", data);
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i8274_unit.u6++;
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}
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return (0);
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}
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}
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/* channel B data */
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int32 i8274Bd(int32 io, int32 data)
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{
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if (io == 0) { /* read data port */
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i8274_unit.u3 &= 0xFD;
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return (i8274_unit.buf);
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} else { /* write data port */
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sim_putchar(data);
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}
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return 0;
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}
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/* end of i8274.c */ |