9c4779c061
The makefile now works for Linux and most Unix's. Howevr, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
318 lines
12 KiB
C
318 lines
12 KiB
C
/* pdp11_pclk.c: KW11P programmable clock simulator
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Copyright (c) 1993-2008, Robert M Supnik
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Written by John Dundas, used with his gracious permission
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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pclk KW11P line frequency clock
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20-May-08 RMS Standardized clock delay at 1mips
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18-Jun-07 RMS Added UNIT_IDLE flag
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07-Jul-05 RMS Removed extraneous externs
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KW11-P Programmable Clock
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I/O Page Registers:
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CSR 17 772 540
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CSB 17 772 542
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CNT 17 772 544
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Vector: 0104
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Priority: BR6
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** Theory of Operation **
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A real KW11-P is built around the following major components:
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- 16-bit up/down counter
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- 16-bit count set buffer
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- 9-bit control and status register
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- clocks: crystal controlled (1) 100 kHz and (2) 10 kHz clocks,
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(3) a 50/60 Hz line frequency clock, and (4) an analog signal
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input trigger
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This software emulator for SIMH implements all of the above with
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the exception of the external input trigger, which is arbitrarily
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wired to 10Hz.
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Operation of this emulator is rather simplistic as compared to the
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actual device. The register read and write routines are responsible
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for copying internal state from the simulated device to the operating
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program. Clock state variables are altered in the write routine
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as well as the desired clock ticking rate. Possible rates are
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given in the table below.
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Rate Bit 2 Bit 1
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100 kHz 0 0
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10 kHz 0 1
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Line frequency 1 0
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External 1 1
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I think SIMH would have a hard time actually keeping up with a 100
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kHz ticking rate. I haven't tried this to verify, though.
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The clock service routine (pclk_svc) is responsible for ticking
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the clock. The routine does implement up/down, repeat vs.
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single-interrupt, and single clocking (maintenance). The routine
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updates the internal state according to the options selected and
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signals interrupts when appropriate.
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For a complete description of the device, please see DEC-11-HPWB-D
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KW11-P Programmable Real-Time Clock Manual.
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** Notes **
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1. The device is disabled by default.
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2. Use XXDP V2.5 test program ZKWBJ1.BIC; loads at 1000, starts at
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1100? Seems to execute the first few tests correctly then waits
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for input from the console. I don't have a description of how this
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diagnostic works and thus don't know how to proceed from that point.
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3. The read and write routines don't do anything with odd address
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accesses. The manual says that byte writes don't work.
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4. RSTS can use this clock in place of the standard KW11-L line
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frequency clock. In order to do this, use the DEFAULT response in
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the OPTION: dialog. To the Preferred clock prompt answer "P".
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Then you have the option of line frequency "L" or some multiple of
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50 between 50 and 1000 to use the programmable portion of the clock.
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5. This is really a Unibus peripheral and thus doesn't actually make
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sense within a J-11 system as there never was a Qbus version of
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this to the best of my knowledge. However the OSs I have tried
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don't appear to exhibit any dissonance between this option and the
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processor/bus emulation. I think the options that would make
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somewhat more sense in a Qbus environment the KWV11-C and/or KWV11-S.
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I don't know if any of the -11 OSs contained support for using
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these as the system clock, though.
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*/
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#include "pdp11_defs.h"
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#define PCLKCSR_RDMASK 0100377 /* readable */
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#define PCLKCSR_WRMASK 0000137 /* writeable */
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#define UNIT_V_LINE50HZ (UNIT_V_UF + 0)
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#define UNIT_LINE50HZ (1 << UNIT_V_LINE50HZ)
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/* CSR - 17772540 */
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#define CSR_V_FIX 5 /* single tick */
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#define CSR_V_UPDN 4 /* down/up */
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#define CSR_V_MODE 3 /* single/repeat */
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#define CSR_FIX (1u << CSR_V_FIX)
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#define CSR_UPDN (1u << CSR_V_UPDN)
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#define CSR_MODE (1u << CSR_V_MODE)
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#define CSR_V_RATE 1 /* rate */
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#define CSR_M_RATE 03
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#define CSR_GETRATE(x) (((x) >> CSR_V_RATE) & CSR_M_RATE)
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extern int32 int_req[IPL_HLVL];
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uint32 pclk_csr = 0; /* control/status */
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uint32 pclk_csb = 0; /* count set buffer */
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uint32 pclk_ctr = 0; /* counter */
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static uint32 rate[4] = { 100000, 10000, 60, 10 }; /* ticks per second */
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static uint32 xtim[4] = { 10, 100, 16667, 100000 }; /* nominal time delay */
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DEVICE pclk_dev;
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t_stat pclk_rd (int32 *data, int32 PA, int32 access);
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t_stat pclk_wr (int32 data, int32 PA, int32 access);
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t_stat pclk_svc (UNIT *uptr);
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t_stat pclk_reset (DEVICE *dptr);
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t_stat pclk_set_line (UNIT *uptr, int32 val, char *cptr, void *desc);
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void pclk_tick (void);
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/* PCLK data structures
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pclk_dev PCLK device descriptor
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pclk_unit PCLK unit descriptor
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pclk_reg PCLK register list
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*/
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DIB pclk_dib = {
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IOBA_PCLK, IOLN_PCLK, &pclk_rd, &pclk_wr,
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1, IVCL (PCLK), VEC_PCLK, { NULL }
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};
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UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) };
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REG pclk_reg[] = {
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{ ORDATA (CSR, pclk_csr, 16) },
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{ ORDATA (CSB, pclk_csb, 16) },
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{ ORDATA (CNT, pclk_ctr, 16) },
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{ FLDATA (INT, IREQ (PCLK), INT_V_PCLK) },
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{ FLDATA (OVFL, pclk_csr, CSR_V_ERR) },
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{ FLDATA (DONE, pclk_csr, CSR_V_DONE) },
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{ FLDATA (IE, pclk_csr, CSR_V_IE) },
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{ FLDATA (UPDN, pclk_csr, CSR_V_UPDN) },
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{ FLDATA (MODE, pclk_csr, CSR_V_MODE) },
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{ FLDATA (RUN, pclk_csr, CSR_V_GO) },
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{ BRDATA (TIME, xtim, 10, 32, 4), REG_NZ + PV_LEFT },
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{ BRDATA (TPS, rate, 10, 32, 4), REG_NZ + PV_LEFT },
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{ DRDATA (CURTIM, pclk_unit.wait, 32), REG_HRO },
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{ ORDATA (DEVADDR, pclk_dib.ba, 32), REG_HRO },
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{ ORDATA (DEVVEC, pclk_dib.vec, 16), REG_HRO },
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{ NULL }
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};
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MTAB pclk_mod[] = {
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{ UNIT_LINE50HZ, UNIT_LINE50HZ, "50 Hz", "50HZ", &pclk_set_line },
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{ UNIT_LINE50HZ, 0, "60 Hz", "60HZ", &pclk_set_line },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
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&set_vec, &show_vec, NULL },
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{ 0 }
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};
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DEVICE pclk_dev = {
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"PCLK", &pclk_unit, pclk_reg, pclk_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &pclk_reset,
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NULL, NULL, NULL,
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&pclk_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS
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};
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/* Clock I/O address routines */
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t_stat pclk_rd (int32 *data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 03) {
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case 00: /* CSR */
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*data = pclk_csr & PCLKCSR_RDMASK; /* return CSR */
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pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE); /* clr err, done */
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CLR_INT (PCLK); /* clr intr */
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break;
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case 01: /* buffer */
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*data = 0; /* read only */
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break;
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case 02: /* counter */
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*data = pclk_ctr & DMASK; /* return counter */
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break;
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}
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return SCPE_OK;
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}
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t_stat pclk_wr (int32 data, int32 PA, int32 access)
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{
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int32 old_csr = pclk_csr;
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int32 rv;
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switch ((PA >> 1) & 03) {
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case 00: /* CSR */
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pclk_csr = data & PCLKCSR_WRMASK; /* clear and write */
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CLR_INT (PCLK); /* clr intr */
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rv = CSR_GETRATE (pclk_csr); /* new rate */
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pclk_unit.wait = xtim[rv]; /* new delay */
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if ((pclk_csr & CSR_GO) == 0) { /* stopped? */
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sim_cancel (&pclk_unit); /* cancel */
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if (data & CSR_FIX) /* fix? tick */
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pclk_tick ();
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}
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else if (((old_csr & CSR_GO) == 0) || /* run 0 -> 1? */
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(rv != CSR_GETRATE (old_csr))) { /* rate change? */
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sim_cancel (&pclk_unit); /* cancel */
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sim_activate (&pclk_unit, /* start clock */
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sim_rtcn_init (pclk_unit.wait, TMR_PCLK));
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}
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break;
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case 01: /* buffer */
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pclk_csb = pclk_ctr = data; /* store ctr */
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pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE); /* clr err, done */
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CLR_INT (PCLK); /* clr intr */
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break;
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case 02: /* counter */
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break; /* read only */
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}
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return SCPE_OK;
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}
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/* Clock tick (automatic or manual) */
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void pclk_tick (void)
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{
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if (pclk_csr & CSR_UPDN) /* up or down? */
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pclk_ctr = (pclk_ctr + 1) & DMASK; /* 1 = up */
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else pclk_ctr = (pclk_ctr - 1) & DMASK; /* 0 = down */
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if (pclk_ctr == 0) { /* reached zero? */
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if (pclk_csr & CSR_DONE) /* done already set? */
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pclk_csr = pclk_csr | CSR_ERR; /* set error */
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else pclk_csr = pclk_csr | CSR_DONE; /* else set done */
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if (pclk_csr & CSR_IE) /* if IE, set int */
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SET_INT (PCLK);
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if (pclk_csr & CSR_MODE) /* if rpt, reload */
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pclk_ctr = pclk_csb;
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else {
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pclk_csb = 0; /* else clr ctr */
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pclk_csr = pclk_csr & ~CSR_GO; /* and clr go */
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}
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}
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return;
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}
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/* Clock service */
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t_stat pclk_svc (UNIT *uptr)
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{
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int32 rv;
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pclk_tick (); /* tick clock */
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if ((pclk_csr & CSR_GO) == 0) /* done? */
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return SCPE_OK;
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rv = CSR_GETRATE (pclk_csr); /* get rate */
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sim_activate (&pclk_unit, sim_rtcn_calb (rate[rv], TMR_PCLK));
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return SCPE_OK;
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}
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/* Clock reset */
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t_stat pclk_reset (DEVICE *dptr)
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{
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pclk_csr = 0; /* clear reg */
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pclk_csb = 0;
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pclk_ctr = 0;
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CLR_INT (PCLK); /* clear int */
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sim_cancel (&pclk_unit); /* cancel */
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pclk_unit.wait = xtim[0]; /* reset delay */
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return SCPE_OK;
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}
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/* Set line frequency */
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t_stat pclk_set_line (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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if (val == UNIT_LINE50HZ)
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rate[2] = 50;
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else rate[2] = 60;
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return SCPE_OK;
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}
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