1010 lines
32 KiB
C
1010 lines
32 KiB
C
/* vax630_sysdev.c: MicroVAX II system-specific logic
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Copyright (c) 2009-2012, Matt Burke
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This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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This module contains the MicroVAX II system-specific registers and devices.
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rom bootstrap ROM (no registers)
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nvr non-volatile ROM (no registers)
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sysd system devices
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08-Nov-2012 MB First version
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*/
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#include "vax_defs.h"
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#include <time.h>
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#ifdef DONT_USE_INTERNAL_ROM
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#if defined(VAX_620)
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#define BOOT_CODE_FILENAME "ka620.bin"
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#else
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#define BOOT_CODE_FILENAME "ka320.bin"
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#endif
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#else /* !DONT_USE_INTERNAL_ROM */
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#if defined(VAX_620)
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#include "vax_ka620_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */
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#else
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#include "vax_ka630_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */
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#endif
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#endif /* DONT_USE_INTERNAL_ROM */
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#define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */
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#define UNIT_NODELAY (1u << UNIT_V_NODELAY)
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t_stat vax630_boot (int32 flag, char *ptr);
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int32 sys_model = 0;
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/* Special boot command, overrides regular boot */
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CTAB vax630_cmd[] = {
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{ "BOOT", &vax630_boot, RU_BOOT,
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"bo{ot} boot simulator\n", &run_cmd_message },
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{ NULL }
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};
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/* KA630 boot/diagnostic register */
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#define BDR_DISP 0x0000000F /* LED display */
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#define BDR_V_BDC 8 /* boot/diag code */
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#define BDR_M_BDC 0x3
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#define BDR_BDC (BDR_M_BDC << BDR_V_BDC)
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#define BDR_V_CPUC 11 /* cpu code */
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#define BDR_M_CPUC 0x3
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#define BDR_CPUC (BDR_M_CPUC << BDR_V_CPUC)
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#define BDR_BRKENB 0x00004000 /* break enable */
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#define BDR_POK 0x00008000 /* power ok */
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#define BDR_RD (BDR_DISP | BDR_BDC | BDR_CPUC | BDR_BRKENB | BDR_POK)
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#define BDR_WR (BDR_DISP)
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/* BDR boot/diagnostic codes */
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#define BDC_NORM 0x0 /* normal startup */
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#define BDC_LNGI 0x1 /* language inquiry */
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#define BDC_TSTL 0x2 /* test loop */
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#define BDC_SKPM 0x3 /* skip mem test */
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/* BDR CPU codes */
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#define CPUC_ARB 0x0 /* arbiter */
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#define CPUC_AUX1 0x1 /* auxiliary 1 */
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#define CPUC_AUX2 0x2 /* auxiliary 2 */
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#define CPUC_AUX3 0x3 /* auxiliary 3 */
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/* KA630 Memory system error register */
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#define MSER_PE 0x00000001 /* Parity Enable */
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#define MSER_WWP 0x00000002 /* Write Wrong Parity */
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#define MSER_LEB 0x00000008 /* Lost Error Bit */
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#define MSER_DQPE 0x00000010 /* DMA Q22 Parity Err */
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#define MSER_CQPE 0x00000020 /* CPU Q22 Parity Err */
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#define MSER_CLPE 0x00000040 /* CPU Mem Parity Err */
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#define MSER_NXM 0x00000080 /* CPU NXM */
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#define MSER_MCD0 0x00000100 /* Mem Code 0 */
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#define MSER_MCD1 0x00000200 /* Mem Code 1 */
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#define MSER_MBZ 0xFFFFFC04
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#define MSER_RD (MSER_PE | MSER_WWP | MSER_LEB | \
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MSER_DQPE | MSER_CQPE | MSER_CLPE | \
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MSER_NXM | MSER_MCD0 | MSER_MCD1)
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#define MSER_WR (MSER_PE | MSER_WWP)
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#define MSER_RS (MSER_LEB | MSER_DQPE | MSER_CQPE | MSER_CLPE | MSER_NXM)
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/* KA630 CPU error address reg */
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#define CEAR_LMADD 0x00007FFF /* local mem addr */
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#define CEAR_RD (CEAR_LMADD)
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/* KA630 DMA error address reg */
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#define DEAR_LMADD 0x00007FFF /* local mem addr */
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#define DEAR_RD (DEAR_LMADD)
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extern int32 R[16];
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extern int32 STK[5];
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extern int32 PSL;
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extern int32 SISR;
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extern int32 SCBB;
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extern int32 mapen;
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extern int32 pcq[PCQ_SIZE];
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extern int32 pcq_p;
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extern int32 ibcnt, ppc;
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extern int32 in_ie;
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extern int32 mchk_va, mchk_ref;
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extern int32 fault_PC;
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extern int32 int_req[IPL_HLVL];
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extern UNIT cpu_unit;
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extern UNIT clk_unit;
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extern jmp_buf save_env;
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extern int32 p1;
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extern int32 tmr_poll;
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uint32 *rom = NULL; /* boot ROM */
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uint32 *nvr = NULL; /* non-volatile mem */
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int32 conisp, conpc, conpsl; /* console reg */
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int32 ka_bdr = BDR_BRKENB; /* KA630 boot diag */
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int32 ka_mser = 0; /* KA630 mem sys err */
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int32 ka_cear = 0; /* KA630 cpu err */
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int32 ka_dear = 0; /* KA630 dma err */
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static uint32 rom_delay = 0;
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t_bool ka_diag_full = FALSE;
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t_bool ka_hltenab = TRUE; /* Halt Enable / Autoboot flag */
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t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat rom_reset (DEVICE *dptr);
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t_stat rom_set_diag (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat rom_show_diag (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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char *rom_description (DEVICE *dptr);
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t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat nvr_reset (DEVICE *dptr);
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t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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t_stat nvr_attach (UNIT *uptr, char *cptr);
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t_stat nvr_detach (UNIT *uptr);
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char *nvr_description (DEVICE *dptr);
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t_stat sysd_reset (DEVICE *dptr);
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t_stat sysd_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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char *sysd_description (DEVICE *dptr);
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int32 rom_rd (int32 pa);
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int32 nvr_rd (int32 pa);
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void nvr_wr (int32 pa, int32 val, int32 lnt);
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int32 ka_rd (int32 pa);
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void ka_wr (int32 pa, int32 val, int32 lnt);
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t_stat sysd_powerup (void);
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int32 con_halt (int32 code, int32 cc);
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extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
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extern int32 qbmap_rd (int32 pa);
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extern void qbmap_wr (int32 pa, int32 val, int32 lnt);
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extern int32 qbmem_rd (int32 pa);
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extern void qbmem_wr (int32 pa, int32 val, int32 lnt);
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extern int32 wtc_rd (int32 pa);
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extern void wtc_wr (int32 pa, int32 val, int32 lnt);
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extern void wtc_set_valid (void);
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extern void wtc_set_invalid (void);
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extern int32 iccs_rd (void);
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extern int32 todr_rd (void);
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extern int32 rxcs_rd (void);
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extern int32 rxdb_rd (void);
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extern int32 txcs_rd (void);
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extern void iccs_wr (int32 dat);
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extern void todr_wr (int32 dat);
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extern void rxcs_wr (int32 dat);
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extern void txcs_wr (int32 dat);
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extern void txdb_wr (int32 dat);
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extern void ioreset_wr (int32 dat);
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/* ROM data structures
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rom_dev ROM device descriptor
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rom_unit ROM units
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rom_reg ROM register list
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*/
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UNIT rom_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK, ROMSIZE) };
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REG rom_reg[] = {
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{ NULL }
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};
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MTAB rom_mod[] = {
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{ UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL, NULL, NULL, "Disable calibrated ROM access speed" },
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{ UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL, NULL, NULL, "Enable calibrated ROM access speed" },
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{ 0 }
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};
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DEVICE rom_dev = {
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"ROM", &rom_unit, rom_reg, rom_mod,
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1, 16, ROMAWIDTH, 4, 16, 32,
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&rom_ex, &rom_dep, &rom_reset,
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NULL, NULL, NULL,
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NULL, 0, 0, NULL, NULL, NULL, &rom_help, NULL, NULL,
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&rom_description
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};
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/* NVR data structures
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nvr_dev NVR device descriptor
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nvr_unit NVR units
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nvr_reg NVR register list
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*/
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UNIT nvr_unit =
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{ UDATA (NULL, UNIT_FIX+UNIT_BINK, NVRSIZE) };
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REG nvr_reg[] = {
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{ NULL }
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};
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DEVICE nvr_dev = {
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"NVR", &nvr_unit, nvr_reg, NULL,
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1, 16, NVRAWIDTH, 4, 16, 32,
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&nvr_ex, &nvr_dep, &nvr_reset,
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NULL, &nvr_attach, &nvr_detach,
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NULL, 0, 0, NULL, NULL, NULL, &nvr_help, NULL, NULL,
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&nvr_description
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};
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/* SYSD data structures
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sysd_dev SYSD device descriptor
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sysd_unit SYSD units
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sysd_reg SYSD register list
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*/
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UNIT sysd_unit = { UDATA (NULL, 0, 0) };
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REG sysd_reg[] = {
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{ HRDATAD (CONISP, conisp, 32, "console ISP") },
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{ HRDATAD (CONPC, conpc, 32, "console PD") },
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{ HRDATAD (CONPSL, conpsl, 32, "console PSL") },
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{ HRDATAD (BDR, ka_bdr, 16, "KA630 boot diag") },
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{ HRDATAD (MSER, ka_mser, 8, "KA630 mem sys err") },
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{ HRDATAD (CEAR, ka_cear, 8, "KA630 cpu err") },
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{ HRDATAD (DEAR, ka_dear, 8, "KA630 dma err") },
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{ HRDATAD (DEAR, ka_dear, 8, "KA630 dma err") },
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{ FLDATAD (DIAG, ka_diag_full, 0, "KA630 Full Boot diagnostics") },
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{ FLDATAD (HLTENAB, ka_hltenab, 0, "KA630 Autoboot/Halt Enable") },
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{ NULL }
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};
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DEVICE sysd_dev = {
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"SYSD", &sysd_unit, sysd_reg, NULL,
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1, 16, 16, 1, 16, 8,
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NULL, NULL, &sysd_reset,
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NULL, NULL, NULL,
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NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
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&sysd_description
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};
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/* ROM: read only memory - stored in a buffered file
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Register space access routines see ROM twice
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ROM access has been 'regulated' to about 1Mhz to avoid issues
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with testing the interval timers in self-test. Specifically,
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the VAX boot ROM (ka630.bin) contains code which presumes that
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the VAX runs at a particular slower speed when code is running
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from ROM (which is not cached). These assumptions are built
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into instruction based timing loops. As the host platform gets
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much faster than the original VAX, the assumptions embedded in
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these code loops are no longer valid.
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Code has been added to the ROM implementation to limit CPU speed
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to about 500K instructions per second. This heads off any future
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issues with the embedded timing loops.
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*/
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int32 rom_swapb(int32 val)
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{
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return ((val << 24) & 0xff000000) | (( val << 8) & 0xff0000) |
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((val >> 8) & 0xff00) | ((val >> 24) & 0xff);
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}
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int32 rom_read_delay (int32 val)
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{
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uint32 i, l = rom_delay;
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int32 loopval = 0;
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if (rom_unit.flags & UNIT_NODELAY)
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return val;
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/* Calibrate the loop delay factor when first used.
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Do this 4 times to and use the largest value computed. */
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if (rom_delay == 0) {
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uint32 ts, te, c = 10000, samples = 0;
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while (1) {
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c = c * 2;
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te = sim_os_msec();
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while (te == (ts = sim_os_msec ())); /* align on ms tick */
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/* This is merely a busy wait with some "work" that won't get optimized
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away by a good compiler. loopval always is zero. To avoid smart compilers,
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the loopval variable is referenced in the function arguments so that the
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function expression is not loop invariant. It also must be referenced
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by subsequent code or to avoid the whole computation being eliminated. */
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for (i = 0; i < c; i++)
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loopval |= (loopval + ts) ^ rom_swapb (rom_swapb (loopval + ts));
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te = sim_os_msec ();
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if ((te - ts) < 50) /* sample big enough? */
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continue;
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if (rom_delay < (loopval + (c / (te - ts) / 1000) + 1))
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rom_delay = loopval + (c / (te - ts) / 1000) + 1;
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if (++samples >= 4)
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break;
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c = c / 2;
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}
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if (rom_delay < 5)
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rom_delay = 5;
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}
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for (i = 0; i < l; i++)
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loopval |= (loopval + val) ^ rom_swapb (rom_swapb (loopval + val));
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return val + loopval;
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}
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int32 rom_rd (int32 pa)
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{
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int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2;
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return rom_read_delay (rom[rg]);
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}
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void rom_wr_B (int32 pa, int32 val)
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{
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int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2;
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int32 sc = (pa & 3) << 3;
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rom[rg] = ((val & 0xFF) << sc) | (rom[rg] & ~(0xFF << sc));
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return;
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}
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/* ROM examine */
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t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if ((vptr == NULL) || (addr & 03))
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return SCPE_ARG;
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if (addr >= ROMSIZE)
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return SCPE_NXM;
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*vptr = rom[addr >> 2];
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return SCPE_OK;
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}
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/* ROM deposit */
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t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if (addr & 03)
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return SCPE_ARG;
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if (addr >= ROMSIZE)
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return SCPE_NXM;
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rom[addr >> 2] = (uint32) val;
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return SCPE_OK;
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}
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/* ROM reset */
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t_stat rom_reset (DEVICE *dptr)
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{
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if (rom == NULL)
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rom = (uint32 *) calloc (ROMSIZE >> 2, sizeof (uint32));
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if (rom == NULL)
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return SCPE_MEM;
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return SCPE_OK;
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}
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t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
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{
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fprintf (st, "Read-only memory (ROM)\n\n");
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fprintf (st, "The boot ROM consists of a single unit, simulating the 64KB boot ROM. It has\n");
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fprintf (st, "no registers. The boot ROM is loaded with a binary byte stream using the \n");
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fprintf (st, "LOAD -r command:\n\n");
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fprintf (st, " LOAD -r KA630.BIN load ROM image KA630.BIN\n\n");
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fprintf (st, "When the simulator starts running (via the BOOT command), if the ROM has\n");
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fprintf (st, "not yet been loaded, an attempt will be made to automatically load the\n");
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fprintf (st, "ROM image from the file ka655x.bin in the current working directory.\n");
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fprintf (st, "If that load attempt fails, then a copy of the missing ROM file is\n");
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fprintf (st, "written to the current directory and the load attempt is retried.\n\n");
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fprintf (st, "ROM accesses a use a calibrated delay that slows ROM-based execution to\n");
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fprintf (st, "about 500K instructions per second. This delay is required to make the\n");
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fprintf (st, "power-up self-test routines run correctly on very fast hosts.\n");
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fprint_set_help (st, dptr);
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fprintf (st, "By default the memory power-up self-tests are skipped as they take a long\n");
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fprintf (st, "time to complete. The self-test sequence can be controlled with the\n");
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fprintf (st, "following commands:\n\n");
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fprintf (st, " SET CPU DIAG=MIN Run minimal diagnostics (skip memory test)\n");
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fprintf (st, " SET CPU DIAG=FULL Run full diagnostics\n\n");
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return SCPE_OK;
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}
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char *rom_description (DEVICE *dptr)
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{
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return "read-only memory";
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}
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/* NVR: non-volatile RAM - stored in a buffered file */
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int32 nvr_rd (int32 pa)
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{
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int32 rg = (pa - NVRBASE) >> 2;
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if (rg < 7) /* watch chip */
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return wtc_rd (pa);
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else
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return nvr[rg];
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}
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void nvr_wr (int32 pa, int32 val, int32 lnt)
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{
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int32 rg = (pa - NVRBASE) >> 2;
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if (rg < 7) /* watch chip */
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wtc_wr (pa, val, lnt);
|
|
else {
|
|
int32 sc = (pa & 3) << 3; /* merge */
|
|
int32 mask = 0xFF;
|
|
nvr[rg] = ((val & mask) << sc) | (nvr[rg] & ~(mask << sc));
|
|
}
|
|
}
|
|
|
|
/* NVR examine */
|
|
|
|
t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
|
|
{
|
|
uint32 addr = (uint32) exta;
|
|
|
|
if ((vptr == NULL) || (addr & 03))
|
|
return SCPE_ARG;
|
|
if (addr >= NVRSIZE)
|
|
return SCPE_NXM;
|
|
*vptr = nvr[addr >> 2];
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* NVR deposit */
|
|
|
|
t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
|
|
{
|
|
uint32 addr = (uint32) exta;
|
|
|
|
if (addr & 03)
|
|
return SCPE_ARG;
|
|
if (addr >= NVRSIZE)
|
|
return SCPE_NXM;
|
|
nvr[addr >> 2] = (uint32) val;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* NVR reset */
|
|
|
|
t_stat nvr_reset (DEVICE *dptr)
|
|
{
|
|
if (nvr == NULL) {
|
|
nvr = (uint32 *) calloc (NVRSIZE >> 2, sizeof (uint32));
|
|
nvr_unit.filebuf = nvr;
|
|
}
|
|
if (nvr == NULL)
|
|
return SCPE_MEM;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
|
|
{
|
|
fprintf (st, "Non-volatile Memory (NVR)\n\n");
|
|
fprintf (st, "The NVR simulates 128 bytes of battery-backed up memory.\n");
|
|
fprintf (st, "When the simulator starts, NVR is cleared to 0, and the battery-low indicator\n");
|
|
fprintf (st, "is set. Alternately, NVR can be attached to a file. This allows the NVR\n");
|
|
fprintf (st, "state to be preserved across simulator runs. Successfully attaching an NVR\n");
|
|
fprintf (st, "image clears the battery-low indicator.\n\n");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* NVR attach */
|
|
|
|
t_stat nvr_attach (UNIT *uptr, char *cptr)
|
|
{
|
|
t_stat r;
|
|
|
|
uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE);
|
|
r = attach_unit (uptr, cptr);
|
|
if (r != SCPE_OK)
|
|
uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE);
|
|
else {
|
|
uptr->hwmark = (uint32) uptr->capac;
|
|
wtc_set_valid ();
|
|
}
|
|
return r;
|
|
}
|
|
|
|
/* NVR detach */
|
|
|
|
t_stat nvr_detach (UNIT *uptr)
|
|
{
|
|
t_stat r;
|
|
|
|
r = detach_unit (uptr);
|
|
if ((uptr->flags & UNIT_ATT) == 0) {
|
|
uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE);
|
|
wtc_set_invalid ();
|
|
}
|
|
return r;
|
|
}
|
|
|
|
char *nvr_description (DEVICE *dptr)
|
|
{
|
|
return "non-volatile memory";
|
|
}
|
|
|
|
/* Read KA630 specific IPR's */
|
|
|
|
int32 ReadIPR (int32 rg)
|
|
{
|
|
int32 val;
|
|
|
|
switch (rg) {
|
|
|
|
case MT_ICCS: /* ICCS */
|
|
val = iccs_rd ();
|
|
break;
|
|
|
|
case MT_RXCS: /* RXCS */
|
|
val = rxcs_rd ();
|
|
break;
|
|
|
|
case MT_RXDB: /* RXDB */
|
|
val = rxdb_rd ();
|
|
break;
|
|
|
|
case MT_TXCS: /* TXCS */
|
|
val = txcs_rd ();
|
|
break;
|
|
|
|
case MT_TXDB: /* TXDB */
|
|
val = 0;
|
|
break;
|
|
|
|
case MT_CONISP: /* console ISP */
|
|
val = conisp;
|
|
break;
|
|
|
|
case MT_CONPC: /* console PC */
|
|
val = conpc;
|
|
break;
|
|
|
|
case MT_CONPSL: /* console PSL */
|
|
val = conpsl;
|
|
break;
|
|
|
|
case MT_SID: /* SID */
|
|
#if defined(VAX_620)
|
|
val = VAX620_SID;
|
|
#else
|
|
val = VAX630_SID;
|
|
#endif
|
|
break;
|
|
|
|
case MT_NICR: /* NICR */
|
|
case MT_ICR: /* ICR */
|
|
case MT_TODR: /* TODR */
|
|
case MT_CSRS: /* CSRS */
|
|
case MT_CSRD: /* CSRD */
|
|
case MT_CSTS: /* CSTS */
|
|
case MT_CSTD: /* CSTD */
|
|
case MT_TBDR: /* TBDR */
|
|
case MT_CADR: /* CADR */
|
|
case MT_MCESR: /* MCESR */
|
|
case MT_CAER: /* CAER */
|
|
case MT_SBIFS: /* SBIFS */
|
|
case MT_SBIS: /* SBIS */
|
|
case MT_SBISC: /* SBISC */
|
|
case MT_SBIMT: /* SBIMT */
|
|
case MT_SBIER: /* SBIER */
|
|
case MT_SBITA: /* SBITA */
|
|
case MT_SBIQC: /* SBIQC */
|
|
case MT_TBDATA: /* TBDATA */
|
|
case MT_MBRK: /* MBRK */
|
|
case MT_PME: /* PME */
|
|
val = 0;
|
|
break;
|
|
|
|
default:
|
|
RSVD_OPND_FAULT;
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
/* Write KA630 specific IPR's */
|
|
|
|
void WriteIPR (int32 rg, int32 val)
|
|
{
|
|
switch (rg) {
|
|
|
|
case MT_ICCS: /* ICCS */
|
|
iccs_wr (val);
|
|
break;
|
|
|
|
case MT_RXCS: /* RXCS */
|
|
rxcs_wr (val);
|
|
break;
|
|
|
|
case MT_RXDB: /* RXDB */
|
|
break;
|
|
|
|
case MT_TXCS: /* TXCS */
|
|
txcs_wr (val);
|
|
break;
|
|
|
|
case MT_TXDB: /* TXDB */
|
|
txdb_wr (val);
|
|
break;
|
|
|
|
case MT_IORESET: /* IORESET */
|
|
ioreset_wr (val);
|
|
break;
|
|
|
|
case MT_SID:
|
|
case MT_CONISP:
|
|
case MT_CONPC:
|
|
case MT_CONPSL: /* halt reg */
|
|
RSVD_OPND_FAULT;
|
|
|
|
case MT_NICR: /* NICR */
|
|
case MT_ICR: /* ICR */
|
|
case MT_TODR: /* TODR */
|
|
case MT_CSRS: /* CSRS */
|
|
case MT_CSRD: /* CSRD */
|
|
case MT_CSTS: /* CSTS */
|
|
case MT_CSTD: /* CSTD */
|
|
case MT_TBDR: /* TBDR */
|
|
case MT_CADR: /* CADR */
|
|
case MT_MCESR: /* MCESR */
|
|
case MT_CAER: /* CAER */
|
|
case MT_SBIFS: /* SBIFS */
|
|
case MT_SBIS: /* SBIS */
|
|
case MT_SBISC: /* SBISC */
|
|
case MT_SBIMT: /* SBIMT */
|
|
case MT_SBIER: /* SBIER */
|
|
case MT_SBITA: /* SBITA */
|
|
case MT_SBIQC: /* SBIQC */
|
|
case MT_TBDATA: /* TBDATA */
|
|
case MT_MBRK: /* MBRK */
|
|
case MT_PME: /* PME */
|
|
break;
|
|
|
|
default:
|
|
RSVD_OPND_FAULT;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
/* Read/write I/O register space
|
|
|
|
These routines are the 'catch all' for address space map. Any
|
|
address that doesn't explicitly belong to memory, I/O, or ROM
|
|
is given to these routines for processing.
|
|
*/
|
|
|
|
struct reglink { /* register linkage */
|
|
uint32 low; /* low addr */
|
|
uint32 high; /* high addr */
|
|
int32 (*read)(int32 pa); /* read routine */
|
|
void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */
|
|
};
|
|
|
|
struct reglink regtable[] = {
|
|
{ QBMAPBASE, QBMAPBASE+QBMAPSIZE, &qbmap_rd, &qbmap_wr },
|
|
{ ROMBASE, ROMBASE+ROMSIZE+ROMSIZE, &rom_rd, NULL },
|
|
{ NVRBASE, NVRBASE+NVRSIZE, &nvr_rd, &nvr_wr },
|
|
{ KABASE, KABASE+KASIZE, &ka_rd, &ka_wr },
|
|
/* { QVMBASE, QVMBASE+QVMSIZE, &qv_mem_rd, &qv_mem_wr }, */
|
|
{ QBMBASE, QBMBASE+QBMSIZE, &qbmem_rd, &qbmem_wr },
|
|
{ 0, 0, NULL, NULL }
|
|
};
|
|
|
|
/* ReadReg - read register space
|
|
|
|
Inputs:
|
|
pa = physical address
|
|
lnt = length (BWLQ) - ignored
|
|
Output:
|
|
longword of data
|
|
*/
|
|
|
|
int32 ReadReg (uint32 pa, int32 lnt)
|
|
{
|
|
struct reglink *p;
|
|
|
|
for (p = ®table[0]; p->low != 0; p++) {
|
|
if ((pa >= p->low) && (pa < p->high) && p->read)
|
|
return p->read (pa);
|
|
}
|
|
|
|
MACH_CHECK (MCHK_READ);
|
|
}
|
|
|
|
/* WriteReg - write register space
|
|
|
|
Inputs:
|
|
pa = physical address
|
|
val = data to write, right justified in 32b longword
|
|
lnt = length (BWLQ)
|
|
Outputs:
|
|
none
|
|
*/
|
|
|
|
void WriteReg (uint32 pa, int32 val, int32 lnt)
|
|
{
|
|
struct reglink *p;
|
|
|
|
for (p = ®table[0]; p->low != 0; p++) {
|
|
if ((pa >= p->low) && (pa < p->high) && p->write) {
|
|
p->write (pa, val, lnt);
|
|
return;
|
|
}
|
|
}
|
|
|
|
MACH_CHECK (MCHK_WRITE);
|
|
}
|
|
|
|
/* KA630 registers */
|
|
|
|
int32 ka_rd (int32 pa)
|
|
{
|
|
int32 rg = (pa - KABASE) >> 2;
|
|
|
|
switch (rg) {
|
|
|
|
case 0: /* BDR */
|
|
return ka_bdr & BDR_RD;
|
|
|
|
case 1: /* MSER */
|
|
return ka_mser & MSER_RD;
|
|
|
|
case 2: /* CEAR */
|
|
return ka_cear & CEAR_RD;
|
|
|
|
case 3: /* DEAR */
|
|
return ka_dear & DEAR_RD;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ka_wr (int32 pa, int32 val, int32 lnt)
|
|
{
|
|
int32 rg = (pa - KABASE) >> 2;
|
|
|
|
switch (rg) {
|
|
|
|
case 0: /* BDR */
|
|
ka_bdr = (ka_bdr & ~BDR_WR) | (val & BDR_WR);
|
|
break;
|
|
|
|
case 1: /* MSER */
|
|
ka_mser = (ka_mser & ~MSER_WR) | (val & MSER_WR);
|
|
ka_mser = ka_mser & ~(val & MSER_RS);
|
|
break;
|
|
|
|
case 2: /* CEAR */
|
|
case 3: /* DEAR */
|
|
break;
|
|
}
|
|
return;
|
|
}
|
|
|
|
int32 sysd_hlt_enb (void)
|
|
{
|
|
return ka_bdr & BDR_BRKENB;
|
|
}
|
|
|
|
/* Machine check */
|
|
|
|
int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta)
|
|
{
|
|
int32 st, p2, acc;
|
|
|
|
if (in_ie) {
|
|
in_ie = 0;
|
|
return con_halt(CON_DBLMCK, cc); /* double machine check */
|
|
}
|
|
if (p1 & 0x80) /* mref? set v/p */
|
|
p1 = p1 + mchk_ref;
|
|
p2 = mchk_va + 4; /* save vap */
|
|
st = 0;
|
|
if (p1 & 0x80) { /* mref? */
|
|
cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take normal exception */
|
|
if (!(ka_mser & MSER_CQPE) && !(ka_mser & MSER_CLPE))
|
|
ka_mser |= MSER_NXM;
|
|
}
|
|
else cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take severe exception */
|
|
acc = ACC_MASK (KERN); /* in kernel mode */
|
|
in_ie = 1;
|
|
SP = SP - 16; /* push 4 words */
|
|
Write (SP, 12, L_LONG, WA); /* # bytes */
|
|
Write (SP + 4, p1, L_LONG, WA); /* mcheck type */
|
|
Write (SP + 8, p2, L_LONG, WA); /* address */
|
|
Write (SP + 12, st, L_LONG, WA); /* state */
|
|
in_ie = 0;
|
|
return cc;
|
|
}
|
|
|
|
/* Console entry */
|
|
|
|
int32 con_halt (int32 code, int32 cc)
|
|
{
|
|
int32 temp;
|
|
|
|
conisp = IS; /* save ISP */
|
|
conpc = PC; /* save PC */
|
|
conpsl = ((PSL | cc) & 0xFFFF00FF) | code; /* PSL, param */
|
|
temp = (PSL >> PSL_V_CUR) & 0x7; /* get is'cur */
|
|
if (temp > 4) /* invalid? */
|
|
conpsl = conpsl | CON_BADPSL;
|
|
else STK[temp] = SP; /* save stack */
|
|
if (mapen) /* mapping on? */
|
|
conpsl = conpsl | CON_MAPON;
|
|
mapen = 0; /* turn off map */
|
|
SP = IS; /* set SP from IS */
|
|
PSL = PSL_IS | PSL_IPL1F; /* PSL = 41F0000 */
|
|
JUMP (ROMBASE); /* PC = 20040000 */
|
|
return 0; /* new cc = 0 */
|
|
}
|
|
|
|
|
|
/* Special boot command - linked into SCP by initial reset
|
|
|
|
Syntax: BOOT {CPU}
|
|
|
|
*/
|
|
|
|
t_stat vax630_boot (int32 flag, char *ptr)
|
|
{
|
|
char gbuf[CBUFSIZE];
|
|
|
|
get_glyph (ptr, gbuf, 0); /* get glyph */
|
|
if (gbuf[0] && strcmp (gbuf, "CPU"))
|
|
return SCPE_ARG; /* Only can specify CPU device */
|
|
return run_cmd (flag, "CPU");
|
|
}
|
|
|
|
|
|
/* Bootstrap */
|
|
|
|
t_stat cpu_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
t_stat r;
|
|
|
|
PC = ROMBASE;
|
|
PSL = PSL_IS | PSL_IPL1F;
|
|
conisp = 0;
|
|
conpc = 0;
|
|
conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP;
|
|
if (rom == NULL)
|
|
return SCPE_IERR;
|
|
if (*rom == 0) { /* no boot? */
|
|
r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, TRUE, 0);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat sysd_set_diag (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
if (cptr != NULL) ka_diag_full = strcmp(cptr, "MIN");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat sysd_show_diag (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
fprintf(st, "DIAG=%s", (ka_diag_full ? "full" :"min"));
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat sysd_set_halt (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
ka_hltenab = val;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat sysd_show_halt (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
fprintf(st, "%s", ka_hltenab ? "NOAUTOBOOT" : "AUTOBOOT");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* SYSD reset */
|
|
|
|
t_stat sysd_reset (DEVICE *dptr)
|
|
{
|
|
if (sim_switches & SWMASK ('P')) sysd_powerup (); /* powerup? */
|
|
ka_bdr = (BDR_POK | \
|
|
((ka_diag_full ? BDC_NORM : BDC_SKPM) << BDR_V_BDC) | \
|
|
(CPUC_ARB << BDR_V_CPUC) | \
|
|
(ka_hltenab ? BDR_BRKENB : 0) | \
|
|
0xF);
|
|
ka_mser = 0;
|
|
ka_cear = 0;
|
|
ka_dear = 0;
|
|
|
|
sim_vm_cmd = vax630_cmd;
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
char *sysd_description (DEVICE *dptr)
|
|
{
|
|
return "system devices";
|
|
}
|
|
|
|
/* SYSD powerup */
|
|
|
|
t_stat sysd_powerup (void)
|
|
{
|
|
ka_diag_full = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat cpu_print_model (FILE *st)
|
|
{
|
|
#if defined(VAX_620)
|
|
fprintf (st, "rtVAX 1000");
|
|
#else
|
|
fprintf (st, "MicroVAX II");
|
|
#endif
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
|
|
{
|
|
fprintf (st, "Initial memory size is 16MB.\n\n");
|
|
fprintf (st, "The CPU supports the BOOT command and is the only VAX device to do so. Note\n");
|
|
fprintf (st, "that the behavior of the bootstrap depends on the capabilities of the console\n");
|
|
fprintf (st, "terminal emulator. If the terminal window supports full VT100 emulation\n");
|
|
fprintf (st, "(including Multilanguage Character Set support), the bootstrap will ask the\n");
|
|
fprintf (st, "user to specify the language; otherwise, it will default to English.\n\n");
|
|
fprintf (st, "The simulator is booted with the BOOT command:\n\n");
|
|
fprintf (st, " sim> BOOT\n\n");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
|
|
{
|
|
uint32 memsize = (uint32)(MEMSIZE>>20);
|
|
uint32 baseaddr = 0;
|
|
struct {
|
|
uint32 capacity;
|
|
char *option;
|
|
} boards[] = {
|
|
{ 16, "MS630-CA"},
|
|
{ 4, "MS630-BB"},
|
|
{ 2, "MS630-BA"},
|
|
{ 1, "MS630-AA"},
|
|
{ 0, NULL}};
|
|
int32 i;
|
|
|
|
while (memsize > 1) {
|
|
for (i=0; boards[i].capacity > memsize; ++i)
|
|
;
|
|
if (memsize == 2)
|
|
i = 3;
|
|
fprintf(st, "Memory (@0x%08x): %3d Mbytes (%s)\n", baseaddr, boards[i].capacity, boards[i].option);
|
|
memsize -= boards[i].capacity;
|
|
baseaddr += boards[i].capacity<<20;
|
|
}
|
|
if (memsize)
|
|
fprintf(st, "Memory (0x%08x): 1 Mbytes (On-Board)\n", baseaddr);
|
|
return SCPE_OK;
|
|
}
|