349 lines
12 KiB
C
349 lines
12 KiB
C
/* i8255.c: Intel i8255 PIO adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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?? ??? 10 - Original file.
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16 Dec 12 - Modified to use isbc_80_10.cfg file to set i8255_baseport and size.
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24 Apr 15 -- Modified to use simh_debug
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NOTES:
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These functions support a simulated i8255 interface device on an iSBC.
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The device has threee physical 8-bit I/O ports which could be connected
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to any parallel I/O device.
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All I/O is via programmed I/O. The i8255 has a control port (i8255s)
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and three data ports (i8255a, i8255b, and i8255c).
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The simulated device supports a select from I/O space and two address lines.
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The data ports are at the lower addresses and the control port is at
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the highest.
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A write to the control port can configure the device:
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Control Word
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+---+---+---+---+---+---+---+---+
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| D7 D6 D5 D4 D3 D2 D1 D0|
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+---+---+---+---+---+---+---+---+
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Group B
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D0 Port C (lower) 1-Input, 0-Output
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D1 Port B 1-Input, 0-Output
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D2 Mode Selection 0-Mode 0, 1-Mode 1
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Group A
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D3 Port C (upper) 1-Input, 0-Output
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D4 Port A 1-Input, 0-Output
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D5-6 Mode Selection 00-Mode 0, 01-Mode 1, 1X-Mode 2
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D7 Mode Set Flag 1=Active, 0=Bit Set
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Mode 0 - Basic Input/Output
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Mode 1 - Strobed Input/Output
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Mode 2 - Bidirectional Bus
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Bit Set - D7=0, D3:1 select port C bit, D0 1=set, 0=reset
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A read to the data ports gets the current port value, a write
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to the data ports writes the character to the device.
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This program simulates up to 4 i8255 devices. It handles 2 i8255
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devices on the iSBC 80/10 SBC. Other devices could be on other
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multibus boards in the simulated system.
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*/
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#include "system_defs.h" /* system header in system dir */
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#define i8255_NAME "Intel i8255 PIA Chip"
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/* internal function prototypes */
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t_stat i8255_cfg(uint16 base, uint16 devnum, uint8 dummy);
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t_stat i8255_clr(void);
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t_stat i8255_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat i8255_reset (DEVICE *dptr);
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t_stat i8255_reset_dev ();
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uint8 i8255a(t_bool io, uint8 data, uint8 devnum);
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uint8 i8255b(t_bool io, uint8 data, uint8 devnum);
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uint8 i8255c(t_bool io, uint8 data, uint8 devnum);
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uint8 i8255s(t_bool io, uint8 data, uint8 devnum);
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern uint8 unreg_dev(uint16);
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/* globals */
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static const char* i8255_desc(DEVICE *dptr) {
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return i8255_NAME;
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}
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int i8255_num = 0;
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int i8255_baseport[] = { -1, -1, -1, -1 }; //base port
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uint8 i8255_intnum[4] = { 0, 0, 0, 0 }; //interrupt number
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uint8 i8255_verb[4] = { 0, 0, 0, 0 }; //verbose flag
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/* these bytes represent the input and output to/from a port instance */
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uint8 i8255_A[4]; //port A byte I/O
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uint8 i8255_B[4]; //port B byte I/O
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uint8 i8255_C[4]; //port C byte I/O
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/* external globals */
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/* i8255 Standard I/O Data Structures */
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/* up to 4 i8255 devices */
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UNIT i8255_unit[] = {
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{ UDATA (0, 0, 0) }, /* i8255 0 */
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{ UDATA (0, 0, 0) }, /* i8255 1 */
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{ UDATA (0, 0, 0) }, /* i8255 2 */
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{ UDATA (0, 0, 0) } /* i8255 3 */
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};
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REG i8255_reg[] = {
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{ HRDATA (CS0, i8255_unit[0].u3, 8) }, /* i8255 0 */
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{ HRDATA (A0, i8255_A[0], 8) },
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{ HRDATA (B0, i8255_B[0], 8) },
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{ HRDATA (C0, i8255_C[0], 8) },
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{ HRDATA (CS1, i8255_unit[1].u3, 8) }, /* i8255 1 */
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{ HRDATA (A1, i8255_A[1], 8) },
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{ HRDATA (B1, i8255_B[1], 8) },
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{ HRDATA (C1, i8255_C[1], 8) },
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{ HRDATA (CS2, i8255_unit[2].u3, 8) }, /* i8255 2 */
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{ HRDATA (A2, i8255_A[2], 8) },
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{ HRDATA (B2, i8255_B[2], 8) },
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{ HRDATA (C2, i8255_C[2], 8) },
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{ HRDATA (CS3, i8255_unit[3].u3, 8) }, /* i8255 3 */
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{ HRDATA (A3, i8255_A[3], 8) },
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{ HRDATA (B3, i8255_B[3], 8) },
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{ HRDATA (C3, i8255_C[3], 8) },
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{ NULL }
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};
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MTAB i8255_mod[] = {
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// { MTAB_XTD | MTAB_VDV, 0, NULL, "VERB", &isbc202_set_verb,
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// NULL, NULL, "Sets the verbose mode for i8255"},
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// { MTAB_XTD | MTAB_VDV, 0, NULL, "PORT", &isbc202_set_port,
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// NULL, NULL, "Sets the base port for i8255"},
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// { MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &isbc202_set_int,
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// NULL, NULL, "Sets the interrupt number for i8255"},
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i8255_show_param, NULL,
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"show configured parameters for i8255" },
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{ 0 }
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};
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DEBTAB i8255_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE i8255_dev = {
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"I8255", //name
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i8255_unit, //units
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i8255_reg, //registers
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i8255_mod, //modifiers
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I8255_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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i8255_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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i8255_debug, //debflags
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NULL, //msize
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NULL, //lname
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NULL, //help routine
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NULL, //attach help routine
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NULL, //help context
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&i8255_desc //device description
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};
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// i8255 configuration
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t_stat i8255_cfg(uint16 base, uint16 devnum, uint8 dummy)
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{
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DEVICE *dptr;
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dptr = find_dev (i8255_dev.name);
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i8255_baseport[devnum] = base & BYTEMASK;
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sim_printf(" i8255%d: installed at base port 0%02XH\n",
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devnum, i8255_baseport[devnum]);
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reg_dev(i8255a, i8255_baseport[devnum], devnum, 0);
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reg_dev(i8255b, i8255_baseport[devnum] + 1, devnum, 0);
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reg_dev(i8255c, i8255_baseport[devnum] + 2, devnum, 0);
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reg_dev(i8255s, i8255_baseport[devnum] + 3, devnum, 0);
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i8255_num++;
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return SCPE_OK;
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}
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t_stat i8255_clr(void)
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{
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int i;
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for (i=0; i<i8255_num; i++) {
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unreg_dev(i8255_baseport[i]);
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unreg_dev(i8255_baseport[i] + 1);
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unreg_dev(i8255_baseport[i] + 2);
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unreg_dev(i8255_baseport[i] + 3);
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i8255_baseport[i] = -1;
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i8255_intnum[i] = 0;
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i8255_verb[i] = 0;
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}
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i8255_num = 0;
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return SCPE_OK;
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}
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// show configuration parameters
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t_stat i8255_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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int i;
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "Device %s\n", ((i8255_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled");
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for (i=0; i<i8255_num; i++) {
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fprintf(st, "Unit %d at Base port ", i);
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fprintf(st, "0%02X ", i8255_baseport[i]);
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fprintf(st, "Interrupt # is ");
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fprintf(st, "%d ", i8255_intnum[i]);
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fprintf(st, "Mode ");
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fprintf(st, "%s", i8255_verb[i] ? "Verbose" : "Quiet");
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if (i<i8255_num && i8255_num != 1) fprintf(st, "\n");
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}
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat i8255_reset (DEVICE *dptr)
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{
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i8255_reset_dev(); //software reset
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return SCPE_OK;
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}
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t_stat i8255_reset_dev ()
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{
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uint8 devnum;
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for (devnum = 0; devnum < i8255_num+1; devnum++) {
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i8255_unit[devnum].u3 = 0x9B; /* control */
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i8255_A[devnum] = 0xFF; /* Port A */
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i8255_B[devnum] = 0xFF; /* Port B */
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i8255_C[devnum] = 0xFF; /* Port C */
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}
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return SCPE_OK;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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/* i8255 functions */
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uint8 i8255s(t_bool io, uint8 data, uint8 devnum)
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{
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uint8 bit;
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if (io == 0) { /* read status port */
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return 0xFF; //undefined
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} else { /* write status port */
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if (data & 0x80) { /* mode instruction */
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i8255_unit[devnum].u3 = data;
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if (data & 0x64)
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sim_printf(" Mode 1 and 2 not yet implemented\n");
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} else { /* bit set */
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bit = (data & 0x0E) >> 1; /* get bit number */
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if (data & 0x01) { /* set bit */
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i8255_C[devnum] |= (0x01 << bit);
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} else { /* reset bit */
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i8255_C[devnum] &= ~(0x01 << bit);
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}
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}
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}
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return 0;
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}
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uint8 i8255a(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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return (i8255_A[devnum]);
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} else { /* write data port */
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i8255_A[devnum] = data;
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}
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return 0;
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}
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uint8 i8255b(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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return (i8255_B[devnum]);
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} else { /* write data port */
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i8255_B[devnum] = data;
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}
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return 0;
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}
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uint8 i8255c(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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return (i8255_C[devnum]);
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} else { /* write data port */
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if (devnum == 0) {
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if((i8255_C[devnum] & 0x80) != (data & 0x80)) { //change in ROM enable
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if (data & 0x80)
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sim_printf("Onboard EPROM: Enabled\n");
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else
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sim_printf("Onboard EPROM: Disabled\n");
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}
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if((i8255_C[devnum] & 0x20) != (data & 0x20)) { //change in RAM enable
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if (data & 0x20)
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sim_printf("Onboard RAM: Enabled\n");
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else
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sim_printf("Onboard RAM: Disabled\n");
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}
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}
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i8255_C[devnum] = data;
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}
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return 0;
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}
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/* end of i8255.c */
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