dc871fa631
The save/restore format has been updated to improve its reliability. As a result, save files prior to release 3.0 are no longer supported. The text documentation files are obsolete and are no longer included with the distribution. Up-to-date PDF documentation files are available on the SimH web site. 1. New Features 1.1 3.6-0 1.1.1 Most magnetic tapes - Added support for limiting tape capacity to a particular size in MB 1.1.2 IBM 7090/7094 - First release 1.1.3 VAX-11/780 - Added FLOAD command, loads system file from console floppy disk 1.1.4 VAX, VAX-11/780, and PDP-11 - Added card reader support (from John Dundas) 1.1.5 PDP-11 - Added instruction history 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
972 lines
41 KiB
C
972 lines
41 KiB
C
/* nova_cpu.c: NOVA CPU simulator
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Copyright (c) 1993-2006, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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cpu Nova central processor
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06-Feb-06 RMS Fixed bug in DIVS (found by Mark Hittinger)
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22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
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25-Aug-05 RMS Fixed DIVS case 2^31 / - 1
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14-Jan-04 RMS Fixed device enable/disable support (found by Bruce Ray)
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19-Jan-03 RMS Changed CMASK to CDMASK for Apple Dev Kit conflict
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03-Oct-02 RMS Added DIB infrastructure
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30-Dec-01 RMS Added old PC queue
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07-Dec-01 RMS Revised to use breakpoint package
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30-Nov-01 RMS Added extended SET/SHOW support
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10-Aug-01 RMS Removed register in declarations
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17-Jul-01 RMS Moved function prototype
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26-Apr-01 RMS Added device enable/disable support
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05-Mar-01 RMS Added clock calibration
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22-Dec-00 RMS Added Bruce Ray's second terminal
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15-Dec-00 RMS Added Charles Owen's CPU bootstrap
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08-Dec-00 RMS Changes from Bruce Ray
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-- fixed trap test to include Nova 3
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-- fixed DIV and DIVS divide by 0
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-- fixed RETN to set SP from FP
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-- fixed IORST to preserve carry
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-- added "secret" Nova 4 PSHN/SAVEN instructions
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-- added plotter support
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15-Oct-00 RMS Fixed bug in MDV test, added stack, byte, trap instructions
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14-Apr-98 RMS Changed t_addr to unsigned
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15-Sep-97 RMS Added read and write breakpoints
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The register state for the NOVA CPU is:
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AC[0:3]<0:15> general registers
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C carry flag
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PC<0:14> program counter
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The NOVA has three instruction formats: memory reference, I/O transfer,
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and operate. The memory reference format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| 0| op | AC |in| mode| displacement | memory reference
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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<0:4> mnemonic action
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00000 JMP PC = MA
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00001 JMS AC3 = PC, PC = MA
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00010 ISZ M[MA] = M[MA] + 1, skip if M[MA] == 0
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00011 DSZ M[MA] = M[MA] - 1, skip if M[MA] == 0
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001'n LDA ACn = M[MA]
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010'n STA M[MA] = ACn
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<5:7> mode action
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000 page zero direct MA = zext (IR<8:15>)
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001 PC relative direct MA = PC + sext (IR<8:15>)
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010 AC2 relative direct MA = AC2 + sext (IR<8:15>)
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011 AC3 relative direct MA = AC3 + sext (IR<8:15>)
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100 page zero indirect MA = M[zext (IR<8:15>)]
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101 PC relative indirect MA = M[PC + sext (IR<8:15>)]
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110 AC2 relative indirect MA = M[AC2 + sext (IR<8:15>)]
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111 AC3 relative indirect MA = M[AC3 + sext (IR<8:15>)]
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Memory reference instructions can access an address space of 32K words.
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An instruction can directly reference the first 256 words of memory
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(called page zero), as well as 256 words relative to the PC, AC2, or
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AC3; it can indirectly access all 32K words. If an indirect address
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is in locations 00020-00027, the indirect address is incremented and
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rewritten to memory before use; if in 00030-00037, decremented and
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rewritten.
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The I/O transfer format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| 0 1 1| AC | opcode |pulse| device | I/O transfer
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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The IOT instruction sends the opcode, pulse, and specified AC to the
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specified I/O device. The device may accept data, provide data,
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initiate or cancel operations, or skip on status.
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The operate format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1|srcAC|dstAC| opcode |shift|carry|nl| skip | operate
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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\______/ \___/ \___/ | | | |
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| | | | | | +--- reverse skip sense
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| | | | | +--- skip if C == 0
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| | | | +--- skip if result == 0
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| | | +--- don't load result
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| | +--- carry in (load as is,
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| | set to Zero,
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| | set to One,
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| | load Complement)
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| +--- shift (none,
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| left one,
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| right one,
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| byte swap)
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+--- operation (complement,
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negate,
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move,
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increment,
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add complement,
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subtract,
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add,
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and)
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The operate instruction can be microprogrammed to perform operations
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on the source and destination AC's and the Carry flag.
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Some notes from Bruce Ray:
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1. DG uses the value of the autoindex location -before- the
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modification to determine if additional indirect address
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levels are to be performed. Most DG emulators conform to
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this standard, but some vendor machines (i.e. Point 4 Mark 8)
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do not.
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2. Infinite indirect references may occur on unmapped systems
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and can "hang" the hardware. Some DG diagnostics perform
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10,000s of references during a single instruction.
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3. Nova 3 adds the following instructions to the standard Nova
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instruction set:
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trap instructions
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stack push/pop instructions
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save/return instructions
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stack register manipulation instructions
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unsigned MUL/DIV
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4. Nova 4 adds the following instructions to the Nova 3 instruction
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set:
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signed MUL/DIV
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load/store byte
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secret (undocumented) stack instructions [PSHN, SAVN]
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5. Nova, Nova 3 and Nova 4 unsigned mul/div instructions are the
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same instruction code values on all machines.
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This routine is the instruction decode routine for the NOVA.
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It is called from the simulator control program to execute
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instructions in simulated memory, starting at the simulated PC.
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It runs until 'reason' is set non-zero.
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General notes:
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1. Reasons to stop. The simulator can be stopped by:
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HALT instruction
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breakpoint encountered
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infinite indirection loop
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unknown I/O device and STOP_DEV flag set
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I/O error in I/O simulator
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2. Interrupts. Interrupts are maintained by four parallel variables:
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dev_done device done flags
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dev_disable device interrupt disable flags
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dev_busy device busy flags
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int_req interrupt requests
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In addition, int_req contains the interrupt enable and ION pending
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flags. If ION and ION pending are set, and at least one interrupt
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request is pending, then an interrupt occurs. Note that the 16b PIO
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mask must be mapped to the simulator's device bit mapping.
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3. Non-existent memory. On the NOVA, reads to non-existent memory
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return zero, and writes are ignored. In the simulator, the
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largest possible memory is instantiated and initialized to zero.
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Thus, only writes need be checked against actual memory size.
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4. Adding I/O devices. These modules must be modified:
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nova_defs.h add interrupt request definition
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nova_sys.c add sim_devices entry
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*/
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#include "nova_defs.h"
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#define PCQ_SIZE 64 /* must be 2**n */
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
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#define INCA(x) (((x) + 1) & AMASK)
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#define DECA(x) (((x) - 1) & AMASK)
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#define SEXT(x) (((x) & SIGN)? ((x) | ~DMASK): (x))
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#define STK_CHECK(x,y) if (((x) & 0377) < (y)) int_req = int_req | INT_STK
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#define IND_STEP(x) M[x] & A_IND; \
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if (((x) & 077770) == AUTO_INC) \
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M[x] = (M[x] + 1) & 0177777; \
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else if (((x) & 077770) == AUTO_DEC) \
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M[x] = (M[x] - 1) & 0177777; \
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x = M[x] & AMASK
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#define UNIT_V_MDV (UNIT_V_UF + 0) /* MDV present */
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#define UNIT_V_STK (UNIT_V_UF + 1) /* stack instr */
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#define UNIT_V_BYT (UNIT_V_UF + 2) /* byte instr */
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#define UNIT_V_MSIZE (UNIT_V_UF + 3) /* dummy mask */
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#define UNIT_MDV (1 << UNIT_V_MDV)
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#define UNIT_STK (1 << UNIT_V_STK)
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#define UNIT_BYT (1 << UNIT_V_BYT)
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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#define UNIT_IOPT (UNIT_MDV | UNIT_STK | UNIT_BYT)
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#define UNIT_NOVA3 (UNIT_MDV | UNIT_STK)
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#define UNIT_NOVA4 (UNIT_MDV | UNIT_STK | UNIT_BYT)
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uint16 M[MAXMEMSIZE] = { 0 }; /* memory */
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int32 AC[4] = { 0 }; /* accumulators */
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int32 C = 0; /* carry flag */
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int32 saved_PC = 0; /* program counter */
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int32 SP = 0; /* stack pointer */
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int32 FP = 0; /* frame pointer */
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int32 SR = 0; /* switch register */
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int32 dev_done = 0; /* device done flags */
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int32 dev_busy = 0; /* device busy flags */
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int32 dev_disable = 0; /* int disable flags */
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int32 int_req = 0; /* interrupt requests */
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int32 pimask = 0; /* priority int mask */
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int32 pwr_low = 0; /* power fail flag */
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int32 ind_max = 16; /* iadr nest limit */
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int32 stop_dev = 0; /* stop on ill dev */
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uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
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int32 pcq_p = 0; /* PC queue ptr */
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REG *pcq_r = NULL; /* PC queue reg ptr */
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struct ndev dev_table[64]; /* dispatch table */
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extern int32 sim_int_char;
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extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
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extern DEVICE *sim_devices[];
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t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_boot (int32 unitno, DEVICE *dptr);
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t_stat build_devtab (void);
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/* CPU data structures
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cpu_dev CPU device descriptor
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cpu_unit CPU unit descriptor
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cpu_reg CPU register list
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cpu_mod CPU modifiers list
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*/
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UNIT cpu_unit = {
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UDATA (NULL, UNIT_FIX+UNIT_BINK+UNIT_MDV, MAXMEMSIZE)
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};
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REG cpu_reg[] = {
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{ ORDATA (PC, saved_PC, 15) },
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{ ORDATA (AC0, AC[0], 16) },
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{ ORDATA (AC1, AC[1], 16) },
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{ ORDATA (AC2, AC[2], 16) },
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{ ORDATA (AC3, AC[3], 16) },
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{ FLDATA (C, C, 16) },
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{ ORDATA (SP, SP, 16) },
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{ ORDATA (FP, FP, 16) },
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{ ORDATA (SR, SR, 16) },
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{ ORDATA (PI, pimask, 16) },
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{ FLDATA (ION, int_req, INT_V_ION) },
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{ FLDATA (ION_DELAY, int_req, INT_V_NO_ION_PENDING) },
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{ FLDATA (STKOVF, int_req, INT_V_STK) },
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{ FLDATA (PWR, pwr_low, 0) },
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{ ORDATA (INT, int_req, INT_V_ION+1), REG_RO },
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{ ORDATA (BUSY, dev_busy, INT_V_ION+1), REG_RO },
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{ ORDATA (DONE, dev_done, INT_V_ION+1), REG_RO },
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{ ORDATA (DISABLE, dev_disable, INT_V_ION+1), REG_RO },
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{ FLDATA (STOP_DEV, stop_dev, 0) },
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{ DRDATA (INDMAX, ind_max, 16), REG_NZ + PV_LEFT },
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{ BRDATA (PCQ, pcq, 8, 16, PCQ_SIZE), REG_RO+REG_CIRC },
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{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
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{ ORDATA (WRU, sim_int_char, 8) },
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{ NULL }
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};
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MTAB cpu_mod[] = {
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{ UNIT_IOPT, UNIT_NOVA3, "NOVA3", "NOVA3", NULL },
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{ UNIT_IOPT, UNIT_NOVA4, "NOVA4", "NOVA4", NULL },
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{ UNIT_IOPT, UNIT_MDV, "MDV", "MDV", NULL },
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{ UNIT_IOPT, 0, "none", "NONE", NULL },
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{ UNIT_MSIZE, 4096, NULL, "4K", &cpu_set_size },
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{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size },
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{ UNIT_MSIZE, 12288, NULL, "12K", &cpu_set_size },
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{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size },
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{ UNIT_MSIZE, 20480, NULL, "20K", &cpu_set_size },
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{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size },
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{ UNIT_MSIZE, 28672, NULL, "28K", &cpu_set_size },
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{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size },
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{ 0 }
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};
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DEVICE cpu_dev = {
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"CPU", &cpu_unit, cpu_reg, cpu_mod,
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1, 8, 15, 1, 8, 16,
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&cpu_ex, &cpu_dep, &cpu_reset,
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NULL, NULL, NULL
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};
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t_stat sim_instr (void)
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{
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extern int32 sim_interval;
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int32 PC, IR, i;
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t_stat reason;
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void mask_out (int32 mask);
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extern int32 clk_sel, clk_time[4];
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/* Restore register state */
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if (build_devtab () != SCPE_OK) return SCPE_IERR; /* build dispatch */
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PC = saved_PC & AMASK; /* load local PC */
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C = C & CBIT;
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mask_out (pimask); /* reset int system */
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reason = 0;
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sim_rtc_init (clk_time[clk_sel]); /* init calibration */
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/* Main instruction fetch/decode loop */
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while (reason == 0) { /* loop until halted */
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if (sim_interval <= 0) { /* check clock queue */
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if (reason = sim_process_event ()) break;
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}
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if (int_req > INT_PENDING) { /* interrupt? */
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int32 MA, indf;
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int_req = int_req & ~INT_ION; /* intr off */
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PCQ_ENTRY; /* save old PC */
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M[INT_SAV] = PC;
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if (int_req & INT_STK) { /* stack overflow? */
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int_req = int_req & ~INT_STK; /* clear */
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MA = STK_JMP; /* jmp @3 */
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}
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else MA = INT_JMP; /* intr: jmp @1 */
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for (i = 0, indf = 1; indf && (i < ind_max); i++) {
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indf = IND_STEP (MA); /* indirect loop */
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}
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if (i >= ind_max) {
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reason = STOP_IND_INT;
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break;
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}
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PC = MA;
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} /* end interrupt */
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if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
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reason = STOP_IBKPT; /* stop simulation */
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break;
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}
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IR = M[PC]; /* fetch instr */
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PC = (PC + 1) & AMASK;
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int_req = int_req | INT_NO_ION_PENDING; /* clear ION delay */
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sim_interval = sim_interval - 1;
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/* Operate instruction */
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if (IR & I_OPR) { /* operate? */
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int32 src, srcAC, dstAC;
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srcAC = I_GETSRC (IR); /* get reg decodes */
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dstAC = I_GETDST (IR);
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switch (I_GETCRY (IR)) { /* decode carry */
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case 0: /* load */
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src = AC[srcAC] | C;
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break;
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case 1: /* clear */
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src = AC[srcAC];
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break;
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case 2: /* set */
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src = AC[srcAC] | CBIT;
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break;
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case 3: /* complement */
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src = AC[srcAC] | (C ^ CBIT);
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break;
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} /* end switch carry */
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switch (I_GETALU (IR)) { /* decode ALU */
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case 0: /* COM */
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src = src ^ DMASK;
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break;
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case 1: /* NEG */
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src = ((src ^ DMASK) + 1) & CDMASK;
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break;
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case 2: /* MOV */
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break;
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case 3: /* INC */
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src = (src + 1) & CDMASK;
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break;
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case 4: /* ADC */
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src = ((src ^ DMASK) + AC[dstAC]) & CDMASK;
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break;
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case 5: /* SUB */
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src = ((src ^ DMASK) + AC[dstAC] + 1) & CDMASK;
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break;
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case 6: /* ADD */
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src = (src + AC[dstAC]) & CDMASK;
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break;
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case 7: /* AND */
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src = src & (AC[dstAC] | CBIT);
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break;
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} /* end switch oper */
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switch (I_GETSHF (IR)) { /* decode shift */
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case 0: /* nop */
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break;
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case 1: /* L */
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|
src = ((src << 1) | (src >> 16)) & CDMASK;
|
|
break;
|
|
case 2: /* R */
|
|
src = ((src >> 1) | (src << 16)) & CDMASK;
|
|
break;
|
|
case 3: /* S */
|
|
src = ((src & 0377) << 8) | ((src >> 8) & 0377) |
|
|
(src & CBIT);
|
|
break;
|
|
} /* end switch shift */
|
|
|
|
switch (I_GETSKP (IR)) { /* decode skip */
|
|
case 0: /* nop */
|
|
if ((IR & I_NLD) && (cpu_unit.flags & UNIT_STK)) {
|
|
int32 indf, MA; /* Nova 3 or 4 trap */
|
|
PCQ_ENTRY; /* save old PC */
|
|
M[TRP_SAV] = (PC - 1) & AMASK;
|
|
MA = TRP_JMP; /* jmp @47 */
|
|
for (i = 0, indf = 1; indf && (i < ind_max); i++) {
|
|
indf = IND_STEP (MA); /* resolve ind */
|
|
}
|
|
if (i >= ind_max) { /* indirect loop? */
|
|
reason = STOP_IND_TRP;
|
|
break;
|
|
}
|
|
PC = MA; /* new PC */
|
|
}
|
|
break;
|
|
case 1: /* SKP */
|
|
PC = (PC + 1) & AMASK;
|
|
break;
|
|
case 2: /* SZC */
|
|
if (src < CBIT) PC = (PC + 1) & AMASK;
|
|
break;
|
|
case 3: /* SNC */
|
|
if (src >= CBIT) PC = (PC + 1) & AMASK;
|
|
break;
|
|
case 4: /* SZR */
|
|
if ((src & DMASK) == 0) PC = (PC + 1) & AMASK;
|
|
break;
|
|
case 5: /* SNR */
|
|
if ((src & DMASK) != 0) PC = (PC + 1) & AMASK;
|
|
break;
|
|
case 6: /* SEZ */
|
|
if (src <= CBIT) PC = (PC + 1) & AMASK;
|
|
break;
|
|
case 7: /* SBN */
|
|
if (src > CBIT) PC = (PC + 1) & AMASK;
|
|
break;
|
|
} /* end switch skip */
|
|
if ((IR & I_NLD) == 0) { /* load? */
|
|
AC[dstAC] = src & DMASK;
|
|
C = src & CBIT;
|
|
} /* end if load */
|
|
} /* end if operate */
|
|
|
|
/* Memory reference instructions */
|
|
|
|
else if (IR < 060000) { /* mem ref? */
|
|
int32 src, MA, indf;
|
|
|
|
MA = I_GETDISP (IR); /* get disp */
|
|
switch (I_GETMODE (IR)) { /* decode mode */
|
|
case 0: /* page zero */
|
|
break;
|
|
case 1: /* PC relative */
|
|
if (MA & DISPSIGN) MA = 077400 | MA;
|
|
MA = (MA + PC - 1) & AMASK;
|
|
break;
|
|
case 2: /* AC2 relative */
|
|
if (MA & DISPSIGN) MA = 077400 | MA;
|
|
MA = (MA + AC[2]) & AMASK;
|
|
break;
|
|
case 3: /* AC3 relative */
|
|
if (MA & DISPSIGN) MA = 077400 | MA;
|
|
MA = (MA + AC[3]) & AMASK;
|
|
break;
|
|
} /* end switch mode */
|
|
|
|
if (indf = IR & I_IND) { /* indirect? */
|
|
for (i = 0; indf && (i < ind_max); i++) { /* count */
|
|
indf = IND_STEP (MA); /* resolve indirect */
|
|
}
|
|
if (i >= ind_max) { /* too many? */
|
|
reason = STOP_IND;
|
|
break;
|
|
}
|
|
}
|
|
|
|
switch (I_GETOPAC (IR)) { /* decode op + AC */
|
|
case 001: /* JSR */
|
|
AC[3] = PC;
|
|
case 000: /* JMP */
|
|
PCQ_ENTRY;
|
|
PC = MA;
|
|
break;
|
|
case 002: /* ISZ */
|
|
src = (M[MA] + 1) & DMASK;
|
|
if (MEM_ADDR_OK (MA)) M[MA] = src;
|
|
if (src == 0) PC = (PC + 1) & AMASK;
|
|
break;
|
|
case 003: /* DSZ */
|
|
src = (M[MA] - 1) & DMASK;
|
|
if (MEM_ADDR_OK (MA)) M[MA] = src;
|
|
if (src == 0) PC = (PC + 1) & AMASK;
|
|
break;
|
|
case 004: /* LDA 0 */
|
|
AC[0] = M[MA];
|
|
break;
|
|
case 005: /* LDA 1 */
|
|
AC[1] = M[MA];
|
|
break;
|
|
case 006: /* LDA 2 */
|
|
AC[2] = M[MA];
|
|
break;
|
|
case 007: /* LDA 3 */
|
|
AC[3] = M[MA];
|
|
break;
|
|
case 010: /* STA 0 */
|
|
if (MEM_ADDR_OK (MA)) M[MA] = AC[0];
|
|
break;
|
|
case 011: /* STA 1 */
|
|
if (MEM_ADDR_OK (MA)) M[MA] = AC[1];
|
|
break;
|
|
case 012: /* STA 2 */
|
|
if (MEM_ADDR_OK (MA)) M[MA] = AC[2];
|
|
break;
|
|
case 013: /* STA 3 */
|
|
if (MEM_ADDR_OK (MA)) M[MA] = AC[3];
|
|
break;
|
|
} /* end switch */
|
|
} /* end mem ref */
|
|
|
|
/* IOT instruction */
|
|
|
|
else { /* IOT */
|
|
int32 dstAC, pulse, code, device, iodata;
|
|
|
|
dstAC = I_GETDST (IR); /* decode fields */
|
|
code = I_GETIOT (IR);
|
|
pulse = I_GETPULSE (IR);
|
|
device = I_GETDEV (IR);
|
|
if (code == ioSKP) { /* IO skip? */
|
|
switch (pulse) { /* decode IR<8:9> */
|
|
|
|
case 0: /* skip if busy */
|
|
if ((device == DEV_CPU)? (int_req & INT_ION) != 0:
|
|
(dev_busy & dev_table[device].mask) != 0)
|
|
PC = (PC + 1) & AMASK;
|
|
break;
|
|
|
|
case 1: /* skip if not busy */
|
|
if ((device == DEV_CPU)? (int_req & INT_ION) == 0:
|
|
(dev_busy & dev_table[device].mask) == 0)
|
|
PC = (PC + 1) & AMASK;
|
|
break;
|
|
|
|
case 2: /* skip if done */
|
|
if ((device == DEV_CPU)? pwr_low != 0:
|
|
(dev_done & dev_table[device].mask) != 0)
|
|
PC = (PC + 1) & AMASK;
|
|
break;
|
|
|
|
case 3: /* skip if not done */
|
|
if ((device == DEV_CPU)? pwr_low == 0:
|
|
(dev_done & dev_table[device].mask) == 0)
|
|
PC = (PC + 1) & AMASK;
|
|
break;
|
|
} /* end switch */
|
|
} /* end IO skip */
|
|
|
|
else if (device == DEV_MDV) {
|
|
switch (code) { /* case on opcode */
|
|
|
|
case ioNIO: /* frame ptr */
|
|
if (cpu_unit.flags & UNIT_STK) {
|
|
if (pulse == iopN) FP = AC[dstAC] & AMASK;
|
|
if (pulse == iopC) AC[dstAC] = FP;
|
|
}
|
|
break;
|
|
|
|
case ioDIA: /* load byte */
|
|
if (cpu_unit.flags & UNIT_BYT)
|
|
AC[dstAC] = (M[AC[pulse] >> 1] >>
|
|
((AC[pulse] & 1)? 0: 8)) & 0377;
|
|
else AC[dstAC] = 0;
|
|
break;
|
|
|
|
case ioDOA: /* stack ptr */
|
|
if (cpu_unit.flags & UNIT_STK) {
|
|
if (pulse == iopN) SP = AC[dstAC] & AMASK;
|
|
if (pulse == iopC) AC[dstAC] = SP;
|
|
}
|
|
break;
|
|
|
|
case ioDIB: /* push, pop */
|
|
if (cpu_unit.flags & UNIT_STK) {
|
|
if (pulse == iopN) { /* push */
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = AC[dstAC];
|
|
STK_CHECK (SP, 1);
|
|
}
|
|
if (pulse == iopC) { /* pop */
|
|
AC[dstAC] = M[SP];
|
|
SP = DECA (SP);
|
|
}
|
|
if ((pulse == iopP) && /* Nova 4 pshn */
|
|
(cpu_unit.flags & UNIT_BYT)) {
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = AC[dstAC];
|
|
if (SP > M[042]) int_req = int_req | INT_STK ;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case ioDOB: /* store byte */
|
|
if (cpu_unit.flags & UNIT_BYT) {
|
|
int32 MA, val;
|
|
MA = AC[pulse] >> 1;
|
|
val = AC[dstAC] & 0377;
|
|
if (MEM_ADDR_OK (MA)) M[MA] = (AC[pulse] & 1)?
|
|
((M[MA] & ~0377) | val):
|
|
((M[MA] & 0377) | (val << 8));
|
|
}
|
|
break;
|
|
|
|
case ioDIC: /* save, return */
|
|
if (cpu_unit.flags & UNIT_STK) {
|
|
if (pulse == iopN) { /* save */
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = AC[0];
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = AC[1];
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = AC[2];
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = FP;
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = (C >> 1) |
|
|
(AC[3] & AMASK);
|
|
AC[3] = FP = SP & AMASK;
|
|
STK_CHECK (SP, 5);
|
|
}
|
|
if (pulse == iopC) { /* retn */
|
|
PCQ_ENTRY;
|
|
SP = FP & AMASK;
|
|
C = (M[SP] << 1) & CBIT;
|
|
PC = M[SP] & AMASK;
|
|
SP = DECA (SP);
|
|
AC[3] = M[SP];
|
|
SP = DECA (SP);
|
|
AC[2] = M[SP];
|
|
SP = DECA (SP);
|
|
AC[1] = M[SP];
|
|
SP = DECA (SP);
|
|
AC[0] = M[SP];
|
|
SP = DECA (SP);
|
|
FP = AC[3] & AMASK;
|
|
}
|
|
if ((pulse == iopP) && /* Nova 4 saven */
|
|
(cpu_unit.flags & UNIT_BYT)) {
|
|
int32 frameSz = M[PC] ;
|
|
PC = INCA (PC) ;
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = AC[0];
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = AC[1];
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = AC[2];
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = FP;
|
|
SP = INCA (SP);
|
|
if (MEM_ADDR_OK (SP)) M[SP] = (C >> 1) |
|
|
(AC[3] & AMASK);
|
|
AC[3] = FP = SP & AMASK ;
|
|
SP = (SP + frameSz) & AMASK ;
|
|
if (SP > M[042]) int_req = int_req | INT_STK;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case ioDOC:
|
|
if ((dstAC == 2) && (cpu_unit.flags & UNIT_MDV)) {
|
|
uint32 mddata, uAC0, uAC1, uAC2;
|
|
uAC0 = (uint32) AC[0];
|
|
uAC1 = (uint32) AC[1];
|
|
uAC2 = (uint32) AC[2];
|
|
if (pulse == iopP) { /* mul */
|
|
mddata = (uAC1 * uAC2) + uAC0;
|
|
AC[0] = (mddata >> 16) & DMASK;
|
|
AC[1] = mddata & DMASK;
|
|
}
|
|
if (pulse == iopS) { /* div */
|
|
if ((uAC0 >= uAC2) || (uAC2 == 0)) C = CBIT;
|
|
else {
|
|
C = 0;
|
|
mddata = (uAC0 << 16) | uAC1;
|
|
AC[1] = mddata / uAC2;
|
|
AC[0] = mddata % uAC2;
|
|
}
|
|
}
|
|
}
|
|
if ((dstAC == 3) && (cpu_unit.flags & UNIT_BYT)) {
|
|
int32 mddata;
|
|
if (pulse == iopC) { /* muls */
|
|
mddata = (SEXT (AC[1]) * SEXT (AC[2])) + SEXT (AC[0]);
|
|
AC[0] = (mddata >> 16) & DMASK;
|
|
AC[1] = mddata & DMASK;
|
|
}
|
|
if (pulse == iopN) { /* divs */
|
|
if ((AC[2] == 0) || /* overflow? */
|
|
((AC[0] == 0100000) && (AC[1] == 0) && (AC[2] == 0177777)))
|
|
C = CBIT;
|
|
else {
|
|
mddata = (SEXT (AC[0]) << 16) | AC[1];
|
|
AC[1] = mddata / SEXT (AC[2]);
|
|
AC[0] = mddata % SEXT (AC[2]);
|
|
if ((AC[1] > 077777) || (AC[1] < -0100000))
|
|
C = CBIT;
|
|
else C = 0;
|
|
AC[0] = AC[0] & DMASK;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
} /* end case code */
|
|
} /* end if mul/div */
|
|
|
|
else if (device == DEV_CPU) { /* CPU control */
|
|
switch (code) { /* decode IR<5:7> */
|
|
|
|
case ioDIA: /* read switches */
|
|
AC[dstAC] = SR;
|
|
break;
|
|
|
|
case ioDIB: /* int ack */
|
|
AC[dstAC] = 0;
|
|
int_req = (int_req & ~INT_DEV) | (dev_done & ~dev_disable);
|
|
iodata = int_req & (-int_req);
|
|
for (i = DEV_LOW; i <= DEV_HIGH; i++) {
|
|
if (iodata & dev_table[i].mask) {
|
|
AC[dstAC] = i;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case ioDOB: /* mask out */
|
|
mask_out (pimask = AC[dstAC]);
|
|
break;
|
|
|
|
case ioDIC: /* io reset */
|
|
reset_all (0); /* reset devices */
|
|
break;
|
|
|
|
case ioDOC: /* halt */
|
|
reason = STOP_HALT;
|
|
break;
|
|
} /* end switch code */
|
|
|
|
switch (pulse) { /* decode IR<8:9> */
|
|
|
|
case iopS: /* ion */
|
|
int_req = (int_req | INT_ION) & ~INT_NO_ION_PENDING;
|
|
break;
|
|
|
|
case iopC: /* iof */
|
|
int_req = int_req & ~INT_ION;
|
|
break;
|
|
} /* end switch pulse */
|
|
} /* end CPU control */
|
|
|
|
else if (dev_table[device].routine) { /* normal device */
|
|
iodata = dev_table[device].routine (pulse, code, AC[dstAC]);
|
|
reason = iodata >> IOT_V_REASON;
|
|
if (code & 1) AC[dstAC] = iodata & 0177777;
|
|
}
|
|
else reason = stop_dev;
|
|
} /* end if IOT */
|
|
} /* end while */
|
|
|
|
/* Simulation halted */
|
|
|
|
saved_PC = PC;
|
|
pcq_r->qptr = pcq_p; /* update pc q ptr */
|
|
return reason;
|
|
}
|
|
|
|
/* New priority mask out */
|
|
|
|
void mask_out (int32 newmask)
|
|
{
|
|
int32 i;
|
|
|
|
dev_disable = 0;
|
|
for (i = DEV_LOW; i <= DEV_HIGH; i++) {
|
|
if (newmask & dev_table[i].pi)
|
|
dev_disable = dev_disable | dev_table[i].mask;
|
|
}
|
|
int_req = (int_req & ~INT_DEV) | (dev_done & ~dev_disable);
|
|
return;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat cpu_reset (DEVICE *dptr)
|
|
{
|
|
int_req = int_req & ~(INT_ION | INT_STK);
|
|
pimask = 0;
|
|
dev_disable = 0;
|
|
pwr_low = 0;
|
|
pcq_r = find_reg ("PCQ", NULL, dptr);
|
|
if (pcq_r) pcq_r->qptr = 0;
|
|
else return SCPE_IERR;
|
|
sim_brk_types = sim_brk_dflt = SWMASK ('E');
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Memory examine */
|
|
|
|
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
if (addr >= MEMSIZE) return SCPE_NXM;
|
|
if (vptr != NULL) *vptr = M[addr] & DMASK;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Memory deposit */
|
|
|
|
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
if (addr >= MEMSIZE) return SCPE_NXM;
|
|
M[addr] = val & DMASK;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Alter memory size */
|
|
|
|
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
int32 mc = 0;
|
|
t_addr i;
|
|
|
|
if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0))
|
|
return SCPE_ARG;
|
|
for (i = val; i < MEMSIZE; i++) mc = mc | M[i];
|
|
if ((mc != 0) && (!get_yn ("Really truncate memory [N]?", FALSE)))
|
|
return SCPE_OK;
|
|
MEMSIZE = val;
|
|
for (i = MEMSIZE; i < MAXMEMSIZE; i++) M[i] = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Build dispatch table */
|
|
|
|
t_stat build_devtab (void)
|
|
{
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
int32 i, dn;
|
|
|
|
for (i = 0; i < 64; i++) { /* clr dev_table */
|
|
dev_table[i].mask = 0;
|
|
dev_table[i].pi = 0;
|
|
dev_table[i].routine = NULL;
|
|
}
|
|
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
|
if (!(dptr->flags & DEV_DIS) && /* enabled and */
|
|
(dibp = (DIB *) dptr->ctxt)) { /* defined DIB? */
|
|
dn = dibp->dnum; /* get dev num */
|
|
dev_table[dn].mask = dibp->mask; /* copy entries */
|
|
dev_table[dn].pi = dibp->pi;
|
|
dev_table[dn].routine = dibp->routine;
|
|
}
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Bootstrap routine for CPU */
|
|
|
|
#define BOOT_START 00000
|
|
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int))
|
|
|
|
static const int32 boot_rom[] = {
|
|
0062677, /* IORST ;reset all I/O */
|
|
0060477, /* READS 0 ;read SR into AC0 */
|
|
0024026, /* LDA 1,C77 ;get dev mask */
|
|
0107400, /* AND 0,1 ;isolate dev code */
|
|
0124000, /* COM 1,1 ;- device code - 1 */
|
|
0010014, /* LOOP: ISZ OP1 ;device code to all */
|
|
0010030, /* ISZ OP2 ;I/O instructions */
|
|
0010032, /* ISZ OP3 */
|
|
0125404, /* INC 1,1,SZR ;done? */
|
|
0000005, /* JMP LOOP ;no, increment again */
|
|
0030016, /* LDA 2,C377 ;place JMP 377 into */
|
|
0050377, /* STA 2,377 ;location 377 */
|
|
0060077, /* OP1: 060077 ;start device (NIOS 0) */
|
|
00101102, /* MOVL 0,0,SZC ;test switch 0, low speed? */
|
|
0000377, /* C377: JMP 377 ;no - jmp 377 & wait */
|
|
0004030, /* LOOP2: JSR GET+1 ;get a frame */
|
|
0101065, /* MOVC 0,0,SNR ;is it non-zero? */
|
|
0000017, /* JMP LOOP2 ;no, ignore */
|
|
0004027, /* LOOP4: JSR GET ;yes, get full word */
|
|
0046026, /* STA 1,@C77 ;store starting at 100 */
|
|
/* ;2's complement of word ct */
|
|
0010100, /* ISZ 100 ;done? */
|
|
0000022, /* JMP LOOP4 ;no, get another */
|
|
0000077, /* C77: JMP 77 ;yes location ctr and */
|
|
/* ;jmp to last word */
|
|
0126420, /* GET: SUBZ 1,1 ; clr AC1, set carry */
|
|
/* OP2: */
|
|
0063577, /* LOOP3: 063577 ;done? (SKPDN 0) - 1 */
|
|
0000030, /* JMP LOOP3 ;no -- wait */
|
|
0060477, /* OP3: 060477 ;y -- read in ac0 (DIAS 0,0) */
|
|
0107363, /* ADDCS 0,1,SNC ;add 2 frames swapped - got 2nd? */
|
|
0000030, /* JMP LOOP3 ;no go back after it */
|
|
0125300, /* MOVS 1,1 ;yes swap them */
|
|
0001400, /* JMP 0,3 ;rtn with full word */
|
|
0000000 /* 0 ;padding */
|
|
};
|
|
|
|
t_stat cpu_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
int32 i;
|
|
extern int32 saved_PC;
|
|
|
|
for (i = 0; i < BOOT_LEN; i++) M[BOOT_START + i] = boot_rom[i];
|
|
saved_PC = BOOT_START;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* 1-to-1 map for I/O devices */
|
|
|
|
int32 MapAddr (int32 map, int32 addr)
|
|
{
|
|
return addr;
|
|
}
|