df6475181c
1. New Features 1.1 GRI-909 - This is a new simulator for the GRI-909. - It has been hand-tested; so far, no software has been discovered. 1.2 VAX - SET CPU CONHALT will cause a HALT instruction to return to the boot ROM console rather than to SIMH. SET CPU SIMHALT restores the default behavior. - BRB/W self at IPL 1F stops the simulator. This is the default behavior of VMS at exit. 1.3 PDP-18b - ATTACH -A PTR/PTP attaches the reader and punch in ASCII mode. In ASCII mode, the reader automatically sets the high order bit of incoming alphabetic data, and the punch clears the high order bit of outgoing data. 1.4 SCP - DO -V echoes commands from the file as they are executed. - Under Windows, execution priority is set BELOW_NORMAL when the simulator is running. 2. Release Notes 2.1 Bugs Fixed - PDP-11 CPU: fixed updating of MMR0 on a memory management error. - VAX FPA: changed function names to avoid conflict with C math library. - 1401 MT: read end of record generates group mark without word mark. - 1401 DP: fixed address generation and checking. - SCP: an EXIT within a DO command will cause the simulator to exit. 3. In Progress - Interdata 16b/32b: coded, not tested. - SDS 940: coded, not tested. - IBM 1620: coded, not tested. If you would like to help with the debugging of the untested simulators, they can be made available by special request.
296 lines
10 KiB
C
296 lines
10 KiB
C
/* hp2100_fp.c: HP 2100 floating point instructions
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Copyright (c) 2002, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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The HP2100 uses a unique binary floating point format:
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15 14 0
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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|S | fraction high | : A
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| fraction low | exponent |XS| : A + 1
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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15 8 7 1 0
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where S = 0 for plus fraction, 1 for minus fraction
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fraction = s.bbbbb..., 24 binary digits
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exponent = 2**+/-n
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XS = 0 for plus exponent, 1 for minus exponent
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Numbers can be normalized or unnormalized but are always normalized
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when loaded.
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Unpacked floating point numbers are stored in structure ufp
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sign = fraction sign, 0 = +, 1 = -
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exp = exponent, 2's complement
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h'l = fraction, 2's comp, with 1 high guard bit
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Questions:
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1. Are fraction and exponent magnitude or 2's complement? 2's complement
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2. Do operations round? yes, with IEEE like standards (sticky bits)
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*/
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#include "hp2100_defs.h"
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struct ufp { /* unpacked fp */
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int32 sign; /* sign */
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int32 exp; /* exp */
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uint32 h; /* frac */
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uint32 l; };
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#define FP_V_SIGN 31 /* sign */
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#define FP_M_SIGN 01
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#define FP_GETSIGN(x) (((x) >> FP_V_SIGN) & FP_M_SIGN)
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#define FP_V_FRH 8 /* fraction */
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#define FP_M_FRH 077777777
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#define FP_FRH (FP_M_FRH << FP_V_FRH)
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#define FP_V_EXP 1 /* exponent */
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#define FP_M_EXP 0177
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#define FP_GETEXP(x) (((x) >> FP_V_EXP) & FP_M_EXP)
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#define FP_V_EXPS 0 /* exp sign */
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#define FP_M_EXPS 01
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#define FP_GETEXPS(x) (((x) >> FP_V_EXPS) & FP_M_EXPS)
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#define UFP_GUARD 1 /* 1 extra left */
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#define UFP_V_SIGN (FP_V_SIGN - UFP_GUARD) /* sign */
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#define UFP_SIGN (1 << UFP_V_SIGN)
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#define UFP_CRY (1 << (UFP_V_SIGN + 1)) /* carry */
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#define UFP_NORM (1 << (UFP_V_SIGN - 1)) /* normalized */
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#define UFP_V_LOW (FP_V_FRH - UFP_GUARD) /* low bit */
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#define UFP_LOW (1 << UFP_V_LOW)
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#define UFP_RND (1 << (UFP_V_LOW - 1)) /* round */
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#define UFP_STKY (UFP_RND - 1) /* sticky bits */
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#define FPAB ((((uint32) AR) << 16) | ((uint32) BR))
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#define HFMASK 0x7FFFFFFF /* hi frac mask */
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#define LFMASK 0xFFFFFFFF /* lo frac mask */
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/* Fraction shift; 0 < shift < 32 */
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#define FR_ARSH(v,s) v.l = ((v.l >> (s)) | \
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(v.h << (32 - (s)))) & LFMASK; \
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v.h = ((v.h >> (s)) | ((v.h & UFP_SIGN)? \
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(LFMASK << (32 - (s))): 0)) & HFMASK
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#define FR_LRSH(v,s) v.l = ((v.l >> (s)) | \
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(v.h << (32 - (s)))) & LFMASK; \
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v.h = (v.h >> (s)) & HFMASK
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#define FR_NEG(v) v.l = (~v.l + 1) & LFMASK; \
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v.h = (~v.h + (v.l == 0)) & HFMASK
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#define FR_NEGH(v) v = (~v + 1) & HFMASK
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extern uint16 *M;
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void UnpackFP (struct ufp *fop, uint32 opnd, t_bool abs);
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void NormFP (struct ufp *fop);
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int32 StoreFP (struct ufp *fop, t_bool rnd);
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/* Floating to integer conversion */
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int32 f_fix (void)
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{
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struct ufp res;
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UnpackFP (&res, FPAB, 0); /* unpack A-B, norm */
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if ((res.h == 0) || (res.exp <= 0)) { /* result zero? */
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AR = 0;
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return 0; }
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if (res.exp > 15) {
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AR = 077777;
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return 1; }
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FR_ARSH (res, (30 - res.exp)); /* right align frac */
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if (res.sign && res.l) res.h = res.h + 1; /* round? */
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AR = res.h & DMASK; /* store result */
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return 0;
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}
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/* Integer to floating conversion */
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void f_flt (void)
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{
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struct ufp res = { 0, 15, 0, 0 }; /* +, 2**15 */
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res.h = ((uint32) AR) << 15; /* left justify */
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if (res.h & UFP_SIGN) res.sign = 1; /* set sign */
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NormFP (&res); /* normalize */
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StoreFP (&res, 0); /* store result */
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return;
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}
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/* Floating point add/subtract */
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int32 f_as (uint32 opnd, t_bool sub)
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{
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struct ufp fop1, fop2, t;
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int32 ediff;
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UnpackFP (&fop1, FPAB, 0); /* unpack A-B, norm */
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UnpackFP (&fop2, opnd, 0); /* get op, norm */
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if (sub) { /* subtract? */
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fop2.sign = fop2.sign ^ 1; /* negate sign */
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fop2.h = FR_NEGH (fop2.h); /* negate frac */
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if (fop2.h & UFP_SIGN) { /* -1/2? */
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fop2.h = UFP_NORM; /* special case */
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fop2.exp = fop2.exp + 1; } }
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if (fop1.h == 0) fop1 = fop2; /* op1 = 0? res = op2 */
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else if (fop2.h != 0) { /* op2 = 0? no add */
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if (fop1.exp < fop2.exp) { /* |op1| < |op2|? */
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t = fop2; /* swap operands */
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fop2 = fop1;
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fop1 = t; }
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ediff = fop1.exp - fop2.exp; /* get exp diff */
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if (ediff <= 24) {
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if (ediff) { FR_ARSH (fop2, ediff); } /* denorm, signed */
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fop1.h = fop1.h + fop2.h; /* add fractions */
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if (fop1.sign ^ fop2.sign) { /* eff subtract */
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if (fop1.h & UFP_SIGN) fop1.sign = 1; /* result neg? */
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else fop1.sign = 0;
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NormFP (&fop1); } /* normalize result */
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else if (fop1.h & (fop1.sign? UFP_CRY: UFP_SIGN)) { /* add, cry out? */
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fop1.h = fop1.h >> 1; /* renormalize */
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fop1.exp = fop1.exp + 1; } /* incr exp */
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} /* end if ediff */
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} /* end if fop2 */
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return StoreFP (&fop1, 1); /* store result */
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}
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/* Floating point multiply */
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int32 f_mul (uint32 opnd)
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{
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struct ufp fop1, fop2;
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struct ufp res = { 0, 0, 0, 0 };
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int32 i;
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UnpackFP (&fop1, FPAB, 1); /* unpack |A-B|, norm */
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UnpackFP (&fop2, opnd, 1); /* unpack |op|, norm */
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if (fop1.h && fop2.h) { /* if both != 0 */
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res.sign = fop1.sign ^ fop2.sign; /* sign = diff */
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res.exp = fop1.exp + fop2.exp; /* exp = sum */
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for (i = 0; i < 24; i++) { /* 24 iterations */
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if (fop2.h & UFP_LOW) /* mplr bit set? */
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res.h = res.h + fop1.h; /* add mpcn to res */
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fop2.h = fop2.h >> 1; /* shift mplr */
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FR_LRSH (res, 1); } /* shift res */
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if (res.sign) FR_NEG (res); /* correct sign */
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NormFP (&res); /* normalize */
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}
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return StoreFP (&res, 1); /* store */
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}
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/* Floating point divide */
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int32 f_div (uint32 opnd)
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{
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struct ufp fop1, fop2;
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struct ufp quo = { 0, 0, 0, 0 };
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int32 i;
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UnpackFP (&fop1, FPAB, 1); /* unpack |A-B|, norm */
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UnpackFP (&fop2, opnd, 1); /* unpack |op|, norm */
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if (fop2.h == 0) return 1; /* div by zero? */
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if (fop1.h) { /* dvd != 0? */
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quo.sign = fop1.sign ^ fop2.sign; /* sign = diff */
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quo.exp = fop1.exp - fop2.exp; /* exp = diff */
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if (fop1.h < fop2.h) { /* will sub work? */
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fop1.h = fop1.h << 1; /* ensure success */
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quo.exp = quo.exp - 1; }
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for (i = 0; i < 24; i++) { /* 24 digits */
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quo.h = quo.h << 1; /* shift quotient */
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if (fop1.h >= fop2.h) { /* subtract work? */
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fop1.h = fop1.h - fop2.h; /* decrement */
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quo.h = quo.h + UFP_RND; } /* add quo bit */
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fop1.h = fop1.h << 1; } /* shift divd */
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} /* end if fop1.h */
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if (quo.sign) quo.h = FR_NEGH (quo.h); /* correct sign */
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NormFP (&quo); /* negate */
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return StoreFP (&quo, 1); /* store result */
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}
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/* Utility routines */
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/* Unpack operand */
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void UnpackFP (struct ufp *fop, uint32 opnd, t_bool abs)
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{
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fop -> h = (opnd & FP_FRH) >> UFP_GUARD; /* get frac, guard */
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if (fop -> h) { /* non-zero? */
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fop -> sign = FP_GETSIGN (opnd); /* get sign */
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fop -> exp = FP_GETEXP (opnd); /* get exp */
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if (FP_GETEXPS (opnd)) /* get exp sign */
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fop -> exp = fop -> exp | ~FP_M_EXP; /* if -, sext */
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if (abs && fop -> sign) { /* want abs val? */
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fop -> h = FR_NEGH (fop -> h); /* negate frac*/
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if (fop -> h == UFP_SIGN) { /* -1/2? */
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fop -> h = fop -> h >> 1; /* special case */
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fop -> exp = fop -> exp + 1; } }
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NormFP (fop); } /* normalize */
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else fop -> sign = fop -> exp = 0; /* clean zero */
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fop -> l = 0;
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return;
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}
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/* Normalize unpacked floating point number */
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void NormFP (struct ufp *fop)
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{
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if (fop -> h | fop -> l) { /* any fraction? */
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uint32 test = (fop -> h >> 1) & UFP_NORM;
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while ((fop -> h & UFP_NORM) == test) { /* until norm */
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fop -> exp = fop -> exp - 1;
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fop -> h = (fop -> h << 1) | (fop -> l >> 31);
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fop -> l = fop -> l << 1; } }
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else fop -> sign = fop -> exp = 0; /* clean 0 */
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return;
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}
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/* Round fp number, store, generate overflow */
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int32 StoreFP (struct ufp *fop, t_bool rnd)
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{
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int32 hi, ov;
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if (rnd && (fop -> h & UFP_RND) &&
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((fop -> sign == 0) || (fop -> h & UFP_STKY) || fop -> l)) {
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fop -> h = fop -> h + UFP_RND; /* round */
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if (fop -> h & ((fop -> sign)? UFP_CRY: UFP_SIGN)) {
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fop -> h = fop -> h >> 1;
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fop -> exp = fop -> exp + 1; } }
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if (fop -> h == 0) hi = ov = 0; /* result 0? */
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else if (fop -> exp < -(FP_M_EXP + 1)) { /* underflow? */
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hi = 0; /* store clean 0 */
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ov = 1; }
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else if (fop -> exp > FP_M_EXP) { /* overflow? */
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hi = 0x7FFFFFFE; /* all 1's */
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ov = 1; }
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else { hi = ((fop -> h << UFP_GUARD) & FP_FRH) | /* merge frac */
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((fop -> exp & FP_M_EXP) << FP_V_EXP); /* and exp */
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if (fop -> exp < 0) hi = hi | (1 << FP_V_EXPS); } /* add exp sign */
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AR = (hi >> 16) & DMASK;
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BR = hi & DMASK;
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return ov;
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}
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