df6475181c
1. New Features 1.1 GRI-909 - This is a new simulator for the GRI-909. - It has been hand-tested; so far, no software has been discovered. 1.2 VAX - SET CPU CONHALT will cause a HALT instruction to return to the boot ROM console rather than to SIMH. SET CPU SIMHALT restores the default behavior. - BRB/W self at IPL 1F stops the simulator. This is the default behavior of VMS at exit. 1.3 PDP-18b - ATTACH -A PTR/PTP attaches the reader and punch in ASCII mode. In ASCII mode, the reader automatically sets the high order bit of incoming alphabetic data, and the punch clears the high order bit of outgoing data. 1.4 SCP - DO -V echoes commands from the file as they are executed. - Under Windows, execution priority is set BELOW_NORMAL when the simulator is running. 2. Release Notes 2.1 Bugs Fixed - PDP-11 CPU: fixed updating of MMR0 on a memory management error. - VAX FPA: changed function names to avoid conflict with C math library. - 1401 MT: read end of record generates group mark without word mark. - 1401 DP: fixed address generation and checking. - SCP: an EXIT within a DO command will cause the simulator to exit. 3. In Progress - Interdata 16b/32b: coded, not tested. - SDS 940: coded, not tested. - IBM 1620: coded, not tested. If you would like to help with the debugging of the untested simulators, they can be made available by special request.
416 lines
12 KiB
C
416 lines
12 KiB
C
/* ibm1130_sys.c: IBM 1130 simulator interface
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Copyright (c) 2002, Brian Knittel
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Based on PDP-11 simulator written by Robert M Supnik
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Revision History
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0.24 2002Mar27 - Fixed BOSC bug; BOSC works in short instructions too
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0.23 2002Feb26 - Added @decklist feature for ATTACH CR.
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0.22 2002Feb26 - Replaced "strupr" with "upcase" for compatibility.
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0.21 2002Feb25 - Some compiler compatibiity changes, couple of compiler-detected
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bugs
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0.01 2001Jul31 - Derived from pdp11_sys.c, which carries this disclaimer:
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Copyright (c) 1993-2001, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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*/
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#include "ibm1130_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev, console_dev, dsk_dev, cr_dev, cp_dev;
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extern DEVICE tti_dev, tto_dev, prt_dev, log_dev;
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extern UNIT cpu_unit;
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extern REG cpu_reg[];
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extern int32 saved_PC;
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax number of words for examine
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sim_devices array of pointers to simulated devices
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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char sim_name[] = "IBM 1130";
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char sim_version[] = "V0.24";
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 4;
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DEVICE *sim_devices[] = {
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&cpu_dev, /* the cpu */
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&log_dev, /* cpu logging virtual device */
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#ifdef GUI_SUPPORT
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&console_dev, /* console display (windows GUI) */
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#endif
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&dsk_dev, /* disk drive(s) */
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&cr_dev, /* card reader/punch */
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&cp_dev,
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&tti_dev, /* console keyboard, selectric printer */
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&tto_dev,
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&prt_dev, /* 1132 printer */
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NULL
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};
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const char *sim_stop_messages[] = {
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"Unknown error",
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"Wait",
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"Invalid command",
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"Simulator breakpoint",
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"Use of incomplete simulator function",
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};
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/* Loader. IPL is normally performed by card reader (boot command). This function
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* loads hex data from a file for testing purposes. The format is:
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*
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* blank lines or lines starting with ; / or # are ignored as comments
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*
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* @XXXX set load addresss to hex value XXXX
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* XXXX store hex word value XXXX at current load address and increment address
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* ...
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* =XXXX set IAR to hex value XXXX
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* ZXXXX zero XXXX words and increment load address
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* SXXXX set console entry switches to XXXX. This lets a program specify the
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* default value for the toggle switches.
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*
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* Multiple @ and data sections may be entered. If more than one = or S value is specified
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* the last one wins.
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*
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* Note: the load address @XXXX and data values XXXX can be followed by the letter
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* R to indicate that the values are relocatable addresses. This is ignored in this loader,
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* but the asm1130 cross assembler may put them there.
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*/
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t_stat my_load (FILE *fileref, char *cptr, char *fnam)
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{
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char line[150], *c;
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int iaddr = -1, runaddr = -1, val, nwords;
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while (fgets(line, sizeof(line), fileref) != NULL) {
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for (c = line; *c && *c <= ' '; c++) // find first nonblank
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;
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if (*c == '\0' || *c == '#' || *c == '/' || *c == ';')
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continue; // empty line or comment
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if (*c == '@') { // set load address
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if (sscanf(c+1, "%x", &iaddr) != 1)
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return SCPE_FMT;
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}
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else if (*c == '=') {
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if (sscanf(c+1, "%x", &runaddr) != 1)
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return SCPE_FMT;
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}
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else if (*c == 's' || *c == 'S') {
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if (sscanf(c+1, "%x", &val) != 1)
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return SCPE_FMT;
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CES = val & 0xFFFF; // preload console entry switches
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}
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else if (*c == 'z' || *c == 'Z') {
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if (sscanf(c+1, "%x", &nwords) != 1)
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return SCPE_FMT;
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if (iaddr == -1)
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return SCPE_FMT;
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while (--nwords >= 0) {
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WriteW(iaddr, 0);
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iaddr++;
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}
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}
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else if (strchr("0123456789abcdefABCDEF", *c) != NULL) {
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if (sscanf(c, "%x", &val) != 1)
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return SCPE_FMT;
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if (iaddr == -1)
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return SCPE_FMT;
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WriteW(iaddr, val); // store data
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iaddr++;
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}
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else
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return SCPE_FMT; // unexpected data
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}
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if (runaddr != -1)
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IAR = runaddr;
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return SCPE_OK;
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}
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t_stat my_save (FILE *fileref, char *cptr, char *fnam)
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{
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int iaddr, nzeroes = 0, nwords = (int) (MEMSIZE/2), val;
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fprintf(fileref, "=%04x\r\n", IAR);
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fprintf(fileref, "@0000\r\n");
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for (iaddr = 0; iaddr < nwords; iaddr++) {
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val = ReadW(iaddr);
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if (val == 0) // queue up zeroes
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nzeroes++;
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else {
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if (nzeroes >= 4) { // spit out a Z directive
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fprintf(fileref, "Z%04x\r\n", nzeroes);
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nzeroes = 0;
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}
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else { // write queued zeroes literally
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while (nzeroes > 0) {
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fprintf(fileref, " 0000\r\n");
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nzeroes--;
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}
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}
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fprintf(fileref, " %04x\r\n", val);
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}
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}
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if (nzeroes >= 4) { // emit any queued zeroes
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fprintf(fileref, "Z%04x\r\n", nzeroes);
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nzeroes = 0;
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}
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else {
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while (nzeroes > 0) {
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fprintf(fileref, " 0000\r\n");
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nzeroes--;
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}
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}
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return SCPE_OK;
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}
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t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
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{
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if (flag)
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return my_save(fileref, cptr, fnam);
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else
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return my_load(fileref, cptr, fnam);
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}
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/* Specifier decode
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Inputs:
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*of = output stream
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addr = current PC
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spec = specifier
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nval = next word
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flag = TRUE if decoding for CPU
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iflag = TRUE if decoding integer instruction
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Outputs:
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count = -number of extra words retired
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*/
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/* Symbolic decode
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Inputs:
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*of = output stream
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addr = current PC
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*val = values to decode
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*uptr = pointer to unit
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sw = switches
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Outputs:
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return = if >= 0, error code
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if < 0, number of extra words retired
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*/
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static char *opcode[] = {
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"?00 ", "XIO ", "SLA ", "SRA ",
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"LDS ", "STS ", "WAIT", "?07 ",
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"BSI ", "BSC ", "?0A ", "?0B ",
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"LDX ", "STD ", "MDX ", "?0F ",
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"A ", "AD ", "S ", "SD ",
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"M ", "D ", "?16 ", "?17 ",
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"LD ", "LDD ", "STO ", "STD ",
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"AND ", "OR ", "EOR ", "?1F ",
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};
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static char relative[] = { // true if short mode displacements are IAR relative
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FALSE, TRUE, FALSE, FALSE,
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FALSE, TRUE, FALSE, FALSE,
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TRUE, FALSE, FALSE, FALSE,
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TRUE, TRUE, TRUE, FALSE,
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TRUE, TRUE, TRUE, TRUE,
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TRUE, TRUE, FALSE, FALSE,
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TRUE, TRUE, TRUE, TRUE,
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TRUE, TRUE, TRUE, FALSE
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};
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static char *lsopcode[] = {"SLA ", "SLCA ", "SLT ", "SLC "};
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static char *rsopcode[] = {"SRA ", "?188 ", "SRT ", "RTE "};
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static char tagc[] = " 123";
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t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw)
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{
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int32 cflag, c1, c2, OP, F, TAG, INDIR, DSPLC, IR, eaddr;
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char *mnem, tst[12];
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cflag = (uptr == NULL) || (uptr == &cpu_unit);
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c1 = val[0] & 0177;
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c2 = (val[0] >> 8) & 0177;
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if (sw & SWMASK ('A')) { /* ASCII? */
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fprintf (of, (c1 < 040)? "<%03o>": "%c", c1);
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return SCPE_OK;
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}
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if (sw & SWMASK ('C')) { /* character? */
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fprintf (of, (c1 < 040)? "<%03o>": "%c", c1);
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fprintf (of, (c2 < 040)? "<%03o>": "%c", c2);
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return SCPE_OK;
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}
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if (! (sw & SWMASK ('M')))
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return SCPE_ARG;
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IR = val[0];
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OP = (IR >> 11) & 0x1F; /* opcode */
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F = IR & 0x0400; /* format bit: 1 = long instr */
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TAG = IR & 0x0300; /* tag bits: index reg select */
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if (TAG)
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TAG >>= 8;
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if (F) { /* long instruction, ASSUME it's valid (have to decrement IAR if not) */
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INDIR = IR & 0x0080; /* indirect bit */
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DSPLC = IR & 0x007F; /* displacement or modifier */
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if (DSPLC & 0x0040)
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DSPLC |= ~ 0x7F; /* sign extend */
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eaddr = val[1]; /* get reference address */
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}
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else { /* short instruction, use displacement */
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INDIR = 0; /* never indirect */
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DSPLC = IR & 0x00FF; /* get displacement */
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if (DSPLC & 0x0080)
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DSPLC |= ~ 0xFF;
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eaddr = DSPLC;
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if (relative[OP] && ! TAG)
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eaddr += addr+1; /* turn displacement into address */
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}
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mnem = opcode[OP]; /* get mnemonic */
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if (OP == 0x02) { /* left shifts are special */
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mnem = lsopcode[(DSPLC >> 6) & 0x0003];
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DSPLC &= 0x003F;
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eaddr = DSPLC;
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}
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else if (OP == 0x03) { /* right shifts too */
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mnem = rsopcode[(DSPLC >> 6) & 0x0003];
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DSPLC &= 0x003F;
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eaddr = DSPLC;
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}
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else if (OP == 0x09) {
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if (IR & 0x40)
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mnem = "BOSC";
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tst[0] = '\0';
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if (DSPLC & 0x20) strcat(tst, "Z");
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if (DSPLC & 0x10) strcat(tst, "-");
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if (DSPLC & 0x08) strcat(tst, "+");
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if (DSPLC & 0x04) strcat(tst, "E");
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if (DSPLC & 0x02) strcat(tst, "C");
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if (DSPLC & 0x01) strcat(tst, "O");
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if (F) {
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fprintf(of, "%04x %s %c%c %s,%04x ", IR & 0xFFFF, mnem, F ? (INDIR ? 'I' : 'L') : ' ', tagc[TAG], tst, eaddr & 0xFFFF);
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return -1;
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}
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fprintf(of, "%04x %s %c%c %s ", IR & 0xFFFF, mnem, F ? (INDIR ? 'I' : 'L') : ' ', tagc[TAG], tst);
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return SCPE_OK;
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}
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else if (OP == 0x0e && TAG == 0) { // MDX with no tag => MDM or jump
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if (F) {
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fprintf(of, "%04x %s %c%c %04x,%x (%d) ", IR & 0xFFFF, "MDM ", (INDIR ? 'I' : 'L'), tagc[TAG], eaddr & 0xFFFF, DSPLC & 0xFFFF, DSPLC);
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return -1;
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}
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mnem = "JMP ";
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}
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fprintf(of, "%04x %s %c%c %04x ", IR & 0xFFFF, mnem, F ? (INDIR ? 'I' : 'L') : ' ', tagc[TAG], eaddr & 0xFFFF);
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return F ? -1 : SCPE_OK; /* inform how many words we read */
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}
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int32 get_reg (char *cptr, const char *strings[], char mchar)
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{
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return -1;
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}
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/* Number or memory address
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Inputs:
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*cptr = pointer to input string
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*dptr = pointer to output displacement
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*pflag = pointer to accumulating flags
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Outputs:
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cptr = pointer to next character in input string
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NULL if parsing error
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Flags: 0 (no result), A_NUM (number), A_REL (relative)
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*/
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char *get_addr (char *cptr, int32 *dptr, int32 *pflag)
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{
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return 0;
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}
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/* Specifier decode
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Inputs:
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*cptr = pointer to input string
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addr = current PC
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n1 = 0 if no extra word used
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-1 if extra word used in prior decode
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*sptr = pointer to output specifier
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*dptr = pointer to output displacement
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cflag = true if parsing for the CPU
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iflag = true if integer specifier
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Outputs:
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status = = -1 extra word decoded
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= 0 ok
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= +1 error
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*/
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t_stat get_spec (char *cptr, t_addr addr, int32 n1, int32 *sptr, t_value *dptr,
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int32 cflag, int32 iflag)
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{
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return -1;
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}
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/* Symbolic input
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Inputs:
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*cptr = pointer to input string
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addr = current PC
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*uptr = pointer to unit
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*val = pointer to output values
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sw = switches
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Outputs:
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status = > 0 error code
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<= 0 -number of extra words
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*/
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t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
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{
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return SCPE_ARG;
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}
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