df6475181c
1. New Features 1.1 GRI-909 - This is a new simulator for the GRI-909. - It has been hand-tested; so far, no software has been discovered. 1.2 VAX - SET CPU CONHALT will cause a HALT instruction to return to the boot ROM console rather than to SIMH. SET CPU SIMHALT restores the default behavior. - BRB/W self at IPL 1F stops the simulator. This is the default behavior of VMS at exit. 1.3 PDP-18b - ATTACH -A PTR/PTP attaches the reader and punch in ASCII mode. In ASCII mode, the reader automatically sets the high order bit of incoming alphabetic data, and the punch clears the high order bit of outgoing data. 1.4 SCP - DO -V echoes commands from the file as they are executed. - Under Windows, execution priority is set BELOW_NORMAL when the simulator is running. 2. Release Notes 2.1 Bugs Fixed - PDP-11 CPU: fixed updating of MMR0 on a memory management error. - VAX FPA: changed function names to avoid conflict with C math library. - 1401 MT: read end of record generates group mark without word mark. - 1401 DP: fixed address generation and checking. - SCP: an EXIT within a DO command will cause the simulator to exit. 3. In Progress - Interdata 16b/32b: coded, not tested. - SDS 940: coded, not tested. - IBM 1620: coded, not tested. If you would like to help with the debugging of the untested simulators, they can be made available by special request.
217 lines
6.7 KiB
C
217 lines
6.7 KiB
C
/* pdp18b_drm.c: drum/fixed head disk simulator
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Copyright (c) 1993-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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drm (PDP-7) Type 24 serial drum
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(PDP-9) RM09 serial drum
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03-Feb-02 RMS Fixed bug in reset routine (found by Robert Alan Byer)
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06-Jan-02 RMS Revised enable/disable support
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25-Nov-01 RMS Revised interrupt structure
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10-Jun-01 RMS Cleaned up IOT decoding to reflect hardware
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26-Apr-01 RMS Added device enable/disable support
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14-Apr-99 RMS Changed t_addr to unsigned
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*/
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#include "pdp18b_defs.h"
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#include <math.h>
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/* Constants */
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#define DRM_NUMWDS 256 /* words/sector */
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#define DRM_NUMSC 2 /* sectors/track */
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#define DRM_NUMTR 256 /* tracks/drum */
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#define DRM_NUMDK 1 /* drum/controller */
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#define DRM_NUMWDT (DRM_NUMWDS * DRM_NUMSC) /* words/track */
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#define DRM_SIZE (DRM_NUMDK * DRM_NUMTR * DRM_NUMWDT) /* words/drum */
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#define DRM_SMASK ((DRM_NUMTR * DRM_NUMSC) - 1) /* sector mask */
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/* Parameters in the unit descriptor */
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#define FUNC u4 /* function */
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#define DRM_READ 000 /* read */
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#define DRM_WRITE 040 /* write */
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#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \
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((double) DRM_NUMWDT)))
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extern int32 M[];
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extern int32 int_hwre[API_HLVL+1], dev_enb;
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extern UNIT cpu_unit;
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int32 drm_da = 0; /* track address */
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int32 drm_ma = 0; /* memory address */
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int32 drm_err = 0; /* error flag */
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int32 drm_wlk = 0; /* write lock */
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int32 drm_time = 10; /* inter-word time */
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int32 drm_stopioe = 1; /* stop on error */
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t_stat drm_svc (UNIT *uptr);
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t_stat drm_reset (DEVICE *dptr);
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t_stat drm_boot (int32 unitno);
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/* DRM data structures
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drm_dev DRM device descriptor
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drm_unit DRM unit descriptor
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drm_reg DRM register list
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*/
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UNIT drm_unit =
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{ UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
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DRM_SIZE) };
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REG drm_reg[] = {
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{ ORDATA (DA, drm_da, 9) },
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{ ORDATA (MA, drm_ma, 15) },
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{ FLDATA (INT, int_hwre[API_DRM], INT_V_DRM) },
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{ FLDATA (DONE, int_hwre[API_DRM], INT_V_DRM) },
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{ FLDATA (ERR, drm_err, 0) },
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{ ORDATA (WLK, drm_wlk, 32) },
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{ DRDATA (TIME, drm_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (STOP_IOE, drm_stopioe, 0) },
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{ FLDATA (*DEVENB, dev_enb, ENB_V_DRM), REG_HRO },
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{ NULL } };
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MTAB drm_mod[] = {
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{ MTAB_XTD|MTAB_VDV, ENB_DRM, NULL, "ENABLED", &set_enb },
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{ MTAB_XTD|MTAB_VDV, ENB_DRM, NULL, "DISABLED", &set_dsb },
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{ 0 } };
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DEVICE drm_dev = {
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"DRM", &drm_unit, drm_reg, drm_mod,
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1, 8, 20, 1, 8, 18,
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NULL, NULL, &drm_reset,
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&drm_boot, NULL, NULL };
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/* IOT routines */
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int32 drm60 (int32 pulse, int32 AC)
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{
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if ((pulse & 027) == 06) { /* DRLR, DRLW */
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drm_ma = AC & ADDRMASK; /* load mem addr */
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drm_unit.FUNC = pulse & 040; } /* save function */
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return AC;
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}
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int32 drm61 (int32 pulse, int32 AC)
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{
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int32 t;
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if (pulse & 001) { /* DRSF */
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if (TST_INT (DRM)) AC = AC | IOT_SKP; }
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if (pulse & 002) { /* DRCF */
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CLR_INT (DRM); /* clear done */
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drm_err = 0; } /* clear error */
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if (pulse & 004) { /* DRSS */
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drm_da = AC & DRM_SMASK; /* load sector # */
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t = ((drm_da % DRM_NUMSC) * DRM_NUMWDS) - GET_POS (drm_time);
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if (t < 0) t = t + DRM_NUMWDT; /* wrap around? */
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sim_activate (&drm_unit, t * drm_time); } /* schedule op */
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return AC;
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}
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int32 drm62 (int32 pulse, int32 AC)
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{
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int32 t;
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if (pulse & 001) { /* DRSN */
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if (drm_err == 0) AC = AC | IOT_SKP; }
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if (pulse & 004) { /* DRCS */
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CLR_INT (DRM); /* clear done */
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drm_err = 0; /* clear error */
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t = ((drm_da % DRM_NUMSC) * DRM_NUMWDS) - GET_POS (drm_time);
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if (t < 0) t = t + DRM_NUMWDT; /* wrap around? */
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sim_activate (&drm_unit, t * drm_time); } /* schedule op */
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return AC;
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}
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/* Unit service
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This code assumes the entire drum is buffered.
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*/
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t_stat drm_svc (UNIT *uptr)
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{
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int32 i;
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t_addr da;
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if ((uptr -> flags & UNIT_BUF) == 0) { /* not buf? abort */
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drm_err = 1; /* set error */
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SET_INT (DRM); /* set done */
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return IORETURN (drm_stopioe, SCPE_UNATT); }
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da = drm_da * DRM_NUMWDS; /* compute dev addr */
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for (i = 0; i < DRM_NUMWDS; i++, da++) { /* do transfer */
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if (uptr -> FUNC == DRM_READ) {
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if (MEM_ADDR_OK (drm_ma)) /* read, check nxm */
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M[drm_ma] = *(((int32 *) uptr -> filebuf) + da); }
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else { if ((drm_wlk >> (drm_da >> 4)) & 1) drm_err = 1;
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else { *(((int32 *) uptr -> filebuf) + da) = M[drm_ma];
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if (da >= uptr -> hwmark)
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uptr -> hwmark = da + 1; } }
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drm_ma = (drm_ma + 1) & ADDRMASK; } /* incr mem addr */
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drm_da = (drm_da + 1) & DRM_SMASK; /* incr dev addr */
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SET_INT (DRM); /* set done */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat drm_reset (DEVICE *dptr)
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{
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drm_da = drm_ma = drm_err = 0;
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CLR_INT (DRM); /* clear done */
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sim_cancel (&drm_unit);
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return SCPE_OK;
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}
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/* IORS routine */
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int32 drm_iors (void)
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{
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return (TST_INT (DRM)? IOS_DRM: 0);
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}
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/* Bootstrap routine */
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#define BOOT_START 02000
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#define BOOT_LEN (sizeof (boot_rom) / sizeof (int))
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static const int32 boot_rom[] = {
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0750000, /* CLA ; dev, mem addr */
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0706006, /* DRLR ; load ma */
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0706106, /* DRSS ; load da, start */
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0706101, /* DRSF ; wait for done */
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0602003, /* JMP .-1
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0600000 /* JMP 0 ; enter boot */
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};
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t_stat drm_boot (int32 unitno)
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{
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int32 i;
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extern int32 saved_PC;
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for (i = 0; i < BOOT_LEN; i++) M[BOOT_START + i] = boot_rom[i];
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saved_PC = BOOT_START;
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return SCPE_OK;
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}
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