457 lines
20 KiB
C
457 lines
20 KiB
C
/* alpha_defs.h: Alpha architecture definitions file
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Copyright (c) 2003-2006, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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Respectfully dedicated to the great people of the Alpha chip, systems, and
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software development projects; and to the memory of Peter Conklin, of the
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Alpha Program Office.
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*/
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#ifndef _ALPHA_DEFS_H_
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#define _ALPHA_DEFS_H_ 0
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#include "sim_defs.h"
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#include <setjmp.h>
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#if defined (__GNUC__)
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#define INLINE inline
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#else
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#define INLINE
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#endif
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/* Configuration */
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#define INITMEMSIZE (1 << 24) /* !!debug!! */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) ((x) < MEMSIZE)
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#define DEV_DIB (1u << (DEV_V_UF + 0)) /* takes a DIB */
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/* Simulator stops */
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#define STOP_HALT 1 /* halt */
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#define STOP_IBKPT 2 /* breakpoint */
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#define STOP_NSPAL 3 /* non-supported PAL */
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#define STOP_KSNV 4 /* kernel stk inval */
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#define STOP_INVABO 5 /* invalid abort code */
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#define STOP_MME 6 /* console mem mgt error */
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/* Bit patterns */
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#define M8 0xFF
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#define M16 0xFFFF
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#define M32 0xFFFFFFFF
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#define M64 0xFFFFFFFFFFFFFFFF
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#define B_SIGN 0x80
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#define W_SIGN 0x8000
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#define L_SIGN 0x80000000
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#define Q_SIGN 0x8000000000000000
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#define Q_GETSIGN(x) (((uint32) ((x) >> 63)) & 1)
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/* Architectural variants */
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#define AMASK_BWX 0x0001 /* byte/word */
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#define AMASK_FIX 0x0002 /* sqrt/flt-int moves */
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#define AMASK_CIX 0x0004 /* counts */
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#define AMASK_MVI 0x0100 /* multimedia */
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#define AMASK_PRC 0x0200 /* precise exceptions */
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#define AMASK_PFM 0x1000 /* prefetch w modify */
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#define IMPLV_EV4 0x0 /* EV4 (21064) */
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#define IMPLV_EV5 0x1 /* EV5 (21164) */
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#define IMPLV_EV6 0x2 /* EV6 (21264) */
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#define IMPLV_EV7 0x3 /* EV7 (21364) */
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/* Instruction formats */
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#define I_V_OP 26 /* opcode */
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#define I_M_OP 0x3F
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#define I_OP (I_M_OP << I_V_OP)
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#define I_V_RA 21 /* Ra */
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#define I_M_RA 0x1F
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#define I_V_RB 16 /* Rb */
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#define I_M_RB 0x1F
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#define I_V_FTRP 13 /* floating trap mode */
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#define I_M_FTRP 0x7
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#define I_FTRP (I_M_FTRP << I_V_FTRP)
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#define I_F_VAXRSV 0x4800 /* VAX reserved */
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#define I_FTRP_V 0x2000 /* /V trap */
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#define I_FTRP_U 0x2000 /* /U trap */
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#define I_FTRP_S 0x8000 /* /S trap */
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#define I_FTRP_SUI 0xE000 /* /SUI trap */
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#define I_FTRP_SVI 0xE000 /* /SVI trap */
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#define I_V_FRND 11 /* floating round mode */
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#define I_M_FRND 0x3
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#define I_FRND (I_M_FRND << I_V_FRND)
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#define I_FRND_C 0 /* chopped */
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#define I_FRND_M 1 /* to minus inf */
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#define I_FRND_N 2 /* normal */
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#define I_FRND_D 3 /* dynamic */
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#define I_FRND_P 3 /* in FPCR: plus inf */
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#define I_V_FSRC 9 /* floating source */
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#define I_M_FSRC 0x3
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#define I_FSRC (I_M_FSRC << I_V_FSRC)
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#define I_FSRC_X 0x0200 /* data type X */
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#define I_V_FFNC 5 /* floating function */
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#define I_M_FFNC 0x3F
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#define I_V_LIT8 13 /* integer 8b literal */
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#define I_M_LIT8 0xFF
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#define I_V_ILIT 12 /* literal flag */
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#define I_ILIT (1u << I_V_ILIT)
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#define I_V_IFNC 5 /* integer function */
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#define I_M_IFNC 0x3F
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#define I_V_RC 0 /* Rc */
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#define I_M_RC 0x1F
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#define I_V_MDSP 0 /* memory displacement */
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#define I_M_MDSP 0xFFFF
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#define I_V_BDSP 0
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#define I_M_BDSP 0x1FFFFF /* branch displacement */
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#define I_V_PALOP 0
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#define I_M_PALOP 0x3FFFFFF /* PAL subopcode */
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#define I_GETOP(x) (((x) >> I_V_OP) & I_M_OP)
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#define I_GETRA(x) (((x) >> I_V_RA) & I_M_RA)
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#define I_GETRB(x) (((x) >> I_V_RB) & I_M_RB)
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#define I_GETLIT8(x) (((x) >> I_V_LIT8) & I_M_LIT8)
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#define I_GETIFNC(x) (((x) >> I_V_IFNC) & I_M_IFNC)
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#define I_GETFRND(x) (((x) >> I_V_FRND) & I_M_FRND)
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#define I_GETFFNC(x) (((x) >> I_V_FFNC) & I_M_FFNC)
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#define I_GETRC(x) (((x) >> I_V_RC) & I_M_RC)
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#define I_GETMDSP(x) (((x) >> I_V_MDSP) & I_M_MDSP)
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#define I_GETBDSP(x) (((x) >> I_V_BDSP) & I_M_BDSP)
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#define I_GETPAL(x) (((x) >> I_V_PALOP) & I_M_PALOP)
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/* Floating point types */
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#define DT_F 0 /* type F */
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#define DT_G 1 /* type G */
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#define DT_S 0 /* type S */
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#define DT_T 1 /* type T */
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/* Floating point memory format (VAX F) */
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#define F_V_SIGN 15
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#define F_SIGN (1u << F_V_SIGN)
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#define F_V_EXP 7
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#define F_M_EXP 0xFF
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#define F_BIAS 0x80
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#define F_EXP (F_M_EXP << F_V_EXP)
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#define F_V_FRAC 29
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#define F_GETEXP(x) ((uint32) (((x) >> F_V_EXP) & F_M_EXP))
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#define SWAP_VAXF(x) ((((x) >> 16) & 0xFFFF) | (((x) & 0xFFFF) << 16))
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/* Floating point memory format (VAX G) */
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#define G_V_SIGN 15
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#define G_SIGN (1u << F_V_SIGN)
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#define G_V_EXP 4
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#define G_M_EXP 0x7FF
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#define G_BIAS 0x400
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#define G_EXP (G_M_EXP << G_V_EXP)
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#define G_GETEXP(x) ((uint32) (((x) >> G_V_EXP) & G_M_EXP))
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#define SWAP_VAXG(x) ((((x) & 0x000000000000FFFF) << 48) | \
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(((x) & 0x00000000FFFF0000) << 16) | \
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(((x) >> 16) & 0x00000000FFFF0000) | \
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(((x) >> 48) & 0x000000000000FFFF))
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/* Floating memory format (IEEE S) */
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#define S_V_SIGN 31
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#define S_SIGN (1u << S_V_SIGN)
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#define S_V_EXP 23
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#define S_M_EXP 0xFF
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#define S_BIAS 0x7F
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#define S_NAN 0xFF
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#define S_EXP (S_M_EXP << S_V_EXP)
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#define S_V_FRAC 29
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#define S_GETEXP(x) ((uint32) (((x) >> S_V_EXP) & S_M_EXP))
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/* Floating point memory format (IEEE T) */
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#define T_V_SIGN 63
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#define T_SIGN 0x8000000000000000
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#define T_V_EXP 52
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#define T_M_EXP 0x7FF
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#define T_BIAS 0x3FF
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#define T_NAN 0x7FF
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#define T_EXP 0x7FF0000000000000
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#define T_FRAC 0x000FFFFFFFFFFFFF
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#define T_GETEXP(x) ((uint32) (((uint32) ((x) >> T_V_EXP)) & T_M_EXP))
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/* Floating point register format (all except VAX D) */
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#define FPR_V_SIGN 63
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#define FPR_SIGN 0x8000000000000000
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#define FPR_V_EXP 52
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#define FPR_M_EXP 0x7FF
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#define FPR_NAN 0x7FF
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#define FPR_EXP 0x7FF0000000000000
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#define FPR_HB 0x0010000000000000
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#define FPR_FRAC 0x000FFFFFFFFFFFFF
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#define FPR_GUARD (UF_V_NM - FPR_V_EXP)
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#define FPR_GETSIGN(x) (((uint32) ((x) >> FPR_V_SIGN)) & 1)
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#define FPR_GETEXP(x) (((uint32) ((x) >> FPR_V_EXP)) & FPR_M_EXP)
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#define FPR_GETFRAC(x) ((x) & FPR_FRAC)
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#define FP_TRUE 0x4000000000000000 /* 0.5/2.0 in reg */
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/* Floating point register format (VAX D) */
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#define FDR_V_SIGN 63
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#define FDR_SIGN 0x8000000000000000
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#define FDR_V_EXP 55
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#define FDR_M_EXP 0xFF
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#define FDR_EXP 0x7F80000000000000
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#define FDR_HB 0x0080000000000000
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#define FDR_FRAC 0x007FFFFFFFFFFFFF
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#define FDR_GUARD (UF_V_NM - FDR_V_EXP)
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#define FDR_GETSIGN(x) (((uint32) ((x) >> FDR_V_SIGN)) & 1)
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#define FDR_GETEXP(x) (((uint32) ((x) >> FDR_V_EXP)) & FDR_M_EXP)
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#define FDR_GETFRAC(x) ((x) & FDR_FRAC)
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#define D_BIAS 0x80
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/* Unpacked floating point number */
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typedef struct {
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uint32 sign;
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int32 exp;
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t_uint64 frac;
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} UFP;
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#define UF_V_NM 63
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#define UF_NM 0x8000000000000000 /* normalized */
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/* IEEE control register (left 32b only) */
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#define FPCR_SUM 0x80000000 /* summary */
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#define FPCR_INED 0x40000000 /* inexact disable */
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#define FPCR_UNFD 0x20000000 /* underflow disable */
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#define FPCR_UNDZ 0x10000000 /* underflow to 0 */
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#define FPCR_V_RMOD 26 /* rounding mode */
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#define FPCR_M_RMOD 0x3
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#define FPCR_IOV 0x02000000 /* integer overflow */
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#define FPCR_INE 0x01000000 /* inexact */
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#define FPCR_UNF 0x00800000 /* underflow */
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#define FPCR_OVF 0x00400000 /* overflow */
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#define FPCR_DZE 0x00200000 /* div by zero */
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#define FPCR_INV 0x00100000 /* invalid operation */
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#define FPCR_OVFD 0x00080000 /* overflow disable */
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#define FPCR_DZED 0x00040000 /* div by zero disable */
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#define FPCR_INVD 0x00020000 /* invalid op disable */
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#define FPCR_DNZ 0x00010000 /* denormal to zero */
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#define FPCR_DNOD 0x00008000 /* denormal disable */
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#define FPCR_RAZ 0x00007FFF /* zero */
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#define FPCR_ERR (FPCR_IOV|FPCR_INE|FPCR_UNF|FPCR_OVF|FPCR_DZE|FPCR_INV)
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#define FPCR_GETFRND(x) (((x) >> FPCR_V_RMOD) & FPCR_M_RMOD)
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/* PTE - hardware format */
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#define PTE_V_PFN 32 /* PFN */
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#define PFN_MASK 0xFFFFFFFF
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#define PTE_V_UWE 15 /* write enables */
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#define PTE_V_SWE 14
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#define PTE_V_EWE 13
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#define PTE_V_KWE 12
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#define PTE_V_URE 11 /* read enables */
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#define PTE_V_SRE 10
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#define PTE_V_ERE 9
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#define PTE_V_KRE 8
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#define PTE_V_GH 5 /* granularity hint */
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#define PTE_M_GH 0x3
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#define PTE_GH (PTE_M_GH << PTE_V_GH)
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#define PTE_V_ASM 4 /* address space match */
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#define PTE_V_FOE 3 /* fault on execute */
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#define PTE_V_FOW 2 /* fault on write */
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#define PTE_V_FOR 1 /* fault on read */
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#define PTE_V_V 0 /* valid */
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#define PTE_UWE (1u << PTE_V_UWE)
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#define PTE_SWE (1u << PTE_V_SWE)
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#define PTE_EWE (1u << PTE_V_EWE)
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#define PTE_KWE (1u << PTE_V_KWE)
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#define PTE_URE (1u << PTE_V_URE)
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#define PTE_SRE (1u << PTE_V_SRE)
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#define PTE_ERE (1u << PTE_V_ERE)
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#define PTE_KRE (1u << PTE_V_KRE)
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#define PTE_ASM (1u << PTE_V_ASM)
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#define PTE_FOE (1u << PTE_V_FOE)
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#define PTE_FOW (1u << PTE_V_FOW)
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#define PTE_FOR (1u << PTE_V_FOR)
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#define PTE_V (1u << PTE_V_V)
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#define PTE_MASK 0xFF7F
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#define PTE_GETGH(x) ((((uint32) (x)) >> PTE_V_GH) & PTE_M_GH)
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#define VPN_GETLVL1(x) (((x) >> ((2 * VA_N_LVL) - 3)) & (VA_M_LVL << 3))
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#define VPN_GETLVL2(x) (((x) >> (VA_N_LVL - 3)) & (VA_M_LVL << 3))
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#define VPN_GETLVL3(x) (((x) << 3) & (VA_M_LVL << 3))
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#define ACC_E(m) ((PTE_KRE << (m)) | PTE_FOE | PTE_V)
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#define ACC_R(m) ((PTE_KRE << (m)) | PTE_FOR | PTE_V)
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#define ACC_W(m) ((PTE_KWE << (m)) | PTE_FOW | PTE_V)
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#define ACC_M(m) (((PTE_KRE|PTE_KWE) << (m)) | PTE_FOR | PTE_FOW | PTE_V)
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/* Exceptions */
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#define ABORT(x) longjmp (save_env, (x))
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#define ABORT1(x,y) { p1 = (x); longjmp (save_env, (y)); }
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#define EXC_RSVI 0x01 /* reserved instruction */
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#define EXC_RSVO 0x02 /* reserved operand */
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#define EXC_ALIGN 0x03 /* operand alignment */
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#define EXC_FPDIS 0x04 /* flt point disabled */
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#define EXC_TBM 0x08 /* TLB miss */
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#define EXC_FOX 0x10 /* fault on r/w/e */
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#define EXC_ACV 0x14 /* access control viol */
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#define EXC_TNV 0x18 /* translation not valid */
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#define EXC_BVA 0x1C /* bad address format */
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#define EXC_E 0x00 /* offset for execute */
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#define EXC_R 0x01 /* offset for read */
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#define EXC_W 0x02 /* offset for write */
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/* Traps - corresponds to arithmetic trap summary register */
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#define TRAP_SWC 0x001 /* software completion */
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#define TRAP_INV 0x002 /* invalid operand */
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#define TRAP_DZE 0x004 /* divide by zero */
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#define TRAP_OVF 0x008 /* overflow */
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#define TRAP_UNF 0x010 /* underflow */
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#define TRAP_INE 0x020 /* inexact */
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#define TRAP_IOV 0x040 /* integer overflow */
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#define TRAP_SUMM_RW 0x07F
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/* PALcode */
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#define SP R[30] /* stack pointer */
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#define MODE_K 0 /* kernel */
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#define MODE_E 1 /* executive (UNIX user) */
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#define MODE_S 2 /* supervisor */
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#define MODE_U 3 /* user */
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#define PAL_UNDF 0 /* undefined */
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#define PAL_VMS 1 /* VMS */
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#define PAL_UNIX 2 /* UNIX */
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#define PAL_NT 3 /* Windows NT */
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/* Machine check error summary register */
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#define MCES_INP 0x01 /* in progress */
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#define MCES_SCRD 0x02 /* sys corr in prog */
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#define MCES_PCRD 0x04 /* proc corr in prog */
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#define MCES_DSCRD 0x08 /* disable system corr */
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#define MCES_DPCRD 0x10 /* disable proc corr */
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#define MCES_W1C (MCES_INP|MCES_SCRD|MCES_PCRD)
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#define MCES_DIS (MCES_DSCRD|MCES_DPCRD)
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/* I/O devices */
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#define L_BYTE 0 /* IO request lengths */
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#define L_WORD 1
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#define L_LONG 2
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#define L_QUAD 3
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/* Device information block */
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typedef struct { /* device info block */
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t_uint64 low; /* low addr */
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t_uint64 high; /* high addr */
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t_bool (*read)(t_uint64 pa, t_uint64 *val, uint32 lnt);
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t_bool (*write)(t_uint64 pa, t_uint64 val, uint32 lnt);
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uint32 ipl;
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} DIB;
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/* Interrupt system - 6 levels in EV4 and EV6, 4 in EV5 - software expects 4 */
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#define IPL_HMAX 0x17 /* highest hwre level */
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#define IPL_HMIN 0x14 /* lowest hwre level */
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#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
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#define IPL_SMAX 0x0F /* highest swre level */
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/* Macros */
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#define PCQ_SIZE 64 /* must be 2**n */
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = (PC - 4) & M64
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#define SEXT_B_Q(x) (((x) & B_SIGN)? ((x) | ~((t_uint64) M8)): ((x) & M8))
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#define SEXT_W_Q(x) (((x) & W_SIGN)? ((x) | ~((t_uint64) M16)): ((x) & M16))
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#define SEXT_L_Q(x) (((x) & L_SIGN)? ((x) | ~((t_uint64) M32)): ((x) & M32))
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#define NEG_Q(x) ((~(x) + 1) & M64)
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#define ABS_Q(x) (((x) & Q_SIGN)? NEG_Q (x): (x))
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#define SIGN_BDSP 0x100000
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#define SIGN_MDSP 0x008000
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#define SEXT_MDSP(x) (((x) & SIGN_MDSP)? \
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((x) | ~((t_uint64) I_M_MDSP)): ((x) & I_M_MDSP))
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|
#define SEXT_BDSP(x) (((x) & SIGN_BDSP)? \
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|
((x) | ~((t_uint64) I_M_BDSP)): ((x) & I_M_BDSP))
|
|
|
|
/* Opcodes */
|
|
|
|
enum opcodes {
|
|
OP_PAL, OP_OPC01, OP_OPC02, OP_OPC03,
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|
OP_OPC04, OP_OPC05, OP_OPC06, OP_OPC07,
|
|
OP_LDA, OP_LDAH, OP_LDBU, OP_LDQ_U,
|
|
OP_LDWU, OP_STW, OP_STB, OP_STQ_U,
|
|
OP_IALU, OP_ILOG, OP_ISHFT, OP_IMUL,
|
|
OP_IFLT, OP_VAX, OP_IEEE, OP_FP,
|
|
OP_MISC, OP_PAL19, OP_JMP, OP_PAL1B,
|
|
OP_FLTI, OP_PAL1D, OP_PAL1E, OP_PAL1F,
|
|
OP_LDF, OP_LDG, OP_LDS, OP_LDT,
|
|
OP_STF, OP_STG, OP_STS, OP_STT,
|
|
OP_LDL, OP_LDQ, OP_LDL_L, OP_LDQ_L,
|
|
OP_STL, OP_STQ, OP_STL_C, OP_STQ_C,
|
|
OP_BR, OP_FBEQ, OP_FBLT, OP_FBLE,
|
|
OP_BSR, OP_FBNE, OP_FBGE, OP_FBGT,
|
|
OP_BLBC, OP_BEQ, OP_BLT, OP_BLE,
|
|
OP_BLBS, OP_BNE, OP_BGE, OP_BGT
|
|
};
|
|
|
|
/* Function prototypes */
|
|
|
|
uint32 ReadI (t_uint64 va);
|
|
t_uint64 ReadB (t_uint64 va);
|
|
t_uint64 ReadW (t_uint64 va);
|
|
t_uint64 ReadL (t_uint64 va);
|
|
t_uint64 ReadQ (t_uint64 va);
|
|
t_uint64 ReadAccL (t_uint64 va, uint32 acc);
|
|
t_uint64 ReadAccQ (t_uint64 va, uint32 acc);
|
|
INLINE t_uint64 ReadPB (t_uint64 pa);
|
|
INLINE t_uint64 ReadPW (t_uint64 pa);
|
|
INLINE t_uint64 ReadPL (t_uint64 pa);
|
|
INLINE t_uint64 ReadPQ (t_uint64 pa);
|
|
t_bool ReadIO (t_uint64 pa, t_uint64 *val, uint32 lnt);
|
|
void WriteB (t_uint64 va, t_uint64 dat);
|
|
void WriteW (t_uint64 va, t_uint64 dat);
|
|
void WriteL (t_uint64 va, t_uint64 dat);
|
|
void WriteQ (t_uint64 va, t_uint64 dat);
|
|
void WriteAccL (t_uint64 va, t_uint64 dat, uint32 acc);
|
|
void WriteAccQ (t_uint64 va, t_uint64 dat, uint32 acc);
|
|
INLINE void WritePB (t_uint64 pa, t_uint64 dat);
|
|
INLINE void WritePW (t_uint64 pa, t_uint64 dat);
|
|
INLINE void WritePL (t_uint64 pa, t_uint64 dat);
|
|
INLINE void WritePQ (t_uint64 pa, t_uint64 dat);
|
|
t_bool WriteIO (t_uint64 pa, t_uint64 val, uint32 lnt);
|
|
uint32 mmu_set_cm (uint32 mode);
|
|
void mmu_set_icm (uint32 mode);
|
|
void mmu_set_dcm (uint32 mode);
|
|
void arith_trap (uint32 trap, uint32 ir);
|
|
|
|
#endif
|