100 lines
3.7 KiB
C
100 lines
3.7 KiB
C
/* ipb.c: Intel IPB Processor simulator
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Copyright (c) 2017, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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01 Mar 18 - Original file.
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*/
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#include "system_defs.h"
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#define IPC 0
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/* function prototypes */
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t_stat SBC_config(void);
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t_stat SBC_reset (DEVICE *dptr);
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/* external function prototypes */
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extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
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extern uint8 multibus_get_mbyte(uint16 addr);
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extern void multibus_put_mbyte(uint16 addr, uint8 val);
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extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
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extern uint8 RAM_get_mbyte(uint16 addr);
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extern void RAM_put_mbyte(uint16 addr, uint8 val);
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extern t_stat i8251_cfg(uint8 base, uint8 devnum, uint8 dummy);
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extern t_stat i8251_reset(DEVICE *dptr);
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extern t_stat i8253_cfg(uint8 base, uint8 devnum, uint8 dummy);
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extern t_stat i8253_reset(DEVICE *dptr);
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extern t_stat i8255_cfg(uint8 base, uint8 devnum, uint8 dummy);
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extern t_stat i8255_reset(DEVICE *dptr);
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extern t_stat i8259_cfg(uint8 base, uint8 devnum, uint8 dummy);
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extern t_stat i8259_reset(DEVICE *dptr);
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extern t_stat EPROM_reset(DEVICE *dptr);
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extern t_stat RAM_reset(DEVICE *dptr);
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extern t_stat ipc_cont_reset(DEVICE *dptr);
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extern t_stat ipc_cont_cfg(uint8 base, uint8 devnum, uint8 dummy);
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extern t_stat ioc_cont_reset(DEVICE *dptr);
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extern t_stat ioc_cont_cfg(uint8 base, uint8 devnum, uint8 dummy);
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
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extern t_stat RAM_cfg(uint16 base, uint16 size, uint8 dummy);
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/* globals */
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int ipb_onetime = 0;
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/* extern globals */
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extern uint16 PCX; /* program counter */
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extern uint8 xack; /* XACK signal */
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extern UNIT i8255_unit;
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extern UNIT EPROM_unit;
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extern UNIT RAM_unit;
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extern UNIT ipc_cont_unit;
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extern UNIT ioc_cont_unit;
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extern DEVICE i8080_dev;
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extern DEVICE i8251_dev;
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extern DEVICE i8253_dev;
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extern DEVICE i8255_dev;
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extern DEVICE i8259_dev;
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extern DEVICE ipc_cont_dev;
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extern DEVICE ioc_cont_dev;
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t_stat SBC_config(void)
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{
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return SCPE_OK;
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}
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/* CPU reset routine
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put here to cause a reset of the entire IPC system */
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t_stat SBC_reset (DEVICE *dptr)
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{
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if (ipb_onetime == 0) {
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ipb_onetime++;
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}
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return SCPE_OK;
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}
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/* end of ipb.c */
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