26aa6de663
RESTRICTION: The PDP-15 FPP is only partially debugged. Do NOT enable this feature for normal operations. WARNING: The core simulator files (scp.c, sim_*.c) have been reorganized. Unzip V3.2-0 to an empty directory before attempting to compile the source. IMPORTANT: If you are compiling for UNIX, please read the notes for Ethernet very carefully. You may need to download a new version of the pcap library, or make changes to the makefile, to get Ethernet support to work. 1. New Features in 3.2-0 1.1 SCP and libraries - Added SHOW <device> RADIX command. - Added SHOW <device> MODIFIERS command. - Added SHOW <device> NAMES command. - Added SET/SHOW <device> DEBUG command. - Added sim_vm_parse_addr and sim_vm_fprint_addr optional interfaces. - Added REG_VMAD flag. - Split SCP into separate libraries for easier modification. - Added more room to the device and unit flag fields. - Changed terminal multiplexor library to support unlimited. number of async lines. 1.2 All DECtapes - Added STOP_EOR flag to enable end-of-reel error stop - Added device debug support. 1.3 Nova and Eclipse - Added QTY and ALM multiplexors (Bruce Ray). 1.4 LGP-30 - Added LGP-30/LGP-21 simulator. 1.5 PDP-11 - Added format, address increment inhibit, transfer overrun detection to RK. - Added device debug support to HK, RP, TM, TQ, TS. - Added DEUNA/DELUA (XU) support (Dave Hittner). - Add DZ per-line logging. 1.6 18b PDP's - Added support for 1-4 (PDP-9)/1-16 (PDP-15) additional terminals. 1.7 PDP-10 - Added DEUNA/DELUA (XU) support (Dave Hittner). 1.8 VAX - Added extended memory to 512MB (Mark Pizzolato). - Added RXV21 support. 2. Bugs Fixed in 3.2-0 2.1 SCP - Fixed double logging of SHOW BREAK (found by Mark Pizzolato). - Fixed implementation of REG_VMIO. 2.2 Nova and Eclipse - Fixed device enable/disable support (found by Bruce Ray). 2.3 PDP-1 - Fixed bug in LOAD (found by Mark Crispin). 2.4 PDP-10 - Fixed bug in floating point unpack. - Fixed bug in FIXR (found by Phil Stone, fixed by Chris Smith). 2.6 PDP-11 - Fixed bug in RQ interrupt control (found by Tom Evans). 2.6 PDP-18B - Fixed bug in PDP-15 XVM g_mode implementation. - Fixed bug in PDP-15 indexed address calculation. - Fixed bug in PDP-15 autoindexed address calculation. - Fixed bugs in FPP-15 instruction decode. - Fixed clock response to CAF. - Fixed bug in hardware read-in mode bootstrap. - Fixed PDP-15 XVM instruction decoding errors. 2.7 VAX - Fixed PC read fault in EXTxV. - Fixed PC write fault in INSV.
327 lines
9.5 KiB
Text
327 lines
9.5 KiB
Text
To: Users
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From: Bob Supnik
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Subj: GRI-909 Simulator Usage
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Date: 15-Feb-2004
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COPYRIGHT NOTICE
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The following copyright notice applies to both the SIMH source and binary:
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Original code published in 1993-2004, written by Robert M Supnik
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Copyright (c) 1993-2004, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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This memorandum documents the GRI-909 simulator.
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1. Simulator Files
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sim/ scp.h
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sim_console.h
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sim_defs.h
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sim_fio.h
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sim_rev.h
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sim_sock.h
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sim_timer.h
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sim_tmxr.h
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scp.c
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sim_console.c
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sim_fio.c
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sim_sock.c
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sim_timer.c
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sim_tmxr.c
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sim/gri/ gri_defs.h
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gri_cpu.c
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gri_stddev.c
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gri_sys.c
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2. GRI-909 Features
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The GRI-909 is configured as follows:
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device simulates
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name(s)
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CPU GRI-909 CPU with up to 32KW of memory
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HSR S42-004 high speed reader
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HSP S42-004 high speed punch
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TTI S42-001 Teletype input
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TTO S42-002 Teletype output
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RTC real-time clock
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The GRI-909 simulator implements the following unique stop conditions:
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- an unimplemented operator is referenced, and register
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STOP_OPR is set
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- an invalid interrupt request is made
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The LOAD commands has an optional argument to specify the load address:
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LOAD <filename> {<starting address>}
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The LOAD command loads a paper-tape bootstrap format file at the specified
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address. If no address is specified, loading starts at location 200. The
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DUMP command is not supported.
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2.1 CPU
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The only CPU options are the presence of the extended arithmetic operator
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and the size of main memory.
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SET CPU EAO enable extended arithmetic operator
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SET CPU NOEAO disable extended arithmetic operator
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SET CPU 4K set memory size = 4K
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SET CPU 8K set memory size = 8K
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SET CPU 12K set memory size = 12K
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SET CPU 16K set memory size = 16K
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SET CPU 20K set memory size = 20K
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SET CPU 24K set memory size = 24K
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SET CPU 28K set memory size = 28K
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SET CPU 32K set memory size = 32K
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If memory size is being reduced, and the memory being truncated contains
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non-zero data, the simulator asks for confirmation. Data in the truncated
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portion of memory is lost. Initial memory size is 32K.
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CPU registers include the visible state of the processor as well as the
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control registers for the interrupt system.
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name size comments
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SC 15 sequence counter
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AX 16 arithmetic operator input register 1
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AY 16 arithmetic operator input register 2
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AO 16 arithmetic operator output register
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TRP 16 TRP register
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MSR 16 machine status register
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ISR 16 interrupt status register
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BSW 16 byte swapper buffer
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BPK 16 byte packer buffer
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GR1..GR6 16 general registers 1 to 6
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BOV 1 bus overflow (MSR<15>)
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L 1 link (MSR<14>)
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FOA 2 arithmetic operator function (MSR<9:8>)
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AOV 1 arithmetic overflow (MSR<0>)
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IR 16 instruction register (read only)
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MA 16 memory address register (read only)
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SWR 16 switch register
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DR 16 display register
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THW 6 thumbwheels (selects operator displayed in DR)
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IREQ 16 interrupt requests
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ION 1 interrupts enabled
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INODEF 1 interrupts not deferred
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BKP 1 breakpoint request
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SCQ[0:63] 15 SC prior to last jump or interrupt;
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most recent SC change first
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STOP_OPR 1 stop on undefined operator
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WRU 8 interrupt character
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2.2 Programmed I/O Devices
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2.2.1 S42-004 High Speed Reader (HSR)
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The paper tape reader (HSR) reads data from or a disk file. The POS
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register specifies the number of the next data item to be read.
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Thus, by changing POS, the user can backspace or advance the reader.
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The paper tape reader implements these registers:
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name size comments
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BUF 8 last data item processed
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IRDY 1 device ready flag
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IENB 1 device interrupt enable flag
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POS 32 position in the input file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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0 out of tape
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end of file 1 report error and stop
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0 out of tape
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OS I/O error x report error and stop
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2.2.2 S42-006 High Speed Punch (HSP)
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The paper tape punch (HSP) writes data to a disk file. The POS
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register specifies the number of the next data item to be written.
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Thus, by changing POS, the user can backspace or advance the punch.
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The paper tape punch implements these registers:
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name size comments
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BUF 8 last data item processed
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ORDY 1 device ready flag
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IENB 1 device interrupt enable flag
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POS 32 position in the output file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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0 out of tape
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OS I/O error x report error and stop
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2.2.3 S42-001 Teletype Input (TTI)
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The Teletype interfaces (TTI, TTO) can be set to one of three modes:
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KSR, 7B, or 8B. In KSR mode, lower case input and output characters
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are automatically converted to upper case, and the high order bit is
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forced to one on input. In 7B mode, input and output characters are
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masked to 7 bits. In 8B mode, characters are not modified. Changing
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the mode of either interface changes both. The default mode is KSR.
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The Teletype input (TTI) polls the console keyboard for input. It
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implements these registers:
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name size comments
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BUF 8 last data item processed
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IRDY 1 device ready flag
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IENB 1 device interrupt enable flag
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POS 32 position in the output file
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TIME 24 keyboard polling interval
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2.2.4 S42-002 Teletype Output (TTO)
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The Teletype output (TTO) writes to the simulator console window. It
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implements these registers:
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name size comments
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BUF 8 last data item processed
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ORDY 1 device ready flag
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IENB 1 device interrupt enable flag
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POS 32 number of characters output
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TIME 24 time from I/O initiation to interrupt
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2.2.5 Real-Time Clock (RTC)
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The real-time clock (CLK) implements these registers:
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name size comments
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RDY 1 device ready flag
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IENB 1 interrupt enable flag
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TIME 24 clock interval
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The real-time clock autocalibrates; the clock interval is adjusted up or
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down so that the clock tracks actual elapsed time.
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2.3 Symbolic Display and Input
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The GRI-909 simulator implements symbolic display and input. Display is
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controlled by command line switches:
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-a display as ASCII character
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-c display as packed ASCII characters
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-m display instruction mnemonics
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Input parsing is controlled by the first character typed in or by command
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line switches:
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' or -a ASCII character
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" or -c two packed ASCII characters
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alphabetic instruction mnemonic
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numeric octal number
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Instruction input uses modified GRI-909 basic assembler syntax. There are
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thirteen different instruction formats. Operators, functions, and tests may
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be octal or symbolic; jump conditions and bus operators are always symbolic.
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Function out, general
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Syntax: FO function,operator
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Function symbols: INP, IRDY, ORDY, STRT
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Example: FO ORDY,TTO
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Function out, named
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Syntax: FO{M|I|A} function
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Function symbols: M: CLL, CML, STL, HLT; I: ICF, ICO;
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A: ADD, AND, XOR, OR
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Example: FOA XOR
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Sense function, general
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Syntax: SF operator,{NOT} tests
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Test symbols: IRDY, ORDY
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Example: SF HSR,IRDY
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Sense function, named
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Syntax: SF{M|A} {NOT} tests
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Test symbols: M: POK BOV LNK; A: SOV AOV
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Example: SFM NOT BOV
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Register to register
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Syntax: RR{C} src,{bus op,}dst
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Bus op symbols: P1, L1, R1
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Example: RRC AX,P1,AY
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Zero to register
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Syntax: ZR{C} {bus op,}dst
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Bus op symbols: P1, L1, R1
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Example: ZR P1,GR1
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Register to self
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Syntax: RS{C} dst{,bus op}
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Bus op symbols: P1, L1, R1
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Example: RS AX,L1
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Jump unconditional or named condition
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Syntax: J{U|O|N}{D} address
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Example: JUD 1400
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Jump conditional
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Syntax: JC{D} src,cond,address
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Cond symbols: NEVER,ALWAYS,ETZ,NEZ,LTZ,GEZ,LEZ,GTZ
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Example: JC AX,LEZ,200
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Register to memory
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syntax: RM{I|D|ID} src,{bus op,}address
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Bus op symbols: P1, L1, R1
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Example: RMD AX,P1,1315
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Zero to memory
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Syntax: ZM{I|D|ID} {bus op,}address
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Bus op symbols: P1, L1, R1
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Example: ZM P1,5502
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Memory to register
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Syntax: MR{I|D|ID} address,{bus op,}dst
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Bus op symbols: P1, L1, R1
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Example: MRI 1405,GR6
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Memory to self:
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Syntax: MS{I|D|ID} address{,bus op}
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Bus op symbols: P1, L1, R1
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Example: MS 3333,P1
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