RESTRICTION: The PDP-15 FPP is only partially debugged. Do NOT enable this feature for normal operations. WARNING: The core simulator files (scp.c, sim_*.c) have been reorganized. Unzip V3.2-0 to an empty directory before attempting to compile the source. IMPORTANT: If you are compiling for UNIX, please read the notes for Ethernet very carefully. You may need to download a new version of the pcap library, or make changes to the makefile, to get Ethernet support to work. 1. New Features in 3.2-0 1.1 SCP and libraries - Added SHOW <device> RADIX command. - Added SHOW <device> MODIFIERS command. - Added SHOW <device> NAMES command. - Added SET/SHOW <device> DEBUG command. - Added sim_vm_parse_addr and sim_vm_fprint_addr optional interfaces. - Added REG_VMAD flag. - Split SCP into separate libraries for easier modification. - Added more room to the device and unit flag fields. - Changed terminal multiplexor library to support unlimited. number of async lines. 1.2 All DECtapes - Added STOP_EOR flag to enable end-of-reel error stop - Added device debug support. 1.3 Nova and Eclipse - Added QTY and ALM multiplexors (Bruce Ray). 1.4 LGP-30 - Added LGP-30/LGP-21 simulator. 1.5 PDP-11 - Added format, address increment inhibit, transfer overrun detection to RK. - Added device debug support to HK, RP, TM, TQ, TS. - Added DEUNA/DELUA (XU) support (Dave Hittner). - Add DZ per-line logging. 1.6 18b PDP's - Added support for 1-4 (PDP-9)/1-16 (PDP-15) additional terminals. 1.7 PDP-10 - Added DEUNA/DELUA (XU) support (Dave Hittner). 1.8 VAX - Added extended memory to 512MB (Mark Pizzolato). - Added RXV21 support. 2. Bugs Fixed in 3.2-0 2.1 SCP - Fixed double logging of SHOW BREAK (found by Mark Pizzolato). - Fixed implementation of REG_VMIO. 2.2 Nova and Eclipse - Fixed device enable/disable support (found by Bruce Ray). 2.3 PDP-1 - Fixed bug in LOAD (found by Mark Crispin). 2.4 PDP-10 - Fixed bug in floating point unpack. - Fixed bug in FIXR (found by Phil Stone, fixed by Chris Smith). 2.6 PDP-11 - Fixed bug in RQ interrupt control (found by Tom Evans). 2.6 PDP-18B - Fixed bug in PDP-15 XVM g_mode implementation. - Fixed bug in PDP-15 indexed address calculation. - Fixed bug in PDP-15 autoindexed address calculation. - Fixed bugs in FPP-15 instruction decode. - Fixed clock response to CAF. - Fixed bug in hardware read-in mode bootstrap. - Fixed PDP-15 XVM instruction decoding errors. 2.7 VAX - Fixed PC read fault in EXTxV. - Fixed PC write fault in INSV.
509 lines
17 KiB
C
509 lines
17 KiB
C
/* sds_mux.c: SDS 940 terminal multiplexor simulator
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Copyright (c) 2001-2004, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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mux terminal multiplexor
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05-Jan-04 RMS Revised for tmxr library changes
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09-May-03 RMS Added network device flag
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This module implements up to 32 individual serial interfaces, representing
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either the project Genie terminal multiplexor or the SDS 940 CTE option.
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*/
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#include "sds_defs.h"
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#include "sim_sock.h"
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#include "sim_tmxr.h"
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#include <ctype.h>
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#define PROJ_GENIE (cpu_unit.flags & UNIT_GENIE)
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#define MUX_NUMLIN mux_desc.lines
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#define MUX_LINES 32 /* lines */
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#define MUX_FLAGS 4 /* intr per line */
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#define MUX_FLAGMASK (MUX_FLAGS - 1)
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#define MUX_SCANMAX (MUX_LINES * MUX_FLAGS) /* flags to scan */
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#define MUX_SCANMASK (MUX_SCANMAX - 1)
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#define UNIT_V_UC (UNIT_V_UF + 0) /* UC only */
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#define UNIT_UC (1 << UNIT_V_UC)
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#define MUX_INIT_POLL 8000
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#define MUXL_WAIT 500
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#define MUX_SETFLG(l,x) mux_flags[((l) * MUX_FLAGS) + (x)] = 1
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#define MUX_SETINT(x) int_req = int_req | (INT_MUXR >> (x))
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#define MUX_CLRINT(x) int_req = int_req & ~(INT_MUXR >> (x))
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/* PIN/POT */
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#define P_V_CHAR 16 /* char */
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#define P_M_CHAR 0377
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#define P_CHAR(x) (((x) >> P_V_CHAR) & P_M_CHAR)
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#define PIN_OVR 000100000 /* overrun */
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#define POT_NOX 000100000 /* no xmit */
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#define POT_XMI 000040000 /* xmit int */
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#define POT_GLNE 000020000 /* Genie: enable */
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#define POT_SCDT 000020000 /* 940: clr DTR */
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#define P_V_CHAN 0 /* channel */
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#define P_M_CHAN (MUX_LINES - 1)
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#define P_CHAN(x) (((x) >> P_V_CHAN) & P_M_CHAN)
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/* SKS 940 */
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#define SKS_XBE 000001000 /* xmt buf empty */
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#define SKS_CRO 000000400 /* carrier on */
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#define SKS_DSR 000000200 /* data set ready */
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#define SKS_CHAN(x) P_CHAN(x)
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/* SKS Genie */
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#define SKG_V_CHAN 7
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#define SKG_M_CHAN (MUX_LINES - 1)
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#define SKG_CHAN(x) (((x) >> SKG_V_CHAN) & SKG_M_CHAN)
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/* Flags */
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#define MUX_FRCV 0 /* receive */
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#define MUX_FXMT 1 /* transmit */
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#define MUX_FCRN 2 /* carrier on */
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#define MUX_FCRF 3 /* carrier off */
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/* Line status */
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#define MUX_SCHP 001 /* char pending */
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#define MUX_SOVR 002 /* overrun */
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#define MUX_SLNE 004 /* line enabled */
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#define MUX_SXIE 010 /* xmt int enab */
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#define MUX_SCRO 020 /* carrier on */
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#define MUX_SDSR 040 /* data set ready */
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/* Data */
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extern uint32 alert, int_req;
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extern int32 stop_invins, stop_invdev, stop_inviop;
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extern UNIT cpu_unit;
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uint8 mux_rbuf[MUX_LINES]; /* rcv buf */
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uint8 mux_xbuf[MUX_LINES]; /* xmt buf */
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uint8 mux_sta[MUX_LINES]; /* status */
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uint8 mux_flags[MUX_SCANMAX]; /* flags */
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uint32 mux_tps = 100; /* polls/second */
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uint32 mux_scan = 0; /* scanner */
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uint32 mux_slck = 0; /* scanner locked */
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TMLN mux_ldsc[MUX_LINES] = { 0 }; /* line descriptors */
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TMXR mux_desc = { MUX_LINES, 0, 0, mux_ldsc }; /* mux descriptor */
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t_stat mux (uint32 fnc, uint32 inst, uint32 *dat);
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t_stat muxi_svc (UNIT *uptr);
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t_stat muxo_svc (UNIT *uptr);
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t_stat mux_reset (DEVICE *dptr);
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t_stat mux_attach (UNIT *uptr, char *cptr);
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t_stat mux_detach (UNIT *uptr);
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t_stat mux_summ (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat mux_show (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat mux_vlines (UNIT *uptr, int32 val, char *cptr, void *desc);
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void mux_reset_ln (int32 ln);
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void mux_scan_next (void);
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/* MUX data structures
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mux_dev MUX device descriptor
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mux_unit MUX unit descriptor
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mux_reg MUX register list
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mux_mod MUX modifiers list
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*/
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DIB mux_dib = { -1, DEV3_GMUX, 0, NULL, &mux };
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REG mux_nlreg = { DRDATA (NLINES, MUX_NUMLIN, 6), PV_LEFT };
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UNIT mux_unit = { UDATA (&muxi_svc, UNIT_ATTABLE, 0), MUX_INIT_POLL };
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REG mux_reg[] = {
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{ BRDATA (STA, mux_sta, 8, 6, MUX_LINES) },
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{ BRDATA (RBUF, mux_rbuf, 8, 8, MUX_LINES) },
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{ BRDATA (XBUF, mux_xbuf, 8, 8, MUX_LINES) },
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{ BRDATA (INT, mux_flags, 8, 1, MUX_SCANMAX) },
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{ ORDATA (SCAN, mux_scan, 7) },
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{ FLDATA (SLCK, mux_slck, 0) },
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{ DRDATA (TPS, mux_tps, 8), REG_NZ + PV_LEFT },
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{ NULL } };
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MTAB mux_mod[] = {
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{ MTAB_XTD | MTAB_VDV | MTAB_VAL, 0, "lines", "LINES",
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&mux_vlines, NULL, &mux_nlreg },
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{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &mux_desc },
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{ UNIT_ATT, UNIT_ATT, "connections", NULL, NULL, &mux_summ },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
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NULL, &mux_show, NULL },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
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NULL, &mux_show, NULL },
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{ 0 } };
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DEVICE mux_dev = {
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"MUX", &mux_unit, mux_reg, mux_mod,
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1, 10, 31, 1, 8, 8,
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&tmxr_ex, &tmxr_dep, &mux_reset,
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NULL, &mux_attach, &mux_detach,
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&mux_dib, DEV_NET | DEV_DISABLE };
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/* MUXL data structures
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muxl_dev MUXL device descriptor
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muxl_unit MUXL unit descriptor
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muxl_reg MUXL register list
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muxl_mod MUXL modifiers list
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*/
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UNIT muxl_unit[] = {
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT },
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{ UDATA (&muxo_svc, UNIT_UC, 0), MUXL_WAIT } };
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MTAB muxl_mod[] = {
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{ UNIT_UC, 0, "lower case", "LC", NULL },
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{ UNIT_UC, UNIT_UC, "upper case", "UC", NULL },
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{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
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&tmxr_set_log, &tmxr_show_log, &mux_desc },
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{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
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&tmxr_set_nolog, NULL, &mux_desc },
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{ 0 } };
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REG muxl_reg[] = {
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{ URDATA (TIME, muxl_unit[0].wait, 10, 24, 0,
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MUX_LINES, REG_NZ + PV_LEFT) },
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{ NULL } };
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DEVICE muxl_dev = {
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"MUXL", muxl_unit, muxl_reg, muxl_mod,
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MUX_LINES, 10, 31, 1, 8, 8,
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NULL, NULL, &mux_reset,
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NULL, NULL, NULL,
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NULL, 0 };
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/* MUX: IO routine */
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/* Mux routine - EOM 30001 or EOM 77777,2 */
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t_stat mux (uint32 fnc, uint32 inst, uint32 *dat)
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{
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uint32 ln;
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switch (fnc) {
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case IO_CONN: /* connect */
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if ((PROJ_GENIE && (inst == 000230001)) || /* set alert */
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(!PROJ_GENIE && (inst == 020277777))) alert = POT_MUX;
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else CRETINS;
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break;
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case IO_SKS: /* skip */
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if (PROJ_GENIE && ((inst & 077770077) == 004030001)) {
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ln = SKG_CHAN (inst); /* get line */
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if (!sim_is_active (&muxl_unit[ln])) *dat = 1; }
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else if (!PROJ_GENIE && ((inst & 077776000) == 024076000)) {
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ln = SKS_CHAN (inst); /* get line */
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if (inst & (SKS_XBE|SKS_CRO|SKS_DSR)) *dat = 1;
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if (((inst & SKS_XBE) && sim_is_active (&muxl_unit[ln])) ||
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((inst & SKS_CRO) && !(mux_sta[ln] & MUX_SCRO)) ||
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((inst & SKS_DSR) && !(mux_sta[ln] & MUX_SDSR)))
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*dat = 0; } /* no skip if fail */
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else CRETINS;
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default:
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return SCPE_IERR; } /* end case */
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return SCPE_OK;
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}
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/* PIN routine */
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t_stat pin_mux (uint32 num, uint32 *dat)
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{
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uint32 ln = mux_scan >> 2;
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uint32 flag = mux_scan & MUX_FLAGMASK;
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mux_scan = mux_scan & MUX_SCANMASK; /* mask scan */
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mux_flags[mux_scan] = 0; /* clear flag */
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if (flag == MUX_FRCV) { /* rcv event? */
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*dat = ln | ((uint32) mux_rbuf[ln] << P_V_CHAR) | /* line + char + */
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((mux_sta[ln] & MUX_SOVR)? PIN_OVR: 0); /* overrun */
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mux_sta[ln] = mux_sta[ln] & ~(MUX_SCHP | MUX_SOVR); }
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else *dat = ln; /* just line */
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mux_slck = 0; /* unlock scanner */
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mux_scan_next (); /* kick scanner */
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return SCPE_OK;
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}
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t_stat pot_mux (uint32 num, uint32 *dat)
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{
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uint32 ln = P_CHAN (*dat);
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uint32 chr = P_CHAR (*dat);
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if (PROJ_GENIE && ((*dat & POT_GLNE) == 0)) { /* Genie disable? */
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mux_sta[ln] = mux_sta[ln] & ~MUX_SLNE; /* clear status */
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mux_ldsc[ln].rcve = 0; }
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else if (!PROJ_GENIE && (*dat & POT_SCDT)) { /* SDS disable? */
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if (mux_ldsc[ln].conn) { /* connected? */
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tmxr_linemsg (&mux_ldsc[ln], "\r\nLine hangup\r\n");
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tmxr_reset_ln (&mux_ldsc[ln]); /* reset line */
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mux_reset_ln (ln); /* reset state */
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MUX_SETFLG (ln, MUX_FCRF); /* set carrier off */
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mux_scan_next (); } /* kick scanner */
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mux_sta[ln] = mux_sta[ln] & ~MUX_SLNE; /* clear status */
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mux_ldsc[ln].rcve = 0; }
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else { /* enabled */
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if ((*dat & POT_NOX) == 0) { /* output char? */
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mux_xbuf[ln] = chr; /* store char */
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sim_activate (&muxl_unit[ln], muxl_unit[ln].wait); }
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if (*dat & POT_XMI) mux_sta[ln] = mux_sta[ln] | MUX_SXIE;
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else mux_sta[ln] = mux_sta[ln] & ~MUX_SXIE;
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mux_sta[ln] = mux_sta[ln] | MUX_SLNE; /* line is enabled */
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mux_ldsc[ln].rcve = 1; }
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return SCPE_OK;
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}
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/* Unit service - receive side
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Poll all active lines for input
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Poll for new connections
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*/
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t_stat muxi_svc (UNIT *uptr)
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{
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int32 ln, c, t;
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if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK; /* attached? */
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t = sim_rtcn_calb (mux_tps, TMR_MUX); /* calibrate */
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sim_activate (uptr, t); /* continue poll */
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ln = tmxr_poll_conn (&mux_desc); /* look for connect */
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if (ln >= 0) { /* got one? */
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if (!PROJ_GENIE && (mux_sta[ln] & MUX_SLNE)) { /* modem & DTR? */
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mux_sta[ln] = mux_sta[ln] | (MUX_SCRO|MUX_SDSR);/* carrier on */
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MUX_SETFLG (ln, MUX_FCRN); /* set carr on flag */
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mux_scan_next (); } /* kick scanner */
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mux_ldsc[ln].rcve = 1; } /* set rcv enable */
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tmxr_poll_rx (&mux_desc); /* poll for input */
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for (ln = 0; ln < MUX_NUMLIN; ln++) { /* loop thru lines */
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if (mux_ldsc[ln].conn) { /* connected? */
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if (c = tmxr_getc_ln (&mux_ldsc[ln])) { /* get char */
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if (mux_sta[ln] & MUX_SCHP) /* already got one? */
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mux_sta[ln] = mux_sta[ln] | MUX_SOVR; /* overrun */
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else mux_sta[ln] = mux_sta[ln] | MUX_SCHP; /* char pending */
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c = c & 0177; /* mask to 7b */
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if ((muxl_unit[ln].flags & UNIT_UC) && /* cvt to UC? */
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islower (c & 0x7F)) c = toupper (c);
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mux_rbuf[ln] = c; /* save char */
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MUX_SETFLG (ln, MUX_FRCV); /* set rcv flag */
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mux_scan_next (); } } /* kick scanner */
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else mux_sta[ln] = 0; /* disconnected */
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} /* end for */
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return SCPE_OK;
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}
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/* Unit service - transmit side */
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t_stat muxo_svc (UNIT *uptr)
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{
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int32 c;
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uint32 ln = uptr - muxl_unit; /* line # */
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if (mux_ldsc[ln].conn) { /* connected? */
|
||
if (mux_ldsc[ln].xmte) { /* xmt enabled? */
|
||
c = mux_xbuf[ln] & 0177; /* get char */
|
||
if ((muxl_unit[ln].flags & UNIT_UC) && islower (c))
|
||
c = toupper (c); /* cvt to UC? */
|
||
tmxr_putc_ln (&mux_ldsc[ln], c); /* output char */
|
||
tmxr_poll_tx (&mux_desc); } /* poll xmt */
|
||
else { /* buf full */
|
||
tmxr_poll_tx (&mux_desc); /* poll xmt */
|
||
sim_activate (uptr, muxl_unit[ln].wait); /* wait */
|
||
return SCPE_OK; } }
|
||
if (mux_sta[ln] & MUX_SXIE) {
|
||
MUX_SETFLG (ln, MUX_FXMT); /* set flag */
|
||
mux_scan_next (); } /* kick scanner */
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Kick scanner */
|
||
|
||
void mux_scan_next (void)
|
||
{
|
||
int32 i;
|
||
|
||
if (mux_slck) return; /* locked? */
|
||
for (i = 0; i < MUX_SCANMAX; i++) { /* scan flags */
|
||
mux_scan = (mux_scan + 1) & MUX_SCANMASK; /* next flag */
|
||
if (mux_flags[mux_scan]) { /* flag set? */
|
||
mux_slck = 1; /* lock scanner */
|
||
MUX_SETINT (mux_scan & MUX_FLAGMASK); /* request int */
|
||
return; }
|
||
}
|
||
return;
|
||
}
|
||
|
||
/* Reset routine */
|
||
|
||
t_stat mux_reset (DEVICE *dptr)
|
||
{
|
||
int32 i, t;
|
||
|
||
if (mux_dev.flags & DEV_DIS) /* master disabled? */
|
||
muxl_dev.flags = muxl_dev.flags | DEV_DIS; /* disable lines */
|
||
else muxl_dev.flags = muxl_dev.flags & ~DEV_DIS;
|
||
if (mux_unit.flags & UNIT_ATT) { /* master att? */
|
||
if (!sim_is_active (&mux_unit)) {
|
||
t = sim_rtcn_init (mux_unit.wait, TMR_MUX);
|
||
sim_activate (&mux_unit, t); } } /* activate */
|
||
else sim_cancel (&mux_unit); /* else stop */
|
||
for (i = 0; i < MUX_LINES; i++) mux_reset_ln (i);
|
||
for (i = 0; i < MUX_FLAGS; i++) MUX_CLRINT (i); /* clear all ints */
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Attach master unit */
|
||
|
||
t_stat mux_attach (UNIT *uptr, char *cptr)
|
||
{
|
||
t_stat r;
|
||
int32 t;
|
||
|
||
r = tmxr_attach (&mux_desc, uptr, cptr); /* attach */
|
||
if (r != SCPE_OK) return r; /* error */
|
||
t = sim_rtcn_init (mux_unit.wait, TMR_MUX);
|
||
sim_activate (uptr, t); /* start poll */
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Detach master unit */
|
||
|
||
t_stat mux_detach (UNIT *uptr)
|
||
{
|
||
int32 i;
|
||
t_stat r;
|
||
|
||
r = tmxr_detach (&mux_desc, uptr); /* detach */
|
||
for (i = 0; i < MUX_LINES; i++) mux_ldsc[i].rcve = 0; /* disable rcv */
|
||
sim_cancel (uptr); /* stop poll */
|
||
return r;
|
||
}
|
||
|
||
/* Show summary processor */
|
||
|
||
t_stat mux_summ (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||
{
|
||
int32 i, t;
|
||
|
||
for (i = t = 0; i < MUX_LINES; i++) t = t + (mux_ldsc[i].conn != 0);
|
||
if (t == 1) fprintf (st, "1 connection");
|
||
else fprintf (st, "%d connections", t);
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* SHOW CONN/STAT processor */
|
||
|
||
t_stat mux_show (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||
{
|
||
int32 i;
|
||
|
||
for (i = 0; (i < MUX_LINES) && (mux_ldsc[i].conn == 0); i++) ;
|
||
if (i < MUX_LINES) {
|
||
for (i = 0; i < MUX_LINES; i++) {
|
||
if (mux_ldsc[i].conn)
|
||
if (val) tmxr_fconns (st, &mux_ldsc[i], i);
|
||
else tmxr_fstats (st, &mux_ldsc[i], i); } }
|
||
else fprintf (st, "all disconnected\n");
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Change number of lines */
|
||
|
||
t_stat mux_vlines (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||
{
|
||
int32 newln, i, t;
|
||
t_stat r;
|
||
|
||
if (cptr == NULL) return SCPE_ARG;
|
||
newln = get_uint (cptr, 10, MUX_LINES, &r);
|
||
if ((r != SCPE_OK) || (newln == MUX_NUMLIN)) return r;
|
||
if (newln == 0) return SCPE_ARG;
|
||
if (newln < MUX_NUMLIN) {
|
||
for (i = newln, t = 0; i < MUX_NUMLIN; i++) t = t | mux_ldsc[i].conn;
|
||
if (t && !get_yn ("This will disconnect users; proceed [N]?", FALSE))
|
||
return SCPE_OK;
|
||
for (i = newln; i < MUX_NUMLIN; i++) {
|
||
if (mux_ldsc[i].conn) {
|
||
tmxr_linemsg (&mux_ldsc[i], "\r\nOperator disconnected line\r\n");
|
||
tmxr_reset_ln (&mux_ldsc[i]); } /* reset line */
|
||
muxl_unit[i].flags = muxl_unit[i].flags | UNIT_DIS;
|
||
mux_reset_ln (i); }
|
||
}
|
||
else {
|
||
for (i = MUX_NUMLIN; i < newln; i++) {
|
||
muxl_unit[i].flags = muxl_unit[i].flags & ~UNIT_DIS;
|
||
mux_reset_ln (i); }
|
||
}
|
||
MUX_NUMLIN = newln;
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Reset an individual line */
|
||
|
||
void mux_reset_ln (int32 ln)
|
||
{
|
||
int32 flg = ln * MUX_FLAGS;
|
||
|
||
if (mux_ldsc[ln].conn) mux_sta[ln] = MUX_SCRO | MUX_SDSR;
|
||
else mux_sta[ln] = 0;
|
||
sim_cancel (&muxl_unit[ln]);
|
||
mux_flags[flg + MUX_FRCV] = 0;
|
||
mux_flags[flg + MUX_FXMT] = 0;
|
||
mux_flags[flg + MUX_FCRN] = 0;
|
||
mux_flags[flg + MUX_FCRF] = 0;
|
||
return;
|
||
}
|