691 lines
21 KiB
C
691 lines
21 KiB
C
/* vax730_sys.c: VAX 11/730 system-specific logic
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Copyright (c) 2010-2011, Matt Burke
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This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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This module contains the VAX 11/730 system-specific registers and devices.
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sysb system bus controller
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29-Mar-2011 MB First Version
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*/
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#include "vax_defs.h"
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#ifdef DONT_USE_INTERNAL_ROM
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#define BOOT_CODE_FILENAME "vmb.exe"
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#define BOOT_CODE_ARRAY NULL
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#define BOOT_CODE_SIZE 0
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#else /* !DONT_USE_INTERNAL_ROM */
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#include "vax_vmb_exe.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */
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#endif /* DONT_USE_INTERNAL_ROM */
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static char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */
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int32 sys_model = 0;
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/* VAX-11/730 boot device definitions */
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struct boot_dev {
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char *name;
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int32 code;
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int32 let;
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};
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static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
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static t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
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static struct boot_dev boot_tab[] = {
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{ "HK", BOOT_HK, 0 },
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{ "RL", BOOT_RL, 0 },
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{ "RQ", BOOT_UDA, 1 << 24 },
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{ "RQB", BOOT_UDA, 1 << 24 },
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{ "RQC", BOOT_UDA, 1 << 24 },
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{ "RQD", BOOT_UDA, 1 << 24 },
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{ "TQ", BOOT_TK, 1 << 24 },
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{ "TD", BOOT_TD, 0 },
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{ "RB", BOOT_RB, 0 },
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{ NULL }
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};
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extern int32 R[16];
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extern int32 PSL;
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extern int32 ASTLVL, SISR;
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extern int32 mapen, pme, trpirq;
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extern int32 in_ie;
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extern int32 mchk_va, mchk_ref;
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extern int32 crd_err, mem_err, hlt_pin;
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extern int32 tmr_int, tti_int, tto_int, csi_int, cso_int;
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extern jmp_buf save_env;
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extern int32 p1;
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t_stat sysb_reset (DEVICE *dptr);
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char *sysb_description (DEVICE *dptr);
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t_stat vax730_boot (int32 flag, char *ptr);
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t_stat vax730_boot_parse (int32 flag, char *ptr);
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t_stat cpu_boot (int32 unitno, DEVICE *dptr);
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extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
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extern int32 iccs_rd (void);
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extern int32 nicr_rd (void);
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extern int32 icr_rd (t_bool interp);
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extern int32 todr_rd (void);
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extern int32 rxcs_rd (void);
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extern int32 rxdb_rd (void);
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extern int32 txcs_rd (void);
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extern int32 csrs_rd (void);
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extern int32 csrd_rd (void);
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extern int32 csts_rd (void);
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extern void iccs_wr (int32 dat);
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extern void nicr_wr (int32 dat);
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extern void todr_wr (int32 dat);
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extern void rxcs_wr (int32 dat);
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extern void txcs_wr (int32 dat);
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extern void txdb_wr (int32 dat);
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extern void csrs_wr (int32 dat);
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extern void csts_wr (int32 dat);
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extern void cstd_wr (int32 dat);
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extern void init_ubus_tab (void);
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extern t_stat build_ubus_tab (DEVICE *dptr, DIB *dibp);
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extern int32 ubamap_rd (int32 pa);
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extern void ubamap_wr (int32 pa, int32 val, int32 lnt);
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extern t_bool uba_eval_int (int32 lvl);
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extern int32 uba_get_ubvector (int32 lvl);
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/* SYSB data structures
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sysb_dev SYSB device descriptor
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sysb_unit SYSB unit
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sysb_reg SYSB register list
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*/
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UNIT sysb_unit = { UDATA (NULL, 0, 0) };
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REG sysb_reg[] = {
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{ BRDATA (BOOTCMD, cpu_boot_cmd, 16, 8, CBUFSIZE), REG_HRO },
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{ NULL }
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};
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DEVICE sysb_dev = {
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"SYSB", &sysb_unit, sysb_reg, NULL,
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1, 16, 16, 1, 16, 8,
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NULL, NULL, &sysb_reset,
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NULL, NULL, NULL,
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NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
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&sysb_description
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};
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/* Special boot command, overrides regular boot */
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CTAB vax730_cmd[] = {
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{ "BOOT", &vax730_boot, RU_BOOT,
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"bo{ot} <device>{/R5:flg} boot device\n"
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" type HELP CPU to see bootable devices\n", NULL, &run_cmd_message },
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{ NULL }
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};
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/* The VAX 11/730 has two sources of interrupts
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- internal device interrupts (CPU, console, clock, console storage)
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- external device interrupts (Unibus)
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Find highest priority vectorable interrupt */
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int32 eval_int (void)
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{
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int32 ipl = PSL_GETIPL (PSL);
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int32 i, t;
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static const int32 sw_int_mask[IPL_SMAX] = {
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0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */
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0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */
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0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */
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0xE000, 0xC000, 0x8000 /* C - E */
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};
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if (hlt_pin) /* hlt pin int */
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return IPL_HLTPIN;
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if ((ipl < IPL_CLKINT) && tmr_int) /* clock int */
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return IPL_CLKINT;
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for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */
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if (i <= ipl) /* at ipl? no int */
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return 0;
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if (uba_eval_int(i - IPL_HMIN))
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return i;
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}
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if ((ipl < IPL_TTINT) && (tti_int || tto_int)) /* console int */
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return IPL_TTINT;
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if ((ipl < IPL_CSINT) && (csi_int || cso_int)) /* console storage int */
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return IPL_CSINT;
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if (ipl >= IPL_SMAX) /* ipl >= sw max? */
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return 0;
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if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */
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return 0;
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for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */
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if ((t >> i) & 1) /* req != 0? int */
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return i;
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}
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return 0;
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}
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/* Return vector for highest priority hardware interrupt at IPL lvl */
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int32 get_vector (int32 lvl)
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{
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int32 l;
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if (lvl == IPL_CLKINT) { /* clock? */
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tmr_int = 0; /* clear req */
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return SCB_INTTIM; /* return vector */
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}
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if (lvl > IPL_HMAX) { /* error req lvl? */
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ABORT (STOP_UIPL); /* unknown intr */
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}
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if ((lvl <= IPL_HMAX) && (lvl >= IPL_HMIN)) { /* nexus? */
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l = lvl - IPL_HMIN;
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if (uba_eval_int(l))
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return uba_get_ubvector(l);
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}
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if (lvl == IPL_TTINT) { /* console? */
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if (tti_int) { /* input? */
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tti_int = 0; /* clear req */
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return SCB_TTI; /* return vector */
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}
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if (tto_int) { /* output? */
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tto_int = 0; /* clear req */
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return SCB_TTO; /* return vector */
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}
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}
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if (lvl == IPL_CSINT) { /* console storage? */
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if (csi_int) { /* input? */
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csi_int = 0; /* clear req */
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return SCB_CSI; /* return vector */
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}
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if (cso_int) { /* output? */
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cso_int = 0; /* clear req */
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return SCB_CSO; /* return vector */
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}
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}
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return 0;
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}
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/* Read 730-specific IPR's */
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int32 ReadIPR (int32 rg)
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{
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int32 val;
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switch (rg) {
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case MT_ICCS: /* ICCS */
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val = iccs_rd ();
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break;
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case MT_NICR: /* NICR */
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val = nicr_rd ();
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break;
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case MT_ICR: /* ICR */
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val = icr_rd (FALSE);
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break;
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case MT_TODR: /* TODR */
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val = todr_rd ();
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break;
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case MT_ACCS: /* ACCS (not impl) */
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val = 0;
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break;
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case MT_RXCS: /* RXCS */
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val = rxcs_rd ();
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break;
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case MT_RXDB: /* RXDB */
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val = rxdb_rd ();
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break;
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case MT_TXCS: /* TXCS */
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val = txcs_rd ();
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break;
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case MT_SID: /* SID */
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val = VAX730_SID | VAX730_MICRO;
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break;
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case MT_MCESR: /* MCESR (not impl) */
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val = 0;
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break;
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case MT_CSRS: /* CSRS */
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val = csrs_rd ();
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break;
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case MT_CSRD: /* CSRD */
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val = csrd_rd ();
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break;
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case MT_CSTS: /* CSTS */
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val = csts_rd ();
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break;
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case MT_CDR: /* CDR */
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case MT_SBIFS: /* SBIFS */
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case MT_SBIS: /* SBIS */
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case MT_SBISC: /* SBISC */
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case MT_SBIMT: /* SBIMT */
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case MT_SBIER: /* SBIER */
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case MT_SBITA: /* SBITA */
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val = 0;
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break;
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default:
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RSVD_OPND_FAULT;
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}
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return val;
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}
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/* Write 730-specific IPR's */
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void WriteIPR (int32 rg, int32 val)
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{
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switch (rg) {
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case MT_ICCS: /* ICCS */
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iccs_wr (val);
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break;
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case MT_NICR: /* NICR */
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nicr_wr (val);
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break;
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case MT_TODR: /* TODR */
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todr_wr (val);
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break;
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case MT_ACCS: /* ACCS (not impl) */
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break;
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case MT_RXCS: /* RXCS */
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rxcs_wr (val);
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break;
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case MT_TXCS: /* TXCS */
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txcs_wr (val);
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break;
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case MT_TXDB: /* TXDB */
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txdb_wr (val);
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break;
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case MT_MCESR: /* MCESR (not impl) */
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break;
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case MT_UBINIT: /* UBINIT (not impl) */
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break;
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case MT_CSRS: /* CSRS */
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csrs_wr (val);
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break;
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case MT_CSTS: /* CSTS */
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csts_wr (val);
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break;
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case MT_CSTD: /* CSTD */
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cstd_wr (val);
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break;
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case MT_CDR: /* CDR */
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case MT_SBIFS: /* SBIFS */
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case MT_SBISC: /* SBISC */
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case MT_SBIMT: /* SBIMT */
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case MT_SBIER: /* SBIER */
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case MT_SBIQC: /* SBIQC */
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break;
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default:
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RSVD_OPND_FAULT;
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}
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return;
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}
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/* ReadReg - read register space
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Inputs:
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pa = physical address
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lnt = length (BWLQ)
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Output:
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longword of data
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*/
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int32 ReadReg (uint32 pa, int32 lnt)
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{
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int32 nexus, val;
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if (ADDR_IS_REG (pa)) { /* reg space? */
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nexus = NEXUS_GETNEX (pa); /* get nexus */
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if (nexusR[nexus] && /* valid? */
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(nexusR[nexus] (&val, pa, lnt) == SCPE_OK)) {
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SET_IRQL;
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return val;
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}
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}
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MACH_CHECK (MCHK_NXM);
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return 0;
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}
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/* WriteReg - write register space
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Inputs:
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pa = physical address
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val = data to write, right justified in 32b longword
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lnt = length (BWLQ)
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Outputs:
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none
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*/
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void WriteReg (uint32 pa, int32 val, int32 lnt)
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{
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int32 nexus;
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if (ADDR_IS_REG (pa)) { /* reg space? */
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nexus = NEXUS_GETNEX (pa); /* get nexus */
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if (nexusW[nexus] && /* valid? */
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(nexusW[nexus] (val, pa, lnt) == SCPE_OK)) {
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SET_IRQL;
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return;
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}
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}
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MACH_CHECK (MCHK_NXM);
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return;
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}
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/* Machine check
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Error status word format
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<2:0> = ASTLVL
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<3> = PME
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<6:4> = arith trap code
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Rest will be zero
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*/
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int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta)
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{
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int32 acc, nxm;
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nxm = ((p1 == MCHK_NXM) || (p1 == MCHK_IIA) || (p1 == MCHK_IUA));
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if (nxm)
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cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take normal exception */
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else
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cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take severe exception */
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acc = ACC_MASK (KERN); /* in kernel mode */
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in_ie = 1;
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SP = SP - 16; /* push 4 words */
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Write (SP, 12, L_LONG, WA); /* # bytes */
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Write (SP + 4, p1, L_LONG, WA); /* mcheck type */
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if (nxm)
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Write (SP + 8, mchk_va, L_LONG, WA); /* NXM addr */
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else
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Write (SP + 8, 0, L_LONG, WA); /* first parameter */
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Write (SP + 12, 0, L_LONG, WA); /* second parameter */
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in_ie = 0;
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return cc;
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}
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/* Console entry - only reached if CONHALT is set (AUTORESTART is set */
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int32 con_halt (int32 code, int32 cc)
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{
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if ((cpu_boot_cmd[0] == 0) || /* saved boot cmd? */
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(vax730_boot_parse (0, cpu_boot_cmd) != SCPE_OK) || /* reparse the boot cmd */
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(reset_all (0) != SCPE_OK) || /* reset the world */
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(cpu_boot (0, NULL) != SCPE_OK)) /* set up boot code */
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ABORT (STOP_BOOT); /* any error? */
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sim_printf ("Rebooting...\n");
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return cc;
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}
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/* Special boot command - linked into SCP by initial reset
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Syntax: BOOT <device>{/R5:val}
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Sets up R0-R5, calls SCP boot processor with effective BOOT CPU
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*/
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t_stat vax730_boot (int32 flag, char *ptr)
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{
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t_stat r;
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r = vax730_boot_parse (flag, ptr); /* parse the boot cmd */
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if (r != SCPE_OK) { /* error? */
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if (r >= SCPE_BASE) { /* message available? */
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sim_printf ("%s\n", sim_error_text (r));
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r |= SCPE_NOMESSAGE;
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}
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return r;
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}
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strncpy (cpu_boot_cmd, ptr, CBUFSIZE); /* save for reboot */
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return run_cmd (flag, "CPU");
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}
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/* Parse boot command, set up registers - also used on reset */
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t_stat vax730_boot_parse (int32 flag, char *ptr)
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{
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char gbuf[CBUFSIZE];
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char *slptr, *regptr;
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int32 i, r5v, unitno;
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DEVICE *dptr;
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UNIT *uptr;
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DIB *dibp;
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uint32 ba;
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t_stat r;
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if (!ptr || !*ptr)
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return SCPE_2FARG;
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regptr = get_glyph (ptr, gbuf, 0); /* get glyph */
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if ((slptr = strchr (gbuf, '/'))) { /* found slash? */
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regptr = strchr (ptr, '/'); /* locate orig */
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*slptr = 0; /* zero in string */
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}
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dptr = find_unit (gbuf, &uptr); /* find device */
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if ((dptr == NULL) || (uptr == NULL))
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return SCPE_ARG;
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dibp = (DIB *) dptr->ctxt; /* get DIB */
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if (dibp == NULL)
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ba = 0;
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else
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ba = dibp->ba;
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unitno = (int32) (uptr - dptr->units);
|
|
r5v = 0;
|
|
if ((strncmp (regptr, "/R5:", 4) == 0) ||
|
|
(strncmp (regptr, "/R5=", 4) == 0) ||
|
|
(strncmp (regptr, "/r5:", 4) == 0) ||
|
|
(strncmp (regptr, "/r5=", 4) == 0)) {
|
|
r5v = (int32) get_uint (regptr + 4, 16, LMASK, &r);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
}
|
|
else
|
|
if (*regptr == '/') {
|
|
r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
}
|
|
else {
|
|
if (*regptr != 0)
|
|
return SCPE_ARG;
|
|
}
|
|
for (i = 0; boot_tab[i].name != NULL; i++) {
|
|
if (strcmp (dptr->name, boot_tab[i].name) == 0) {
|
|
R[0] = boot_tab[i].code;
|
|
if (boot_tab[i].code == BOOT_RB) { /* vector set by console for RB730 */
|
|
extern DIB rb_dib;
|
|
R[0] = R[0] | ((rb_dib.vec - VEC_Q) << 16);
|
|
}
|
|
R[1] = TR_UBA;
|
|
R[2] = boot_tab[i].let | (ba & UBADDRMASK);
|
|
R[3] = unitno;
|
|
R[4] = 0;
|
|
R[5] = r5v;
|
|
return SCPE_OK;
|
|
}
|
|
}
|
|
return SCPE_NOFNC;
|
|
}
|
|
|
|
/* Bootstrap - finish up bootstrap process */
|
|
|
|
t_stat cpu_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
t_stat r;
|
|
|
|
|
|
r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, FALSE, 0x200);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
SP = PC = 512;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* SYSB reset */
|
|
|
|
t_stat sysb_reset (DEVICE *dptr)
|
|
{
|
|
sim_vm_cmd = vax730_cmd;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
char *sysb_description (DEVICE *dptr)
|
|
{
|
|
return "system bus controller";
|
|
}
|
|
|
|
/* Show nexus */
|
|
|
|
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
fprintf (st, "nexus=%d", val);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Init nexus tables */
|
|
|
|
void init_nexus_tab (void)
|
|
{
|
|
uint32 i;
|
|
|
|
for (i = 0; i < NEXUS_NUM; i++) {
|
|
nexusR[i] = NULL;
|
|
nexusW[i] = NULL;
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Build nexus tables
|
|
|
|
Inputs:
|
|
dptr = pointer to device
|
|
dibp = pointer to DIB
|
|
Outputs:
|
|
status
|
|
*/
|
|
|
|
|
|
t_stat build_nexus_tab (DEVICE *dptr, DIB *dibp)
|
|
{
|
|
uint32 idx;
|
|
|
|
if ((dptr == NULL) || (dibp == NULL))
|
|
return SCPE_IERR;
|
|
idx = dibp->ba;
|
|
if (idx >= NEXUS_NUM)
|
|
return SCPE_IERR;
|
|
if ((nexusR[idx] && dibp->rd && /* conflict? */
|
|
(nexusR[idx] != dibp->rd)) ||
|
|
(nexusW[idx] && dibp->wr &&
|
|
(nexusW[idx] != dibp->wr))) {
|
|
sim_printf ("Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba);
|
|
return SCPE_STOP;
|
|
}
|
|
if (dibp->rd) /* set rd dispatch */
|
|
nexusR[idx] = dibp->rd;
|
|
if (dibp->wr) /* set wr dispatch */
|
|
nexusW[idx] = dibp->wr;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Build dib_tab from device list */
|
|
|
|
t_stat build_dib_tab (void)
|
|
{
|
|
uint32 i;
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
t_stat r;
|
|
|
|
init_nexus_tab ();
|
|
init_ubus_tab ();
|
|
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
|
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
|
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
|
|
if (dptr->flags & DEV_NEXUS) { /* Nexus? */
|
|
if ((r = build_nexus_tab (dptr, dibp))) /* add to dispatch table */
|
|
return r;
|
|
}
|
|
else { /* no, Unibus device */
|
|
if ((r = build_ubus_tab (dptr, dibp))) /* add to dispatch tab */
|
|
return r;
|
|
} /* end else */
|
|
} /* end if enabled */
|
|
} /* end for */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat cpu_print_model (FILE *st)
|
|
{
|
|
fprintf (st, "VAX 11/730");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
fprintf (st, "Initial memory size is 2MB.\n\n");
|
|
fprintf (st, "The simulator is booted with the BOOT command:\n\n");
|
|
fprintf (st, " sim> BO{OT} <device>{/R5:flags}\n\n");
|
|
fprintf (st, "where <device> is one of:\n\n");
|
|
fprintf (st, " HKn to boot from hkn\n");
|
|
fprintf (st, " RLn to boot from rln\n");
|
|
fprintf (st, " RQn to boot from rqn\n");
|
|
fprintf (st, " RQBn to boot from rqbn\n");
|
|
fprintf (st, " RQCn to boot from rqcn\n");
|
|
fprintf (st, " RQDn to boot from rqdn\n");
|
|
fprintf (st, " TQn to boot from tqn\n");
|
|
fprintf (st, " TDn to boot from tdn (TU58)\n");
|
|
fprintf (st, " RBn to boot from rbn\n\n");
|
|
return SCPE_OK;
|
|
}
|