783 lines
27 KiB
C
783 lines
27 KiB
C
/* isbc202.c: Intel double density disk adapter
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Copyright (c) 2016, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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27 Jun 16 - Original file.
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Registers:
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078H - Read - Subsystem status
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bit 0 - ready status of drive 0
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bit 1 - ready status of drive 1
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bit 2 - state of channel's interrupt FF
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bit 3 - controller presence indicator
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bit 4 - DD controller presence indicator
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bit 5 - ready status of drive 2
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bit 6 - ready status of drive 3
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bit 7 - zero
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079H - Read - Read result type (bits 2-7 are zero)
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00 - I/O complete with error
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01 - Reserved
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10 - Result byte contains diskette ready status
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11 - Reserved
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079H - Write - IOPB address low byte.
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07AH - Write - IOPB address high byte and start operation.
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07BH - Read - Read result byte
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If result type is 00H
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bit 0 - deleted record
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bit 1 - CRC error
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bit 2 - seek error
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bit 3 - address error
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bit 4 - data overrun/underrun
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bit 5 - write protect
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bit 6 - write error
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bit 7 - not ready
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If result type is 02H and ready has changed
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bit 0 - zero
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bit 1 - zero
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bit 2 - zero
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bit 3 - zero
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bit 4 - drive 2 ready
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bit 5 - drive 3 ready
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bit 6 - drive 0 ready
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bit 7 - drive 1 ready
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else return 0
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07FH - Write - Reset diskette system.
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Operations:
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NOP - 0x00
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Seek - 0x01
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Format Track - 0x02
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Recalibrate - 0x03
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Read Data - 0x04
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Verify CRC - 0x05
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Write Data - 0x06
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Write Deleted Data - 0x07
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IOPB - I/O Parameter Block
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Byte 0 - Channel Word
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bit 3 - data word length (=8-bit, 1=16-bit)
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bit 4-5 - interrupt control
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00 - I/O complete interrupt to be issued
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01 - I/O complete interrupts are disabled
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10 - illegal code
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11 - illegal code
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bit 6- randon format sequence
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Byte 1 - Diskette Instruction
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bit 0-2 - operation code
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000 - no operation
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001 - seek
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010 - format track
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011 - recalibrate
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100 - read data
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101 - verify CRC
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110 - write data
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111 - write deleted data
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bit 3 - data word length ( same as byte-0, bit-3)
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bit 4-5 - unit select
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00 - drive 0
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01 - drive 1
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10 - drive 2
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11 - drive 3
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bit 6-7 - reserved (zero)
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Byte 2 - Number of Records
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Byte 4 - Track Address
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Byte 5 - Sector Address
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Byte 6 - Buffer Low Address
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Byte 7 - Buffer High Address
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u3 -
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u4 -
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u5 -
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u6 - fdd number.
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NOTES:
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This iSBC 202 device simulator (DEVICES) supports 4 floppy disk drives
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(UNITS). It uses the SBC202_BASE and SBC202_INT from system_defs.h to
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set the default base port and interrupt.
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The default base port can be changed by "sim> set sbc202 port=88". The
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default interrupt can be changed by "sim> set sbc202 int=5". Current
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settings can be shown by "sim> show sbc202 param".
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This device simulator can be enabled or disabled if SBC202_NUM in
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system_defs.h is set to 1. Only one board can be simulated. It is
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enabled by "sim> Sset sbc202 ena" and disabled by "sim> set sbc202 dis".
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The disk images in each FDD can be set to RW or WP. They default to WP
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*/
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#include "system_defs.h" /* system header in system dir */
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#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
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#define UNIT_WPMODE (1 << UNIT_V_WPMODE)
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#define FDD_NUM 4
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#define SECSIZ 128
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//disk controller operations
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#define DNOP 0x00 //disk no operation
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#define DSEEK 0x01 //disk seek
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#define DFMT 0x02 //disk format
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#define DHOME 0x03 //disk home
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#define DREAD 0x04 //disk read
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#define DVCRC 0x05 //disk verify CRC
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#define DWRITE 0x06 //disk write
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//status
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#define RDY0 0x01 //FDD 0 ready
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#define RDY1 0x02 //FDD 1 ready
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#define FDCINT 0x04 //FDC interrupt flag
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#define FDCPRE 0x08 //FDC board present
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#define FDCDD 0x10 //FDC is DD
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#define RDY2 0x20 //FDD 2 ready
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#define RDY3 0x40 //FDD 3 ready
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//result type
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#define ROK 0x00 //FDC error
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#define RCHG 0x02 //FDC OK OR disk changed
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// If result type is ROK then rbyte is
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#define RB0DR 0x01 //deleted record
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#define RB0CRC 0x02 //CRC error
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#define RB0SEK 0x04 //seek error
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#define RB0ADR 0x08 //address error
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#define RB0OU 0x10 //data overrun/underrun
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#define RB0WP 0x20 //write protect
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#define RB0WE 0x40 //write error
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#define RB0NR 0x80 //not ready
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// If result type is RCHG then rbyte is
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#define RB1RD2 0x10 //drive 2 ready
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#define RB1RD3 0x20 //drive 3 ready
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#define RB1RD0 0x40 //drive 0 ready
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#define RB1RD1 0x80 //drive 1 ready
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//disk geometry values
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#define MDSDD 512512 //double density FDD size
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#define MAXSECDD 52 //double density last sector
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#define MAXTRK 76 //last track
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#define isbc202_NAME "Intel iSBC 202 Floppy Disk Controller Board"
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/* external globals */
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extern uint16 PCX;
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern uint8 unreg_dev(uint16);
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extern uint8 get_mbyte(uint16 addr);
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extern void put_mbyte(uint16 addr, uint8 val);
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/* function prototypes */
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t_stat isbc202_cfg(uint16 base, uint16 size, uint8 devnum);
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t_stat isbc202_clr(void);
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t_stat isbc202_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc202_set_int(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc202_set_verb(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc202_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat isbc202_reset(DEVICE *dptr);
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void isbc202_reset_dev(void);
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t_stat isbc202_attach (UNIT *uptr, CONST char *cptr);
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t_stat isbc202_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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uint8 isbc202r0(t_bool io, uint8 data, uint8 devnum); /* isbc202 0 */
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uint8 isbc202r1(t_bool io, uint8 data, uint8 devnum); /* isbc202 1 */
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uint8 isbc202r2(t_bool io, uint8 data, uint8 devnum); /* isbc202 2 */
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uint8 isbc202r3(t_bool io, uint8 data, uint8 devnum); /* isbc202 3 */
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uint8 isbc202r7(t_bool io, uint8 data, uint8 devnum); /* isbc202 7 */
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void isbc202_diskio(void); //do actual disk i/o
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/* globals */
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int isbc202_onetime = 1;
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static const char* isbc202_desc(DEVICE *dptr) {
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return isbc202_NAME;
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}
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typedef struct { //FDD definition
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uint8 sec;
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uint8 cyl;
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uint8 att;
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} FDDDEF;
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typedef struct { //FDC definition
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uint8 baseport; //FDC base port
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uint8 intnum; //interrupt number
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uint8 verb; //verbose flag
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uint16 iopb; //FDC IOPB
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uint8 stat; //FDC status
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uint8 rdychg; //FDC ready change
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uint8 rtype; //FDC result type
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uint8 rbyte0; //FDC result byte for type 00
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uint8 rbyte1; //FDC result byte for type 10
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uint8 intff; //fdc interrupt FF
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FDDDEF fdd[FDD_NUM]; //indexed by the FDD number
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} FDCDEF;
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FDCDEF fdc202; //indexed by the isbc-202 instance number
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/* isbc202 Standard I/O Data Structures */
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UNIT isbc202_unit[] = { // 4 FDDs
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD) },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD) },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD) },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD) },
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{ NULL }
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};
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REG isbc202_reg[] = {
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{ HRDATA (STAT0, fdc202.stat, 8) }, /* isbc202 status */
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{ HRDATA (RTYP0, fdc202.rtype, 8) }, /* isbc202 result type */
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{ HRDATA (RBYT0A, fdc202.rbyte0, 8) }, /* isbc202 result byte 0 */
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{ HRDATA (RBYT0B, fdc202.rbyte1, 8) }, /* isbc202 result byte 1 */
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{ HRDATA (INTFF0, fdc202.intff, 8) }, /* isbc202 interrupt f/f */
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{ NULL }
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};
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MTAB isbc202_mod[] = {
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{ UNIT_WPMODE, 0, "RW", "RW", &isbc202_set_mode },
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{ UNIT_WPMODE, UNIT_WPMODE, "WP", "WP", &isbc202_set_mode },
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "VERB", &isbc202_set_verb,
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NULL, NULL, "Sets the verbose mode for iSBC202"},
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "PORT", &isbc202_set_port,
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NULL, NULL, "Sets the base port for iSBC202"},
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &isbc202_set_int,
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NULL, NULL, "Sets the interrupt number for iSBC202"},
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, &isbc202_show_param, NULL,
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"show configured parameters for iSBC202" },
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{ 0 }
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};
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DEBTAB isbc202_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE isbc202_dev = {
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"SBC202", //name
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isbc202_unit, //units
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isbc202_reg, //registers
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isbc202_mod, //modifiers
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FDD_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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isbc202_reset, //reset
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NULL, //boot
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&isbc202_attach, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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isbc202_debug, //debflags
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NULL, //msize
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NULL, //lname
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NULL, //help routine
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NULL, //attach help routine
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NULL, //help context
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&isbc202_desc //device description
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};
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// isbc 202 configuration
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t_stat isbc202_cfg(uint16 baseport, uint16 devnum, uint8 intnum)
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{
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int i;
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UNIT *uptr;
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// one-time initialization for all FDDs for this FDC instance
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for (i = 0; i < FDD_NUM; i++) {
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uptr = isbc202_dev.units + i;
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uptr->u6 = i; //fdd unit number
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uptr->flags &= ~UNIT_ATT;
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}
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fdc202.baseport = baseport & BYTEMASK; //set port
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fdc202.intnum = intnum; //set interrupt
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fdc202.verb = 0; //clear verb
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reg_dev(isbc202r0, fdc202.baseport, 0, 0); //read status
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reg_dev(isbc202r1, fdc202.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
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reg_dev(isbc202r2, fdc202.baseport + 2, 0, 0); //write IOPB addr-h and start
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reg_dev(isbc202r3, fdc202.baseport + 3, 0, 0); //read rstl byte
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reg_dev(isbc202r7, fdc202.baseport + 7, 0, 0); //write reset fdc202
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isbc202_reset_dev(); //software reset
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// if (fdc202.verb)
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sim_printf(" sbc202: Enabled base port at 0%02XH, Interrupt #=%02X, %s\n",
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fdc202.baseport, fdc202.intnum, fdc202.verb ? "Verbose" : "Quiet" );
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return SCPE_OK;
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}
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t_stat isbc202_clr(void)
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{
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fdc202.intnum = -1; //set default interrupt
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fdc202.verb = 0; //set verb = 0
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unreg_dev(fdc202.baseport); //read status
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unreg_dev(fdc202.baseport + 1); //read rslt type/write IOPB addr-l
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unreg_dev(fdc202.baseport + 2); //write IOPB addr-h and start
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unreg_dev(fdc202.baseport + 3); //read rstl byte
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unreg_dev(fdc202.baseport + 7); //write reset fdc202
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// if (fdc202.verb)
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sim_printf(" sbc202: Disabled\n");
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return SCPE_OK;
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}
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/* isbc202 set mode = Write protect */
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t_stat isbc202_set_mode(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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if (uptr->flags & UNIT_ATT)
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return sim_messagef (SCPE_ALATT, "%s is already attached to %s\n",
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sim_uname(uptr), uptr->filename);
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if (val & UNIT_WPMODE) { /* write protect */
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uptr->flags |= val;
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// if (fdc202.verb)
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sim_printf(" SBC202%d: WP\n", uptr->u6);
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} else { /* read write */
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uptr->flags &= ~val;
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// if (fdc202.verb)
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sim_printf(" SBC202%d: RW\n", uptr->u6);
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}
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return SCPE_OK;
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}
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// set base port address parameter
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t_stat isbc202_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 size, result;
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if (uptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "%02x", &size);
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fdc202.baseport = size;
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// if (fdc202.verb)
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sim_printf("SBC202: Installed at base port=%04X\n", fdc202.baseport);
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reg_dev(isbc202r0, fdc202.baseport, 0, 0); //read status
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reg_dev(isbc202r1, fdc202.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
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reg_dev(isbc202r2, fdc202.baseport + 2, 0, 0); //write IOPB addr-h and start
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reg_dev(isbc202r3, fdc202.baseport + 3, 0, 0); //read rstl byte
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reg_dev(isbc202r7, fdc202.baseport + 7, 0, 0); //write reset fdc202
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return SCPE_OK;
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}
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// set interrupt parameter
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t_stat isbc202_set_int(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 size, result;
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if (uptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "%02x", &size);
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fdc202.intnum = size;
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// if (fdc202.verb)
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sim_printf("SBC202: Interrupt number=%04X\n", fdc202.intnum);
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return SCPE_OK;
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}
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// set verbose mode
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t_stat isbc202_set_verb(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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if (cptr == NULL)
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return SCPE_ARG;
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if (strncasecmp(cptr, "OFF", 4) == 0) {
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fdc202.verb = 0;
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return SCPE_OK;
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}
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if (strncasecmp(cptr, "ON", 3) == 0) {
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fdc202.verb = 1;
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return SCPE_OK;
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}
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return SCPE_ARG;
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}
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// show configuration parameters
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t_stat isbc202_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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int i = 0;
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "%s Base port at %04X Interrupt # is %i %s",
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((isbc202_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled",
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fdc202.baseport, fdc202.intnum,
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fdc202.verb ? "Verbose" : "Quiet"
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);
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return SCPE_OK;
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}
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/* Hardware reset routine */
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t_stat isbc202_reset(DEVICE *dptr)
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{
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if (dptr == NULL)
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return SCPE_ARG;
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isbc202_reset_dev(); //software reset
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return SCPE_OK;
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}
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/* Software reset routine */
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|
|
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void isbc202_reset_dev(void)
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{
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int32 i;
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UNIT *uptr;
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fdc202.stat = 0; //clear status
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for (i = 0; i < FDD_NUM; i++) { /* handle all units */
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uptr = isbc202_dev.units + i;
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fdc202.stat |= FDCPRE | FDCDD; //set the FDC status
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fdc202.rtype = ROK;
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fdc202.rbyte0 = 0; //set no error
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if (uptr->flags & UNIT_ATT) { /* if attached */
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switch(i){
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case 0:
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fdc202.stat |= RDY0; //set FDD 0 ready
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fdc202.rbyte1 |= RB1RD0;
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break;
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case 1:
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fdc202.stat |= RDY1; //set FDD 1 ready
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fdc202.rbyte1 |= RB1RD1;
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break;
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case 2:
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fdc202.stat |= RDY2; //set FDD 2 ready
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fdc202.rbyte1 |= RB1RD2;
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break;
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case 3:
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fdc202.stat |= RDY3; //set FDD 3 ready
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fdc202.rbyte1 |= RB1RD3;
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break;
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}
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fdc202.rdychg = 0;
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}
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}
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}
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/* isbc202 attach - attach an .IMG file to an FDD */
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t_stat isbc202_attach (UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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uint8 fddnum;
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fddnum = uptr->u6;
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if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
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sim_printf(" isbc202_attach: Attach error %d\n", r);
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return r;
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}
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switch(fddnum){
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case 0:
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fdc202.stat |= RDY0; //set FDD 0 ready
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fdc202.rbyte1 |= RB1RD0;
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break;
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case 1:
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fdc202.stat |= RDY1; //set FDD 1 ready
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fdc202.rbyte1 |= RB1RD1;
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break;
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case 2:
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fdc202.stat |= RDY2; //set FDD 2 ready
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fdc202.rbyte1 |= RB1RD2;
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break;
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case 3:
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fdc202.stat |= RDY3; //set FDD 3 ready
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fdc202.rbyte1 |= RB1RD3;
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break;
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}
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fdc202.rtype = ROK;
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fdc202.rbyte0 = 0; //set no error
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return SCPE_OK;
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}
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/* iSBC202 control port functions */
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uint8 isbc202r0(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read ststus*/
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return fdc202.stat;
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}
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return 0;
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}
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uint8 isbc202r1(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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fdc202.intff = 0; //clear interrupt FF
|
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fdc202.stat &= ~FDCINT;
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fdc202.rtype = ROK;
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return fdc202.rtype;
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} else { /* write data port */
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fdc202.iopb = data;
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}
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return 0;
|
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}
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uint8 isbc202r2(t_bool io, uint8 data, uint8 devnum)
|
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{
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if (io == 0) { /* read data port */
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;
|
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} else { /* write data port */
|
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fdc202.iopb |= (data << 8);
|
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isbc202_diskio();
|
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if (fdc202.intff)
|
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fdc202.stat |= FDCINT;
|
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}
|
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return 0;
|
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}
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|
|
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uint8 isbc202r3(t_bool io, uint8 data, uint8 devnum)
|
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{
|
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if (io == 0) { /* read data port */
|
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if (fdc202.rtype == ROK) {
|
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return fdc202.rbyte0;
|
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} else {
|
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if (fdc202.rdychg) {
|
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return fdc202.rbyte1;
|
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} else {
|
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return fdc202.rbyte0;
|
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}
|
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}
|
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} else { /* write data port */
|
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; //stop diskette operation
|
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}
|
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return 0;
|
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}
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|
|
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uint8 isbc202r7(t_bool io, uint8 data, uint8 devnum)
|
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{
|
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if (io == 0) { /* read data port */
|
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;
|
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} else { /* write data port */
|
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isbc202_reset_dev();
|
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}
|
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return 0;
|
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}
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|
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// perform the actual disk I/O operation
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|
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void isbc202_diskio(void)
|
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{
|
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uint8 cw, di, nr, ta, sa, data, nrptr;
|
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uint16 ba;
|
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uint32 dskoff;
|
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uint8 fddnum, fmtb;
|
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uint32 i;
|
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UNIT *uptr;
|
|
uint8 *fbuf;
|
|
|
|
//parse the IOPB
|
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cw = get_mbyte(fdc202.iopb);
|
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di = get_mbyte(fdc202.iopb + 1);
|
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nr = get_mbyte(fdc202.iopb + 2);
|
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ta = get_mbyte(fdc202.iopb + 3);
|
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sa = get_mbyte(fdc202.iopb + 4);
|
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ba = get_mbyte(fdc202.iopb + 5);
|
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ba |= (get_mbyte(fdc202.iopb + 6) << 8);
|
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fddnum = (di & 0x30) >> 4;
|
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uptr = isbc202_dev.units + fddnum;
|
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fbuf = (uint8 *) uptr->filebuf;
|
|
if (fdc202.verb)
|
|
sim_printf("\n SBC202: FDD %d - nr=%02XH ta=%02XH sa=%02XH IOPB=%04XH PCX=%04XH",
|
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fddnum, nr, ta, sa, fdc202.iopb, PCX);
|
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switch(fddnum) { //check ready status
|
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case 0:
|
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if ((fdc202.stat & RDY0) == 0) {
|
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fdc202.rtype = ROK;
|
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fdc202.rbyte0 = RB0NR;
|
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fdc202.intff = 1; //set interrupt FF
|
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sim_printf("\n SBC202: FDD %d - Ready error", fddnum);
|
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return;
|
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}
|
|
break;
|
|
case 1:
|
|
if ((fdc202.stat & RDY1) == 0) {
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = RB0NR;
|
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fdc202.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC202: FDD %d - Ready error", fddnum);
|
|
return;
|
|
}
|
|
break;
|
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case 2:
|
|
if ((fdc202.stat & RDY2) == 0) {
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = RB0NR;
|
|
fdc202.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC202: FDD %d - Ready error", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 3:
|
|
if ((fdc202.stat & RDY3) == 0) {
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = RB0NR;
|
|
fdc202.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC202: FDD %d - Ready error", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
//check for address error
|
|
if (
|
|
((di & 0x07) != DHOME) && ( //this is not in manual
|
|
(sa > MAXSECDD) ||
|
|
((sa + nr) > (MAXSECDD + 1)) ||
|
|
(sa == 0) ||
|
|
(ta > MAXTRK)
|
|
)) {
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = RB0ADR;
|
|
fdc202.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC202: FDD %d - Address error nr=%02XH ta=%02XH sa=%02XH IOPB=%04XH PCX=%04XH",
|
|
fddnum, nr, ta, sa, fdc202.iopb, PCX);
|
|
return;
|
|
}
|
|
switch (di & 0x07) {
|
|
case DNOP:
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = 0; //set no error
|
|
fdc202.intff = 1; //set interrupt FF
|
|
break;
|
|
case DSEEK:
|
|
fdc202.fdd[fddnum].sec = sa;
|
|
fdc202.fdd[fddnum].cyl = ta;
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = 0; //set no error
|
|
fdc202.intff = 1; //set interrupt FF
|
|
break;
|
|
case DHOME:
|
|
fdc202.fdd[fddnum].sec = sa;
|
|
fdc202.fdd[fddnum].cyl = 0;
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = 0; //set no error
|
|
fdc202.intff = 1; //set interrupt FF
|
|
break;
|
|
case DVCRC:
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = 0; //set no error
|
|
fdc202.intff = 1; //set interrupt FF
|
|
break;
|
|
case DFMT:
|
|
//check for WP
|
|
if(uptr->flags & UNIT_WPMODE) {
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = RB0WP;
|
|
fdc202.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC202: FDD %d - Write protect error DFMT", fddnum);
|
|
return;
|
|
}
|
|
fmtb = get_mbyte(ba); //get the format byte
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * MAXSECDD) + (sa - 1)) * SECSIZ;
|
|
for(i=0; i<=((uint32)(MAXSECDD) * SECSIZ); i++) {
|
|
*(fbuf + (dskoff + i)) = fmtb;
|
|
}
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = 0; //set no error
|
|
fdc202.intff = 1; //set interrupt FF
|
|
break;
|
|
case DREAD:
|
|
nrptr = 0;
|
|
while(nrptr < nr) {
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * MAXSECDD) + (sa - 1)) * SECSIZ;
|
|
//copy sector from disk image to RAM
|
|
for (i=0; i<SECSIZ; i++) {
|
|
data = *(fbuf + (dskoff + i));
|
|
put_mbyte(ba + i, data);
|
|
}
|
|
sa++;
|
|
ba+=0x80;
|
|
nrptr++;
|
|
}
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = 0; //set no error
|
|
fdc202.intff = 1; //set interrupt FF
|
|
break;
|
|
case DWRITE:
|
|
//check for WP
|
|
if(uptr->flags & UNIT_WPMODE) {
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = RB0WP;
|
|
fdc202.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC202: FDD %d - Write protect error DWRITE", fddnum);
|
|
return;
|
|
}
|
|
nrptr = 0;
|
|
while(nrptr < nr) {
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * MAXSECDD) + (sa - 1)) * SECSIZ;
|
|
//copy sector from RAM to disk image
|
|
for (i=0; i<SECSIZ; i++) {
|
|
data = get_mbyte(ba + i);
|
|
*(fbuf + (dskoff + i)) = data;
|
|
}
|
|
sa++;
|
|
ba+=0x80;
|
|
nrptr++;
|
|
}
|
|
fdc202.rtype = ROK;
|
|
fdc202.rbyte0 = 0; //set no error
|
|
fdc202.intff = 1; //set interrupt FF
|
|
break;
|
|
default:
|
|
sim_printf("\n SBC202: FDD %d - isbc202_diskio bad command di=%02X",
|
|
fddnum, di & 0x07);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* end of isbc202.c */
|