546 lines
23 KiB
C
546 lines
23 KiB
C
/* id_mt.c: Interdata magnetic tape simulator
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Copyright (c) 2001-2022, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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mt M46-494 dual density 9-track magtape controller
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26-Mar-22 RMS Added extra case points for new MTSE definitions
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16-Feb-06 RMS Added tape capacity checking
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18-Mar-05 RMS Added attached test to detach routine
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07-Dec-04 RMS Added read-only file support
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25-Apr-03 RMS Revised for extended file support
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28-Mar-03 RMS Added multiformat support
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28-Feb-03 RMS Revised for magtape library
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20-Feb-03 RMS Fixed read to stop selch on error
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Magnetic tapes are represented as a series of variable 8b records
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of the form:
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32b record length in bytes - exact number
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byte 0
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byte 1
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:
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byte n-2
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byte n-1
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32b record length in bytes - exact number
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If the byte count is odd, the record is padded with an extra byte
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of junk. File marks are represented by a single record length of 0.
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End of tape is two consecutive end of file marks.
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*/
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#include "id_defs.h"
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#include "sim_tape.h"
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#define UST u3 /* unit status */
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#define UCMD u4 /* unit command */
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#define MT_MAXFR (1 << 24) /* max transfer */
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/* Command - in UCMD */
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#define MTC_SPCR 0x11 /* backspace */
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#define MTC_SKFR 0x13 /* space file rev */
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#define MTC_CLR 0x20 /* clear */
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#define MTC_RD 0x21 /* read */
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#define MTC_WR 0x22 /* write */
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#define MTC_SKFF 0x23 /* space file fwd */
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#define MTC_WEOF 0x30 /* write eof */
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#define MTC_REW 0x38 /* rewind */
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#define MTC_MASK 0x3F
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#define MTC_STOP1 0x40 /* stop, set EOM */
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#define MTC_STOP2 0x80 /* stop, set NMTN */
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/* Status byte, * = in UST */
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#define STA_ERR 0x80 /* error */
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#define STA_EOF 0x40 /* end of file */
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#define STA_EOT 0x20 /* *end of tape */
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#define STA_NMTN 0x10 /* *no motion */
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#define STA_UFLGS (STA_EOT|STA_NMTN) /* unit flags */
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#define STA_MASK (STA_ERR|STA_EOF|STA_BSY|STA_EOM)
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#define SET_EX (STA_ERR|STA_EOF|STA_NMTN)
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extern uint32 int_req[INTSZ], int_enb[INTSZ];
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uint8 mtxb[MT_MAXFR]; /* xfer buffer */
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uint32 mt_bptr = 0; /* pointer */
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uint32 mt_blnt = 0; /* length */
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uint32 mt_sta = 0; /* status byte */
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uint32 mt_db = 0; /* data buffer */
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uint32 mt_xfr = 0; /* data xfr in prog */
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uint32 mt_arm[MT_NUMDR] = { 0 }; /* intr armed */
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int32 mt_wtime = 10; /* byte latency */
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int32 mt_rtime = 1000; /* record latency */
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int32 mt_stopioe = 1; /* stop on error */
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uint8 mt_tplte[] = { 0, o_MT0, o_MT0*2, o_MT0*3, TPL_END };
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static const uint8 bad_cmd[64] = {
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1
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};
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uint32 mt (uint32 dev, uint32 op, uint32 dat);
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t_stat mt_svc (UNIT *uptr);
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t_stat mt_reset (DEVICE *dptr);
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t_stat mt_attach (UNIT *uptr, CONST char *cptr);
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t_stat mt_detach (UNIT *uptr);
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t_stat mt_boot (int32 unitno, DEVICE *dptr);
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t_stat mt_map_err (UNIT *uptr, t_stat st);
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/* MT data structures
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mt_dev MT device descriptor
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mt_unit MT unit list
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mt_reg MT register list
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mt_mod MT modifier list
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*/
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DIB mt_dib = { d_MT, 0, v_MT, mt_tplte, &mt, NULL };
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UNIT mt_unit[] = {
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{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
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{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
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{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
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{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }
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};
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REG mt_reg[] = {
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{ HRDATA (STA, mt_sta, 8) },
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{ HRDATA (BUF, mt_db, 8) },
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{ BRDATA (DBUF, mtxb, 16, 8, MT_MAXFR) },
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{ HRDATA (DBPTR, mt_bptr, 16) },
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{ HRDATA (DBLNT, mt_blnt, 17), REG_RO },
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{ FLDATA (XFR, mt_xfr, 0) },
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{ GRDATA (IREQ, int_req[l_MT], 16, MT_NUMDR, i_MT) },
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{ GRDATA (IENB, int_enb[l_MT], 16, MT_NUMDR, i_MT) },
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{ BRDATA (IARM, mt_arm, 16, 1, MT_NUMDR) },
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{ FLDATA (STOP_IOE, mt_stopioe, 0) },
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{ DRDATA (WTIME, mt_wtime, 24), PV_LEFT + REG_NZ },
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{ DRDATA (RTIME, mt_rtime, 24), PV_LEFT + REG_NZ },
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{ URDATA (UST, mt_unit[0].UST, 16, 8, 0, MT_NUMDR, 0) },
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{ URDATA (CMD, mt_unit[0].UCMD, 16, 8, 0, MT_NUMDR, 0) },
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{ URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
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MT_NUMDR, PV_LEFT | REG_RO) },
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{ HRDATA (DEVNO, mt_dib.dno, 8), REG_HRO },
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{ HRDATA (SELCH, mt_dib.sch, 1), REG_HRO },
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{ NULL }
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};
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MTAB mt_mod[] = {
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{ MTAB_XTD|MTAB_VUN, 0, "write enabled", "WRITEENABLED",
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&set_writelock, &show_writelock, NULL, "Write ring in place" },
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{ MTAB_XTD|MTAB_VUN, 1, NULL, "LOCKED",
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&set_writelock, NULL, NULL, "no Write ring in place" },
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{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
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&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
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{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
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&sim_tape_set_capac, &sim_tape_show_capac, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
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&set_dev, &show_dev, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "SELCH", "SELCH",
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&set_sch, &show_sch, NULL },
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{ 0 }
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};
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DEVICE mt_dev = {
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"MT", mt_unit, mt_reg, mt_mod,
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MT_NUMDR, 10, 31, 1, 16, 8,
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NULL, NULL, &mt_reset,
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&mt_boot, &mt_attach, &mt_detach,
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&mt_dib, DEV_DISABLE | DEV_TAPE
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};
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/* Magtape: IO routine */
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uint32 mt (uint32 dev, uint32 op, uint32 dat)
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{
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uint32 i, f, t;
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uint32 u = (dev - mt_dib.dno) / o_MT0;
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UNIT *uptr = mt_dev.units + u;
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switch (op) { /* case IO op */
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case IO_ADR: /* select */
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sch_adr (mt_dib.sch, dev); /* inform sel ch */
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return BY; /* byte only */
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case IO_RD: /* read data */
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if (mt_xfr) /* xfr? set busy */
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mt_sta = mt_sta | STA_BSY;
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return mt_db; /* return data */
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case IO_WD: /* write data */
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if (mt_xfr) { /* transfer? */
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mt_sta = mt_sta | STA_BSY; /* set busy */
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if ((uptr->UCMD & (MTC_STOP1 | MTC_STOP2)) &&
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((uptr->UCMD & MTC_MASK) == MTC_WR)) /* while stopping? */
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mt_sta = mt_sta | STA_ERR; /* write overrun */
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}
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mt_db = dat & DMASK8; /* store data */
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break;
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case IO_SS: /* status */
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mt_sta = mt_sta & STA_MASK; /* ctrl status */
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if (uptr->flags & UNIT_ATT) /* attached? */
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t = mt_sta | (uptr->UST & STA_UFLGS); /* yes, unit status */
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else t = mt_sta | STA_DU; /* no, dev unavail */
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if (t & SET_EX) /* test for ex */
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t = t | STA_EX;
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return t;
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case IO_OC: /* command */
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mt_arm[u] = int_chg (v_MT + u, dat, mt_arm[u]);
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f = dat & MTC_MASK; /* get cmd */
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if (f == MTC_CLR) { /* clear? */
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mt_reset (&mt_dev); /* reset world */
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break;
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}
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if (((uptr->flags & UNIT_ATT) == 0) || /* ignore if unatt */
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bad_cmd[f] || /* or bad cmd */
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(((f == MTC_WR) || (f == MTC_WEOF)) && /* or write */
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sim_tape_wrp (uptr))) /* and protected */
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break;
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for (i = 0; i < MT_NUMDR; i++) { /* check other drvs */
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if (sim_is_active (&mt_unit[i]) && /* active? */
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(mt_unit[i].UCMD != MTC_REW)) { /* not rewind? */
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sim_cancel (&mt_unit[i]); /* stop */
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mt_unit[i].UCMD = 0;
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}
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}
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if (sim_is_active (uptr) && /* unit active? */
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!(uptr->UCMD & (MTC_STOP1 | MTC_STOP2))) /* not stopping? */
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break; /* ignore */
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if ((f == MTC_WR) || (f == MTC_REW)) /* write, rew: bsy=0 */
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mt_sta = 0;
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else mt_sta = STA_BSY; /* bsy=1,nmtn,eom,err=0 */
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mt_bptr = mt_blnt = 0; /* not yet started */
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if ((f == MTC_RD) || (f == MTC_WR)) /* data xfr? */
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mt_xfr = 1; /* set xfr flag */
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else mt_xfr = 0;
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uptr->UCMD = f; /* save cmd */
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uptr->UST = 0; /* clr tape stat */
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sim_activate (uptr, mt_rtime); /* start op */
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break;
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}
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return 0;
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}
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/* Unit service
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A given operation can generate up to three interrupts
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- EOF generates an interrupt when set (read, space, wreof)
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BUSY will still be set, EOM and NMTN will be clear
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- After operation complete + delay, EOM generates an interrupt
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BUSY will be clear, EOM will be set, NMTN will be clear
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- After a further delay, NMTN generates an interrupt
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BUSY will be clear, EOM and NMTN will be set
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Rewind generates an interrupt when NMTN sets
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*/
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t_stat mt_svc (UNIT *uptr)
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{
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uint32 i;
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int32 u = uptr - mt_dev.units;
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uint32 dev = mt_dib.dno + (u * o_MT0);
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t_mtrlnt tbc;
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t_bool passed_eot;
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t_stat st, r = SCPE_OK;
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if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
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uptr->UCMD = 0; /* clr cmd */
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uptr->UST = 0; /* set status */
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mt_xfr = 0; /* clr op flags */
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mt_sta = STA_ERR | STA_EOM; /* set status */
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if (mt_arm[u]) /* interrupt */
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SET_INT (v_MT + u);
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return IORETURN (mt_stopioe, SCPE_UNATT);
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}
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if (uptr->UCMD & MTC_STOP2) { /* stop, gen NMTN? */
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uptr->UCMD = 0; /* clr cmd */
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uptr->UST = uptr->UST | STA_NMTN; /* set nmtn */
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mt_xfr = 0; /* clr xfr */
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if (mt_arm[u]) /* set intr */
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SET_INT (v_MT + u);
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return SCPE_OK;
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}
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if (uptr->UCMD & MTC_STOP1) { /* stop, gen EOM? */
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uptr->UCMD = uptr->UCMD | MTC_STOP2; /* clr cmd */
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mt_sta = (mt_sta & ~STA_BSY) | STA_EOM; /* clr busy, set eom */
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if (mt_arm[u]) /* set intr */
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SET_INT (v_MT + u);
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sim_activate (uptr, mt_rtime); /* schedule */
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return SCPE_OK;
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}
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passed_eot = sim_tape_eot (uptr); /* passed EOT? */
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switch (uptr->UCMD) { /* case on function */
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case MTC_REW: /* rewind */
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sim_tape_rewind (uptr); /* reposition */
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uptr->UCMD = 0; /* clr cmd */
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uptr->UST = STA_NMTN | STA_EOT; /* update status */
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mt_sta = mt_sta & ~STA_BSY; /* don't set EOM */
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if (mt_arm[u]) /* interrupt */
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SET_INT (v_MT + u);
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return SCPE_OK;
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/* For read, busy = 1 => buffer empty
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For write, busy = 1 => buffer full
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For read, data transfers continue for the full length of the
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record, or the maximum size of the transfer buffer
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For write, data transfers continue until a write is attempted
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and the buffer is empty
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*/
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case MTC_RD: /* read */
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if (mt_blnt == 0) { /* first time? */
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st = sim_tape_rdrecf (uptr, mtxb, &tbc, MT_MAXFR); /* read rec */
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if (st == MTSE_RECE) /* rec in err? */
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mt_sta = mt_sta | STA_ERR;
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else if (st != SCPE_OK) { /* other error? */
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r = mt_map_err (uptr, st); /* map error */
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if (sch_actv (mt_dib.sch, dev)) /* if sch, stop */
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sch_stop (mt_dib.sch);
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break;
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}
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mt_blnt = tbc; /* set buf lnt */
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}
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if (sch_actv (mt_dib.sch, dev)) { /* sch active? */
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i = sch_wrmem (mt_dib.sch, mtxb, mt_blnt); /* store rec in mem */
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if (sch_actv (mt_dib.sch, dev)) /* sch still active? */
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sch_stop (mt_dib.sch); /* stop chan, long rd */
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else if (i < mt_blnt) /* process entire rec? */
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mt_sta = mt_sta | STA_ERR; /* no, overrun error */
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}
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else if (mt_bptr < mt_blnt) { /* no, if !eor */
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if (!(mt_sta & STA_BSY)) /* busy still clr? */
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mt_sta = mt_sta | STA_ERR; /* read overrun */
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mt_db = mtxb[mt_bptr++]; /* get next byte */
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mt_sta = mt_sta & ~STA_BSY; /* !busy = buf full */
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if (mt_arm[u]) /* set intr */
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SET_INT (v_MT + u);
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sim_activate (uptr, mt_wtime); /* reschedule */
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return SCPE_OK;
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}
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break; /* record done */
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case MTC_WR: /* write */
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if (sch_actv (mt_dib.sch, dev)) { /* sch active? */
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mt_bptr = sch_rdmem (mt_dib.sch, mtxb, MT_MAXFR); /* get rec */
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if (sch_actv (mt_dib.sch, dev)) /* not done? */
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sch_stop (mt_dib.sch); /* stop chan */
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}
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else if (mt_sta & STA_BSY) { /* no, if !eor */
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if (mt_bptr < MT_MAXFR) /* if room */
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mtxb[mt_bptr++] = mt_db; /* store in buf */
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mt_sta = mt_sta & ~STA_BSY; /* !busy = buf emp */
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if (mt_arm[u]) /* set intr */
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SET_INT (v_MT + u);
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sim_activate (uptr, mt_wtime); /* reschedule */
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return SCPE_OK;
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}
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if (mt_bptr) { /* any chars? */
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if ((st = sim_tape_wrrecf (uptr, mtxb, mt_bptr)))/* write, err? */
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r = mt_map_err (uptr, st); /* map error */
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}
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break; /* record done */
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case MTC_WEOF: /* write eof */
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if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
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r = mt_map_err (uptr, st); /* map error */
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mt_sta = mt_sta | STA_EOF; /* set eof */
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if (mt_arm[u]) /* set intr */
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SET_INT (v_MT + u);
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break;
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case MTC_SKFF: /* skip file fwd */
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while ((st = sim_tape_sprecf (uptr, &tbc)) == MTSE_OK) ;
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if (st == MTSE_TMK) { /* stopped by tmk? */
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mt_sta = mt_sta | STA_EOF; /* set eof */
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if (mt_arm[u]) /* set intr */
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SET_INT (v_MT + u);
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}
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else r = mt_map_err (uptr, st); /* map error */
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break;
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case MTC_SKFR: /* skip file rev */
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while ((st = sim_tape_sprecr (uptr, &tbc)) == MTSE_OK) ;
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if (st == MTSE_TMK) { /* stopped by tmk? */
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mt_sta = mt_sta | STA_EOF; /* set eof */
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if (mt_arm[u]) /* set intr */
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SET_INT (v_MT + u);
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}
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else r = mt_map_err (uptr, st); /* map error */
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break;
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case MTC_SPCR: /* backspace */
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if ((st = sim_tape_sprecr (uptr, &tbc))) /* skip rec rev, err? */
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r = mt_map_err (uptr, st); /* map error */
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break;
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} /* end case */
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if (!passed_eot && sim_tape_eot (uptr)) /* just passed EOT? */
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uptr->UST = uptr->UST | STA_EOT;
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uptr->UCMD = uptr->UCMD | MTC_STOP1; /* set stop stage 1 */
|
|
sim_activate (uptr, mt_rtime); /* schedule */
|
|
return r;
|
|
}
|
|
|
|
/* Map tape error status */
|
|
|
|
t_stat mt_map_err (UNIT *uptr, t_stat st)
|
|
{
|
|
int32 u = uptr - mt_dev.units;
|
|
|
|
switch (st) {
|
|
|
|
case MTSE_FMT: /* illegal fmt */
|
|
case MTSE_UNATT: /* not attached */
|
|
default: /* unknown error */
|
|
mt_sta = mt_sta | STA_ERR;
|
|
case MTSE_OK: /* no error */
|
|
return SCPE_IERR;
|
|
|
|
case MTSE_TMK: /* end of file */
|
|
mt_sta = mt_sta | STA_EOF; /* set eof */
|
|
if (mt_arm[u]) /* set intr */
|
|
SET_INT (v_MT + u);
|
|
break;
|
|
|
|
case MTSE_IOERR: /* IO error */
|
|
mt_sta = mt_sta | STA_ERR; /* set err */
|
|
if (mt_stopioe)
|
|
return SCPE_IOERR;
|
|
break;
|
|
|
|
case MTSE_INVRL: /* invalid rec lnt */
|
|
mt_sta = mt_sta | STA_ERR;
|
|
return SCPE_MTRLNT;
|
|
|
|
case MTSE_WRP: /* write protect */
|
|
case MTSE_RECE: /* record in error */
|
|
case MTSE_EOM: /* end of medium */
|
|
mt_sta = mt_sta | STA_ERR; /* set err */
|
|
break;
|
|
|
|
case MTSE_BOT: /* reverse into BOT */
|
|
uptr->UST = uptr->UST | STA_EOT; /* set err */
|
|
break;
|
|
} /* end switch */
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat mt_reset (DEVICE *dptr)
|
|
{
|
|
uint32 u;
|
|
UNIT *uptr;
|
|
|
|
mt_bptr = mt_blnt = 0; /* clr buf */
|
|
mt_sta = STA_BSY; /* clr flags */
|
|
mt_xfr = 0; /* clr controls */
|
|
for (u = 0; u < MT_NUMDR; u++) { /* loop thru units */
|
|
CLR_INT (v_MT + u); /* clear int */
|
|
CLR_ENB (v_MT + u); /* disable int */
|
|
mt_arm[u] = 0; /* disarm int */
|
|
uptr = mt_dev.units + u;
|
|
sim_tape_reset (uptr); /* clear pos flag */
|
|
sim_cancel (uptr); /* cancel activity */
|
|
uptr->UST = (uptr->UST & STA_UFLGS) | STA_NMTN; /* init status */
|
|
uptr->UCMD = 0; /* init cmd */
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Attach routine */
|
|
|
|
t_stat mt_attach (UNIT *uptr, CONST char *cptr)
|
|
{
|
|
int32 u = uptr - mt_dev.units;
|
|
t_stat r;
|
|
|
|
r = sim_tape_attach (uptr, cptr);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
uptr->UST = STA_EOT;
|
|
if (mt_arm[u])
|
|
SET_INT (v_MT + u);
|
|
return r;
|
|
}
|
|
|
|
/* Detach routine */
|
|
|
|
t_stat mt_detach (UNIT* uptr)
|
|
{
|
|
int32 u = uptr - mt_dev.units;
|
|
t_stat r;
|
|
|
|
if (!(uptr->flags & UNIT_ATT))
|
|
return SCPE_OK;
|
|
r = sim_tape_detach (uptr);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
if (mt_arm[u])
|
|
SET_INT (v_MT + u);
|
|
uptr->UST = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Bootstrap routine */
|
|
|
|
#define BOOT_START 0x50
|
|
#define BOOT_LEN (sizeof (boot_rom) / sizeof (uint8))
|
|
|
|
static uint8 boot_rom[] = {
|
|
0xD5, 0x00, 0x00, 0xCF, /* ST: AL CF */
|
|
0x43, 0x00, 0x00, 0x80 /* BR 80 */
|
|
};
|
|
|
|
t_stat mt_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
extern DIB sch_dib;
|
|
uint32 sch_dev;
|
|
|
|
if (decrom[0xD5] & dec_flgs) /* AL defined? */
|
|
return SCPE_NOFNC;
|
|
sim_tape_rewind (&mt_unit[unitno]); /* rewind */
|
|
sch_dev = sch_dib.dno + mt_dib.sch; /* sch dev # */
|
|
IOWriteBlk (BOOT_START, BOOT_LEN, boot_rom); /* copy boot */
|
|
IOWriteB (AL_DEV, mt_dib.dno + (unitno * o_MT0)); /* set dev no for unit */
|
|
IOWriteB (AL_IOC, 0xA1); /* set dev cmd */
|
|
IOWriteB (AL_SCH, sch_dev); /* set dev no for chan */
|
|
PC = BOOT_START;
|
|
return SCPE_OK;
|
|
}
|