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WARNING: V2.10 has reorganized and renamed some of the definition files for the PDP-10, PDP-11, and VAX. Be sure to delete all previous source files before you unpack the Zip archive, or unpack it into a new directory structure. WARNING: V2.10 has a new, more comprehensive save file format. Restoring save files from previous releases will cause 'invalid register' errors and loss of CPU option flags, device enable/ disable flags, unit online/offline flags, and unit writelock flags. WARNING: If you are using Visual Studio .NET through the IDE, be sure to turn off the /Wp64 flag in the project settings, or dozens of spurious errors will be generated. WARNING: Compiling Ethernet support under Windows requires extra steps; see the Ethernet readme file. Ethernet support is currently available only for Windows, Linux, NetBSD, and OpenBSD. 1. New Features 1.1 SCP and Libraries - The VT emulation package has been replaced by the capability to remote the console to a Telnet session. Telnet clients typically have more complete and robust VT100 emulation. - Simulated devices may now have statically allocated buffers, in addition to dynamically allocated buffers or disk-based data stores. - The DO command now takes substitutable arguments (max 9). In command files, %n represents substitutable argument n. - The initial command line is now interpreted as the command name and substitutable arguments for a DO command. This is backward compatible to prior versions. - The initial command line parses switches. -Q is interpreted as quiet mode; informational messages are suppressed. - The HELP command now takes an optional argument. HELP <cmd> types help on the specified command. - Hooks have been added for implementing GUI-based consoles, as well as simulator-specific command extensions. A few internal data structures and definitions have changed. - Two new routines (tmxr_open_master, tmxr_close_master) have been added to sim_tmxr.c. The calling sequence for sim_accept_conn has been changed in sim_sock.c. - The calling sequence for the VM boot routine has been modified to add an additional parameter. - SAVE now saves, and GET now restores, controller and unit flags. - Library sim_ether.c has been added for Ethernet support. 1.2 VAX - Non-volatile RAM (NVR) can behave either like a memory or like a disk-based peripheral. If unattached, it behaves like memory and is saved and restored by SAVE and RESTORE, respectively. If attached, its contents are loaded from disk by ATTACH and written back to disk at DETACH and EXIT. - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape) has been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from vax_stddev.c and now references a common implementation file, dec_pt.h. - Examine and deposit switches now work on all devices, not just the CPU. - Device address conflicts are not detected until simulation starts. 1.3 PDP-11 - SHOW <device> VECTOR displays the device's interrupt vector. Most devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk), RX211 (double density floppy), and KW11P programmable clock have been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from pdp11_stddev.c and now references a common implementation file, dec_pt.h. - Device bootstraps now use the actual CSR specified by the SET ADDRESS command, rather than just the default CSR. Note that PDP-11 operating systems may NOT support booting with non-standard addresses. - Specifying more than 256KB of memory, or changing the bus configuration, causes all peripherals that are not compatible with the current bus configuration to be disabled. - Device address conflicts are not detected until simulation starts. 1.4 PDP-10 - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The RX211 (double density floppy) has been added; it is off by default. - The paper tape now references a common implementation file, dec_pt.h. - Device address conflicts are not detected until simulation starts. 1.5 PDP-1 - DECtape (then known as MicroTape) support has been added. - The line printer and DECtape can be disabled and enabled. 1.6 PDP-8 - The RX28 (double density floppy) has been added as an option to the existing RX8E controller. - SHOW <device> DEVNO displays the device's device number. Most devices allow the device number to be changed with SET <device> DEVNO=nnn. - Device number conflicts are not detected until simulation starts. 1.7 IBM 1620 - The IBM 1620 simulator has been released. 1.8 AltairZ80 - A hard drive has been added for increased storage. - Several bugs have been fixed. 1.9 HP 2100 - The 12845A has been added and made the default line printer (LPT). The 12653A has been renamed LPS and is off by default. It also supports the diagnostic functions needed to run the DCPC and DMS diagnostics. - The 12557A/13210A disk defaults to the 13210A (7900/7901). - The 12559A magtape is off by default. - New CPU options (EAU/NOEAU) enable/disable the extended arithmetic instructions for the 2116. These instructions are standard on the 2100 and 21MX. - New CPU options (MPR/NOMPR) enable/disable memory protect for the 2100 and 21MX. - New CPU options (DMS/NODMS) enable/disable the dynamic mapping instructions for the 21MX. - The 12539 timebase generator autocalibrates. 1.10 Simulated Magtapes - Simulated magtapes recognize end of file and the marker 0xFFFFFFFF as end of medium. Only the TMSCP tape simulator can generate an end of medium marker. - The error handling in simulated magtapes was overhauled to be consistent through all simulators. 1.11 Simulated DECtapes - Added support for RT11 image file format (256 x 16b) to DECtapes. 2. Release Notes 2.1 Bugs Fixed - TS11/TSV05 was not simulating the XS0_MOT bit, causing failures under VMS. In addition, two of the CTL options were coded interchanged. - IBM 1401 tape was not setting a word mark under group mark for load mode reads. This caused the diagnostics to crash. - SCP bugs in ssh_break and set_logon were fixed (found by Dave Hittner). - Numerous bugs in the HP 2100 extended arithmetic, floating point, 21MX, DMS, and IOP instructions were fixed. Bugs were also fixed in the memory protect and DMS functions. The moving head disks (DP, DQ) were revised to simulate the hardware more accurately. Missing functions in DQ (address skip, read address) were added. 2.2 HP 2100 Debugging - The HP 2100 CPU nows runs all of the CPU diagnostics. - The peripherals run most of the peripheral diagnostics. There is still a problem in overlapped seek operation on the disks. See the file hp2100_diag.txt for details. 3. In Progress These simulators are not finished and are available in a separate Zip archive distribution. - Interdata 16b/32b: coded, partially tested. See the file id_diag.txt for details. - SDS 940: coded, partially tested.
314 lines
9.5 KiB
Text
314 lines
9.5 KiB
Text
To: Users
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From: Bob Supnik
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Subj: H316 Simulator Usage
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Date: 15-Nov-2002
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COPYRIGHT NOTICE
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The following copyright notice applies to both the SIMH source and binary:
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Original code published in 1993-2002, written by Robert M Supnik
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Copyright (c) 1993-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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This memorandum documents the Honeywell 316/516 simulator.
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1. Simulator Files
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The H316 requires the following files:
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sim/ sim_defs.h
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sim_rev.h
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sim_sock.h
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sim_tmxr.h
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scp.c
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scp_tty.c
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sim_sock.c
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sim_tmxr.c
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sim/h316/ h316_defs.h
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h316_cpu.c
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h316_lp.c
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h316_stddev.c
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h316_cpu.c
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2. H316/H516 Features
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The Honeywell 316/516 simulator is configured as follows:
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device simulates
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name(s)
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CPU H316/H516 CPU with 16/32KW memory
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PTR 316/516-50 paper tape reader
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PTP 316/516-52 paper tape punch
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TTY 316/516-33 console terminal
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CLK 316/516-12 real time clock
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LPT 316/516 line printer
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The H316/H516 simulator implements several unique stop conditions:
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- decode of an undefined instruction, and STOP_INST is et
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- reference to an undefined I/O device, and STOP_DEV is set
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- more than INDMAX indirect references are detected during
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memory reference address decoding
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The H316/H516 loader is not implemented.
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2.1 CPU
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CPU options include choice of instruction set and memory size.
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SET CPU HSA high speed arithmetic instructions
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SET CPU NOHSA no high speed arithmetic instructions
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SET CPU 4K set memory size = 4K
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SET CPU 8K set memory size = 8K
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SET CPU 12K set memory size = 12K
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SET CPU 16K set memory size = 16K
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SET CPU 24K set memory size = 24K
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SET CPU 32K set memory size = 32K
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If memory size is being reduced, and the memory being truncated contains
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non-zero data, the simulator asks for confirmation. Data in the truncated
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portion of memory is lost. Initial memory size is 32K.
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CPU registers include the visible state of the processor as well as the
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control registers for the interrupt system.
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name size comments
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P 15 program counter
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A 16 A register
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B 16 B register
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X 16 index register
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SC 16 shift count
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C 1 carry flag
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EXT 1 extend flag
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PME 1 previous mode extend flag
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EXT_OFF 1 extend off pending flag
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DP 1 double precision flag
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SS1..4 1 sense switches 1..4
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ION 1 interrupts enabled
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INODEF 1 interrupts not deferred
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INTREQ 16 interrupt requests
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DEVRDY 16 device ready flags (read only)
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DEVENB 16 device interrupt enable flags (read only)
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STOP_INST 1 stop on undefined instruction
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STOP_DEV 1 stop on undefined device
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INDMAX 1 indirect address limit
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PCQ[0:63] 15 PC prior to last JMP, JSB, or interrupt;
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most recent PC change first
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WRU 8 interrupt character
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2.2 Programmed I/O Devices
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2.2.1 316/516-50 Paper Tape Reader (PTR)
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The paper tape reader (PTR) reads data from a disk file. The POS
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register specifies the number of the next data item to be read.
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Thus, by changing POS, the user can backspace or advance the reader.
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The paper tape reader supports the BOOT command. BOOT PTR copies the
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absolute binary loader into memory and starts it running.
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The paper tape reader implements these registers:
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name size comments
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BUF 8 last data item processed
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INTREQ 1 device interrupt request
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READY 1 device ready
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ENABLE 1 device interrupts enabled
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POS 32 position in the input or output file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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0 out of tape
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end of file 1 report error and stop
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0 out of tape or paper
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OS I/O error x report error and stop
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2.2.2 316/516-52 Paper Tape Punch (PTP)
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The paper tape punch (PTP) writes data to a disk file. The POS
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register specifies the number of the next data item to be written.
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Thus, by changing POS, the user can backspace or advance the punch.
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The paper tape punch implements these registers:
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name size comments
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BUF 8 last data item processed
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INTREQ 1 device interrupt request
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READY 1 device ready
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ENABLE 1 device interrupts enabled
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POWER 1 device powered up
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POS 32 position in the input or output file
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TIME 24 time from I/O initiation to interrupt
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PWRTIME 24 time from I/O request to power up
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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0 out of tape
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OS I/O error x report error and stop
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2.2.3 316/516-33 Console Teletype (TTY)
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The Teletype units (TTY0, TTY1) can be set to one of three modes:
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KSR, 7B, or 8B. In KSR mode, lower case input and output characters
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are automatically converted to upper case, and the high order bit is
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forced to one on input. In 7B mode, input and output characters are
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masked to 7 bits. In 8B mode, characters are not modified. Changing
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the mode of either unit changes both. The default mode is KSR.
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The Teletype reads from the console keyboard and writes to the
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simulator console window. It implements these registers:
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name size comments
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BUF 8 last data item processed
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MODE 1 read/write mode
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INTREQ 1 device interrupt request
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READY 1 device ready
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ENABLE 1 device interrupts enabled
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KPOS 32 number of characters input
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KTIME 24 keyboard polling interval
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TPOS 32 number of characters output
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TTIME 24 time from I/O initiation to interrupt
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2.2.4 316/516-12 Real Time Clock (CLK)
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The real time clock (CLK) implements these registers:
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name size comments
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INTREQ 1 device interrupt request
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READY 1 device ready
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ENABLE 1 device interrupts enabled
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TIME 24 clock interval
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The real-time clock autocalibrates; the clock interval is adjusted up or
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down so that the clock tracks actual elapsed time.
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2.2.5 316/5116 Line Printer (LPT)
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The line printer (LPT) writes data to a disk file. The POS register
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specifies the number of the next data item to be written. Thus,
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by changing POS, the user can backspace or advance the printer.
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The line printer implements these registers:
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name size comments
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WDPOS 6 word position in current scan
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DRPOS 6 drum position
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CRPOS 1 carriage position
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XFER 1 transfer ready flag
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PRDN 1 print done flag
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INTREQ 1 device interrupt request
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ENABLE 1 device interrupt enable
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SVCST 2 service state
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SVCCH 2 service channel
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BUF 8 buffer
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POS 32 number of characters output
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XTIME 24 delay between transfers
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ETIME 24 delay at end of scan
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PTIME 24 delay for shuttle/line advance
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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0 out of paper
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OS I/O error x report error and stop
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2.3 Symbolic Display and Input
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The H316/H516 simulator implements symbolic display and input. Display is
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controlled by command line switches:
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-a display as ASCII character
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-c display as two character string
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-m display instruction mnemonics
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Input parsing is controlled by the first character typed in or by command
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line switches:
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' or -a ASCII character
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" or -c two character sixbit string
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alphabetic instruction mnemonic
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numeric octal number
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Instruction input uses standard H316/H516 assembler syntax. There are six
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instruction classes: memory reference, I/O, control, shift, skip, and
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operate.
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Memory reference instructions have the format
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memref{*} {C/Z} address{,1}
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where * signifies indirect, C a current sector reference, Z a sector zero
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reference, and 1 indexed. The address is an octal number in the range 0 -
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077777; if C or Z is specified, the address is a page offset in the range
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0 - 0777. Normally, C is not needed; the simulator figures out from the
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address what mode to use. However, when referencing memory outside the CPU
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(eg, disks), there is no valid PC, and C must be used to specify current
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sector addressing.
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I/O instructions have the format
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io pulse+device
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The pulse+device is an octal number in the range 0 - 01777.
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Control and operate instructions consist of a single opcode
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opcode
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Shift instructions have the format
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shift n
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where n is an octal number in the range 0-77.
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Skip instructions have the format
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sub-op sub-op sub-op...
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The simulator checks that the combination of sub-opcodes is legal.
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