f20f5c629d
1. New Features in 2.10-3
1.1 SCP and Libraries
- Added dynamic extension of the breakpoint table.
- Added breakpoint actions.
- Added VMS support for ! (from Mark Pizzolato).
1.2 18b PDP's
- Added RB09 fixed head disk for the PDP-9.
- Added LP09 line printer for the PDP-9 and PDP-15.
- Added variable size support and autosizing to the RF15/RF09.
1.3 PDP-8
- Added variable size support and autosizing to the DF32 and RF08.
1.4 Nova
- Added variable size support and autosizing to the Novadisk.
2. Bugs Fixed in 2.10-3
- 18b PDP RF15/RF09: fixed IOT decoding and address wraparound
logic (found by Hans Pufal).
- 18b PDP RP15: fixed IOT decoding and command initiation.
- HP2100 IPL: changed to full duplex (found by Mike Gemeny).
- HP2100 CPU: fixed last cycle bug in DMA outpout (found by Mike
Gemeny).
- Interdata 16b CPU: fixed bug in SETM, SETMR (found by Mark
Pizzolato).
3. New Features in 2.10 vs prior releases
3.1 SCP and Libraries
- The VT emulation package has been replaced by the capability
to remote the console to a Telnet session. Telnet clients
typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
in addition to dynamically allocated buffers or disk-based
data stores.
- The DO command now takes substitutable arguments (max 9).
In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
name and substitutable arguments for a DO command. This is
backward compatible to prior versions.
- The initial command line parses switches. -Q is interpreted
as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument. HELP <cmd>
types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
as well as simulator-specific command extensions. A few
internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
been added to sim_tmxr.c. The calling sequence for
sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.
- The EVAL command will evaluate a symbolic type-in and display
it in numeric form.
- The ! command (with no arguments) will launch the host operating
system command shell. The ! command (with an argument) executes
the argument as a host operating system command. (Code from
Mark Pizzolato)
- Telnet sessions now recognize BREAK. How a BREAK is transmitted
dependent on the particular Telnet client. (Code from Mark
Pizzolato)
- The sockets library includes code for active connections as
well as listening connections.
- The RESTORE command will restore saved memory size, if the
simulator supports dynamic memory resizing.
3.2 VAX
- Non-volatile RAM (NVR) can behave either like a memory or like
a disk-based peripheral. If unattached, it behaves like memory
and is saved and restored by SAVE and RESTORE, respectively.
If attached, its contents are loaded from disk by ATTACH and
written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
A few devices allow the vector to be changed with SET
<device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
the CPU.
- Device address conflicts are not detected until simulation starts.
- If the VAX console is attached to a Telnet session, BREAK is
interpreted as console halt.
- The SET/SHOW HISTORY commands enable and display a history of
the most recently executed instructions. (Code from Mark
Pizzolato)
3.3 PDP-11
- SHOW <device> VECTOR displays the device's interrupt vector.
Most devices allow the vector to be changed with SET
<device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
RX211 (double density floppy), and KW11P programmable clock
have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
SET ADDRESS command, rather than just the default CSR. Note
that PDP-11 operating systems may NOT support booting with
non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
configuration, causes all peripherals that are not compatible
with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.
- The PDP-11 implements a stub DEUNA/DELUA (XU). The real XU
module will be included in a later release.
3.4 PDP-10
- SHOW <device> VECTOR displays the device's interrupt vector.
A few devices allow the vector to be changed with SET
<device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
by default.
- The paper tape now references a common implementation file,
dec_pt.h.
- Device address conflicts are not detected until simulation starts.
- The PDP-10 implements a stub DEUNA/DELUA (XU). The real XU
module will be included in a later release.
3.5 PDP-1
- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.
- The PDP-1 supports the Type 24 serial drum (based on recently
discovered documents).
3.6 18b PDP's
- The PDP-4 supports the Type 24 serial drum (based on recently
discovered documents).
3.7 PDP-8
- The RX28 (double density floppy) has been added as an option to
the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number. Most
devices allow the device number to be changed with SET <device>
DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.
3.8 AltairZ80
- A hard drive has been added for increased storage.
- Several bugs have been fixed.
3.9 HP 2100
- The 12845A has been added and made the default line printer (LPT).
The 12653A has been renamed LPS and is off by default. It also
supports the diagnostic functions needed to run the DCPC and DMS
diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
instructions for the 2116. These instructions are standard on
the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
instructions for the 21MX.
- The 12539 timebase generator autocalibrates.
- The IOP microinstruction set is supported for the 21MX as well
as the 2100.
- The HP2100 supports the Access Interprocessor Link (IPL).
3.10 Simulated Magtapes
- Simulated magtapes recognize end of file and the marker
0xFFFFFFFF as end of medium. Only the TMSCP tape simulator
can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
consistent through all simulators.
3.11 Simulated DECtapes
- Added support for RT11 image file format (256 x 16b) to DECtapes.
3.12 Terminals Multiplexors
- BREAK detection was added to the HP, DEC, and Interdata terminal
multiplexors.
4. Bugs Fixed in 2.10 vs prior releases
- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
under VMS. In addition, two of the CTL options were coded
interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
load mode reads. This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
21MX, DMS, and IOP instructions were fixed. Bugs were also fixed
in the memory protect and DMS functions. The moving head disks
(DP, DQ) were revised to simulate the hardware more accurately.
Missing functions in DQ (address skip, read address) were added.
- PDP-10 tape wouldn't boot, and then wouldn't read (reported by
Michael Thompson and Harris Newman, respectively)
- PDP-1 typewriter is half duplex, with only one shift state for
both input and output (found by Derek Peschel)
- PDP-11 console must default to 7b for early UNIX compatibility.
- PDP-11/VAX TMSCP emulator was using the wrong packet length for
read/write end packets.
- Telnet IAC+IAC processing was fixed, both for input and output
(found by Mark Pizzolato).
- PDP-11/VAX Ethernet setting flag bits wrong for chained
descriptors (found by Mark Pizzolato).
5. General Notes
WARNING: The build procedures have changed. There is only one UNIX
makefile. To compile without Ethernet support, simply type
gmake {target|all}
To compile with Ethernet support, type
gmake USE_NETWORK=1 {target|all}
The Mingw batch files require Mingw release 2 and invoke the Unix
makefile. There are still separate batch files for compilation
with or without Ethernet support.
WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX. Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.
WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.
WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.
WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file. Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.
944 lines
30 KiB
Text
944 lines
30 KiB
Text
To: Users
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From: Bob Supnik
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Subj: HP2100 Simulator Usage
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Date: 15-Nov-2002
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COPYRIGHT NOTICE
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The following copyright notice applies to both the SIMH source and binary:
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Original code published in 1993-2002, written by Robert M Supnik
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Copyright (c) 1993-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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This memorandum documents the HP 2100 simulator.
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1. Simulator Files
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sim/ sim_defs.h
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sim_rev.h
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sim_sock.h
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sim_tmxr.h
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scp.c
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scp_tty.c
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sim_sock.c
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sim_tmxr.c
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sim/hp2100/ hp2100_defs.h
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hp2100_cpu.c
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hp2100_fp.c
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hp2100_dp.c
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hp2100_dq.c
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hp2100_dr.c
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hp2100_ipl.c
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hp2100_lps.c
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hp2100_lpt.c
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hp2100_mt.c
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hp2100_ms.c
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hp2100_mux.c
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hp2100_stddev.c
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hp2100_sys.c
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2. HP2100 Features
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The HP2100 simulator is configured as follows:
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device simulates
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name(s)
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CPU 2116 CPU with 32KW memory
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2100 CPU with 32KW memory, FP or IOP instructions
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21MX CPU with 1024KW memory, FP or DMS instructions
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DMA0, DMA1 dual channel DMA controller
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PTR,PTP 12597A paper tape reader/punch
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TTY 12631C buffered terminal controller
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LPS 12653A printer controller with 2767 printer
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12566B microcircuit interface for diagnostics
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LPT 12845A printer controller with 2607 printer
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CLK 12539A/B/C time base generator
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MUXL,MUXU,MUXC 12920A terminal multiplexor
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DP 12557A disk controller with four 2871 drives
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13210A disk controller with four 7900 drives
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DQ 12565A disk controller with two 2883 drives
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DR 12606B fixed head disk controller with 2770/2771 disks
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12610B drum controller with 2773/2774/2775 drums
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MT 12559C magnetic tape controller with one 3030 drive
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MS 13181A magnetic tape controller with four 7970B drives
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13183A magnetic tape controller with four 7970E drives
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IPLI 12556B interprocessor link, input side
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IPLO 12556B interprocessor link, output side
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The HP2100 simulator implements several unique stop conditions:
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- decode of an undefined instruction, and STOP_INST is et
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- reference to an undefined I/O device, and STOP_DEV is set
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- more than INDMAX indirect references are detected during
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memory reference address decoding
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The HP2100 loader supports standard absolute binary format. The DUMP
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command is not implemented.
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2.1 CPU
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CPU options include choice of instruction set and memory size.
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SET CPU 2116 2116 CPU
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SET CPU 2100 2100 CPU
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SET CPU 21MX 21MX CPU
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SET CPU EAU EAU instructions (2116 only)
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SET CPU NOEAU no EAU instructions (2116 only)
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SET CPU FP FP instructions (2100 only)
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SET CPU NOFP no FP instructions (2100 only)
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SET CPU IOP IOP instructions (2100, 21MX only)
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SET CPU NOIOP no IOP instructions (2100, 21MX only)
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SET CPU DMS DMS instructions (21MX only)
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SET CPU NODMS no DMS instructions (21MX only)
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SET CPU 4K set memory size = 4K
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SET CPU 8K set memory size = 8K
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SET CPU 16K set memory size = 16K
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SET CPU 32K set memory size = 32K
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SET CPU 64K set memory size = 64K (21MX only)
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SET CPU 128K set memory size = 128K (21MX only)
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SET CPU 256K set memory size = 256K (21MX only)
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SET CPU 512K set memory size = 512K (21MX only)
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SET CPU 1024K set memory size = 1024K (21MX only)
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On the 2100, EAU is standard, and the FP and IOP options are mutually
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exclusive. On the 21MX, EAU and FP are standard. The 2100 and 21MX
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include memory protection as standard; the 21MX optionally includes
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DMS (dynamic memory system).
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If memory size is being reduced, and the memory being truncated contains
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non-zero data, the simulator asks for confirmation. Data in the truncated
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portion of memory is lost. Initial memory size is 32K.
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These switches are recognized when examining or depositing in CPU memory:
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-v if DMS enabled, interpret address as virtual
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-s if DMS enabled, force system map
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-u if DMS enabled, force user map
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-p if DMS enabled, force port A map
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-q if DMS enabled, force port B map
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CPU registers include the visible state of the processor as well as the
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control registers for the interrupt system.
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name models size comments
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P all 15 program counter
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A all 16 A register
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B all 16 B register
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X 21MX 16 X index register
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Y 21MX 16 Y index register
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S all 16 switch/display register
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F 2100,21MX 15 memory protection fence
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E all 1 extend flag
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O all 1 overflow flag
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ION all 1 interrupt enable flag
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ION_DEFER all 1 interrupt defer flag
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IADDR all 6 most recent interrupting device
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MPCTL 2100,21MX 1 memory protection enable
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MPFLG 2100,21MX 1 memory protection flag
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MPFBF 2100,21MX 1 memory protection flag buffer
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MPVR 2100,21MX 16 memory protection violation reg
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MPEVR 2100,21MX 1 memory protection freeze flag
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MPMEV 2100,21MX 1 memory protection DMS error flag
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DMSENB 21MX 1 DMS enable
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DMSCUR 21MX 1 DMS current mode
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DMSSR 21MX 16 DMS status register
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DMSVR 21MX 16 DMS violation register
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DMSMAP[4][32] 21MX 20 DMS maps
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STOP_INST all 1 stop on undefined instruction
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STOP_DEV all 1 stop on undefined device
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INDMAX all 16 indirect address limit
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PCQ[0:63] all 15 P of last JMP, JSB, or interrupt;
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most recent P change first
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WRU all 8 interrupt character
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2.2 DMA Controllers
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The HP2100 includes two DMA channel controllers (DMA0 and DMA1). Each
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DMA channel has the following visible state:
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name size comments
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CMD 1 channel enabled
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CTL 1 interrupt enabled
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FLG 1 channel ready
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FBF 1 channel ready buffer
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CW1 16 command word 1
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CW2 16 command word 2
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CW3 16 command word 3
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2.3 Variable Device Assignments
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On the HP2100, I/O device take their device numbers from the backplane
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slot they are plugged into. Thus, device number assignments vary
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considerably from system to system, and software package to software
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package. The HP2100 simulator supports dynamic device number assignment.
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To show the current device number, use the SHOW <dev> DEVNO command:
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sim> SHOW PTR DEV
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device=10
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To change the device number, use the SET <dev> DEVNO=<num> command:
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sim> SET PTR DEV=30
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sim> SHOW PTR DEV
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device=30
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The new device number must be in the range 010..077 (octal). For devices
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with two device numbers, only the lower numbered device number can be
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changed; the higher is automatically set to the lower + 1. If a
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device number conflict occurs, the simulator will return an error
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when started.
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In addition, most devices can be enabled or disabled. To enable a
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device, use the SET <dev> ENABLED command:
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sim> SET DP ENABLED
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To disable a device, use the SET <dev> DISABLED command:
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sim> SET DP DISABLED
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For devices with more than one device number, disabling or enabling any
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device in the set disables all the devices.
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2.4 Programmed I/O Devices
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2.4.1 12597A-002 Paper Tape Reader (PTR)
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The paper tape reader (PTR) reads data from a disk file. The POS
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register specifies the number of the next data item to be read.
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Thus, by changing POS, the user can backspace or advance the reader.
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The paper tape reader supports the BOOT command. BOOT PTR copies the
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absolute binary loader into memory and starts it running.
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The paper tape reader implements these registers:
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name size comments
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BUF 8 last data item processed
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CMD 1 reader enable
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CTL 1 device/interrupt enable
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FLG 1 device ready
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FBF 1 device ready buffer
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POS 32 position in the input file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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0 out of tape
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end of file 1 report error and stop
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0 out of tape or paper
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OS I/O error x report error and stop
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2.4.2 12597A-005 Paper Tape Punch (PTP)
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The paper tape punch (PTP) writes data to a disk file. The POS
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register specifies the number of the next data item to be written.
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Thus, by changing POS, the user can backspace or advance the punch.
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The paper tape punch implements these registers:
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name size comments
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BUF 8 last data item processed
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CMD 1 punch enable
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CTL 1 device/interrupt enable
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FLG 1 device ready
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FBF 1 device ready buffer
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POS 32 position in the output file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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0 out of tape
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OS I/O error x report error and stop
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2.4.3 12631C Buffered Terminal (TTY)
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The console terminal has three units: keyboard (unit 0), printer
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(unit 1), and punch (unit 2). The keyboard reads from the console
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keyboard; the printer writes to the simulator console window. The
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punch writes to a disk file. The keyboard and printer units (TTY0,
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TTY1) can be set to one of three modes: UC, 7B, or 8B. In UC mode,
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lower case input and output characters are automatically converted to
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upper case. In 7B mode, input and output characters are masked to 7
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bits. In 8B mode, characters are not modified. Changing the mode
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of either unit changes both. The default mode is UC.
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The console teleprinter implements these registers:
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name size comments
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BUF 8 last data item processed
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MODE 16 mode
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CTL 1 device/interrupt enable
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FLG 1 device ready
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FBF 1 device ready buffer
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KPOS 32 number of characters input
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KTIME 24 keyboard polling interval
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TPOS 32 number of characters printed
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TTIME 24 time from I/O initiation to interrupt
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PPOS 32 position in the punch output file
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STOP_IOE 1 punch stop on I/O error
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Error handling for the punch is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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0 out of tape
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OS I/O error x report error and stop
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2.4.4 12653A Printer Controller (LPS) with 2767 Printer
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12566B Microcircuit Interface
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The 12653A line printer uses the 12566B microcircuit interface as
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its controller. As a line printer, LPS writes data to a disk file.
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The POS register specifies the number of the next data item to be
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written. Thus, by changing POS, the user can backspace or advance
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the printer.
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As a microcircuit interface, LPS provides the DMA test device for
|
|
running the dual channel port controller and DMS diagnostics. Printer
|
|
mode verus diagnostic mode is controlled by the commands:
|
|
|
|
SET LPS PRINTER configure as line printer
|
|
SET LPS DIAG configure for diagnostic tests
|
|
|
|
The 12653A is disabled by default.
|
|
|
|
The 12653A implements these registers:
|
|
|
|
name size comments
|
|
|
|
BUF 16 output buffer
|
|
STA 16 input buffer or status
|
|
CMD 1 printer enable
|
|
CTL 1 device/interrupt enable
|
|
FLG 1 device ready
|
|
FBF 1 device ready buffer
|
|
POS 32 position in the output file
|
|
CTIME 24 time between characters
|
|
PTIME 24 time for a print operation
|
|
STOP_IOE 1 stop on I/O error
|
|
|
|
In printer mode, error handling is as follows:
|
|
|
|
error STOP_IOE processed as
|
|
|
|
not attached 1 report error and stop
|
|
0 out of tape or paper
|
|
|
|
OS I/O error x report error and stop
|
|
|
|
In diagnostic mode, there are no errors; data sent to the output
|
|
buffer is looped back to the status register with a fixed delay of 1.
|
|
|
|
2.4.5 12845A Printer Controller (LPT)
|
|
|
|
The line printer (LPT) writes data to a disk file. The POS register
|
|
specifies the number of the next data item to be written. Thus,
|
|
by changing POS, the user can backspace or advance the printer.
|
|
|
|
The line printer implements these registers:
|
|
|
|
name size comments
|
|
|
|
BUF 8 last data item processed
|
|
CMD 1 printer enable
|
|
CTL 1 device/interrupt enable
|
|
FLG 1 device ready
|
|
FBF 1 device ready buffer
|
|
LCNT 7 line count within page
|
|
POS 32 position in the output file
|
|
CTIME 24 time between characters
|
|
PTIME 24 time for a print operation
|
|
STOP_IOE 1 stop on I/O error
|
|
|
|
Error handling is as follows:
|
|
|
|
error STOP_IOE processed as
|
|
|
|
not attached 1 report error and stop
|
|
0 out of tape or paper
|
|
|
|
OS I/O error x report error and stop
|
|
|
|
2.4.6 12539A/B/C Time Base Generator (CLK)
|
|
|
|
The time base generator (CLK) implements these registers:
|
|
|
|
name size comments
|
|
|
|
SEL 3 time base select
|
|
CTR 14 repeat counter for < 1Hz operation
|
|
CTL 1 device/interrupt enable
|
|
FLG 1 device ready
|
|
FBF 1 device ready buffer
|
|
ERR 1 error flag
|
|
TIME[0:7] 31 clock intervals, select = 0..7
|
|
DEVNO 6 current device number (read only)
|
|
|
|
The time base generator autocalibrates; the clock interval is adjusted
|
|
up or down so that the clock tracks actual elapsed time. Operation at
|
|
the fastest rates (100 usec, 1 msec) is not recommended.
|
|
|
|
2.4.7 12920A Terminal Multiplexor (MUXL, MUXU, MUXC)
|
|
|
|
The 12920A is a 16-line terminal multiplexor, with five additional
|
|
receive-only diagnostic lines. It consists of three devices:
|
|
|
|
MUX scanning logic (corresponding more or less
|
|
to the upper data card)
|
|
MUXL individual lines (corresponding more or
|
|
less to the lower data card)
|
|
MUXC modem control and status logic (corresponding
|
|
to the control card)
|
|
|
|
The MUX performs input and output through Telnet sessions connected to a
|
|
user-specified port. The ATTACH command to the scanning logic specifies
|
|
the port to be used:
|
|
|
|
ATTACH MUX <port> set up listening port
|
|
|
|
where port is a decimal number between 1 and 65535 that is not being used
|
|
for other TCP/IP activities.
|
|
|
|
Each line (each unit of MUXL) can be set to one of three modes: UC, 7B,
|
|
or 8B. In UC mode, lower case input and output characters are converted
|
|
automatically to upper case. In 7B mode, input and output characters
|
|
are masked to 7 bits. In 8B mode, characters are not modified. The
|
|
default mode is UC. In addition, each line supports the DATASET option.
|
|
DATASET, when set, enables modem control. The default settings are UC
|
|
mode and DATASET disabled.
|
|
|
|
The modem controls model a simplified Bell 103A dataset with just four
|
|
lines: data terminal ready and request to send from the computer to the
|
|
data set, and carrier detect and data set ready from the data set to
|
|
the computer. There is no ring detection. If data terminal ready is
|
|
set when a Telnet connection starts up, then carrier detect and data
|
|
set ready are also set. The connection is established whether data
|
|
terminal ready is set or not.
|
|
|
|
Once MUX is attached and the simulator is running, the multiplexor listens
|
|
for connections on the specified port. It assumes that the incoming
|
|
connections are Telnet connections. The connections remain open until
|
|
disconnected either by the Telnet client, a SET MUXL DISCONNECT command,
|
|
or a DETACH MUX command.
|
|
|
|
The SHOW MUX CONNECTIONS command displays the current connections to the
|
|
extra terminals. The SHOW MUX STATISTICS command displays statistics for
|
|
active connections. The SET MUX DISCONNECT=linenumber disconnects the
|
|
specified line.
|
|
|
|
The scanner (MUX) implements these registers:
|
|
|
|
name size comments
|
|
|
|
IBUF 16 input buffer, holds line status
|
|
OBUF 16 output buffer, holds channel select
|
|
|
|
The lines (MUXL) implements these registers:
|
|
|
|
name size comments
|
|
|
|
CTL 1 device/interrupt enable
|
|
FLG 1 device ready
|
|
FBF 1 device ready buffer
|
|
STA[0:20] 16 line status, lines 0-20
|
|
RPAR[0:20] 16 receive parameters, lines 0-20
|
|
XPAR[0:15] 16 transmit parameters, lines 0-15
|
|
RBUF[0:20] 8 receive buffer, lines 0-20
|
|
XBUF[0:15] 8 transmit buffer, lines 0-15
|
|
RCHP[0:20] 1 receive character present, lines 0-20
|
|
XDON[0:15] 1 transmit done, lines 0-15
|
|
TIME[0:15] 24 transmit time, lines 0-15
|
|
|
|
The modem control (MUXM) implements these registers:
|
|
|
|
name size comments
|
|
|
|
CTL 1 device/interrupt enable
|
|
FLG 1 device ready
|
|
FBF 1 device ready buffer
|
|
SCAN 1 scan enabled
|
|
CHAN 4 current line
|
|
DSO[0:15] 6 C2,C1,ES2,ES1,SS2,SS1, lines 0-15
|
|
DSI[0:15] 2 S2,S1, lines 0-15
|
|
|
|
|
|
The terminal multiplexor does not support save and restore. All open
|
|
connections are lost when the simulator shuts down or MUXU is detached.
|
|
|
|
2.4.8 Interprocessor Link (IPLI, IPLO)
|
|
|
|
The interprocessor link is a pair of 12556B parallel interfaces that
|
|
are cross coupled to provide interprocessor communications to a second
|
|
copy of the HP2100 simulator. The IPL is intended to support simulation
|
|
of a two system HP TimeShared Basic configuration. The links are actually
|
|
bidirectional half-duplex; TimeShared Basic uses them unidirectionally.
|
|
The IPL is disabled by default.
|
|
|
|
To operate, the IPL devices must be enabled and then connected to the IPL
|
|
devices in another copy of the simulator. The IPLI device in the first
|
|
simulator is connected to the IPLO device in the second, and vice versa.
|
|
Connections are established with the ATTACH command. One copy of the
|
|
simulator listens for connections on a specified port (ATTACH -L); the
|
|
other establishes connections to an IP address and port (ATTACH -C).
|
|
Either copy may perform either operation, but the operations must be
|
|
done in matched pairs:
|
|
|
|
simulator #1 simulator #2
|
|
|
|
sim> set ipli ena sim> set ipli ena
|
|
(also enables iplo) (also enables iplo)
|
|
sim> att -lw ipli 4000
|
|
Listening on port 4000
|
|
Waiting for connection
|
|
sim> att -c iplo 4000
|
|
Connection established Connected to 127.0.0.1 port 4000
|
|
sim> att -lw iplo 4000
|
|
Listening on port 4001
|
|
Waiting for connection
|
|
sim> att -c ipli 4001
|
|
Connection established Connected to 127.0.0.1 port 4000
|
|
|
|
Both forms of ATTACH take a modifier -W (wait); if specified, the command
|
|
will wait up to 30 seconds for the connection process to complete. ATTACH
|
|
-C can specify both an IP address and a port, in the form aa.bb.cc.dd:port;
|
|
if the IP address is omitted, it defaults to 127.0.0.1 (local system).
|
|
|
|
Both IPLI and IPLO implement the BOOT command. BOOT loads the HP Access
|
|
Basic Block Loader for the IOP into the top 64 words of memory and starts
|
|
it running.
|
|
|
|
Both IPLI and IPLO implement these registers:
|
|
|
|
name size comments
|
|
|
|
BUF 16 buffer
|
|
HOLD 8 holding buffer
|
|
CMD 1 device enable
|
|
CTL 1 device/interrupt enable
|
|
FLG 1 device ready
|
|
FBF 1 device ready buffer
|
|
TIME 24 polling interval for input
|
|
STOP_IOE 1 stop on I/O error
|
|
|
|
|
|
2.5 12557A Disk Controller (DPC, DPD) with 2781 Drives
|
|
13210A Disk Controller (DPC, DPD) with 7900 Drives
|
|
|
|
The 12557A/13210A disk controller can be configured as either a
|
|
12557A, supporting 2.5MB drives, or a 13210A, supporting 5MB drives,
|
|
with the commands:
|
|
|
|
SET DP 12557A 2.5MB drives
|
|
SET DP 13210A 5.0MB drives
|
|
|
|
Drive types cannot be intermixed; the controller is configured for
|
|
one type or the other. The 13210A (for 7900/7901 disks) is selected
|
|
by default.
|
|
|
|
The simulated controller has two separate devices, a data channel and
|
|
a device controller. The data channel includes a 128-word (one sector)
|
|
buffer for reads and writes. The device controller includes the four
|
|
disk drives. Disk drives can be set ONLINE or OFFLINE.
|
|
|
|
The 12557A/13210A supports the BOOT command. BOOT DP loads the IBL
|
|
for 7900 class disks into memory and starts it running. BOOT -F DP
|
|
boots from the fixed platter (head 2). The switch register (S) is
|
|
set automatically to the value expected by the IBL loader:
|
|
|
|
<15:14> = 01
|
|
<13:12> = 00
|
|
<11:6> = data channel device code
|
|
<5:1> = 00000
|
|
<0> = 1 if booting from the fixed platter
|
|
|
|
The data channel implements these registers:
|
|
|
|
name size comments
|
|
|
|
IBUF 16 input buffer
|
|
OBUF 16 output buffer
|
|
DBUF[0:127] 16 sector buffer
|
|
BPTR 7 sector buffer pointer
|
|
CMD 1 channel enable
|
|
CTL 1 interrupt enable
|
|
FLG 1 channel ready
|
|
FBF 1 channel ready buffer
|
|
XFER 1 transfer in progress flag
|
|
WVAL 1 write data valid flag
|
|
|
|
The device controller implements these registers:
|
|
|
|
name size comments
|
|
|
|
OBUF 16 output buffer
|
|
BUSY 3 busy (unit #, + 1, of active unit)
|
|
CNT 5 check record count
|
|
CMD 1 controller enable
|
|
CTL 1 interrupt enable
|
|
FLG 1 controller ready
|
|
FBF 1 controller ready buffer
|
|
EOC 1 end of cylinder pending
|
|
RARC[0:3] 8 record address register cylinder, drives 0-3
|
|
RARH[0:3] 2 record address register head, drives 0-3
|
|
RARS[0:3] 4 record address register sector, drives 0-3
|
|
STA[0:3] 16 drive status, drives 0-3
|
|
CTIME 24 data transfer command delay time
|
|
DTIME 24 data channel command delay time
|
|
STIME 24 seek delay time, per cylinder
|
|
XTIME 24 interword transfer time
|
|
|
|
Error handling is as follows:
|
|
|
|
error processed as
|
|
|
|
not attached disk not ready
|
|
|
|
end of file assume rest of disk is zero
|
|
|
|
OS I/O error report error and stop
|
|
|
|
2.6 12565A Disk Controller (DQC, DRC) with 2883 Drives
|
|
|
|
The 12565A disk controller has two separate devices, a data channel and
|
|
a device controller. The data channel includes a 128-word (one sector)
|
|
buffer for reads and writes. The device controller includes the two
|
|
disk drives. Disk drives can be set ONLINE or OFFLINE.
|
|
|
|
The 12565A supports the BOOT command. BOOT DQ loads the IBL for 2883
|
|
class disks into memory and starts it running. The switch register (S)
|
|
is set automatically to the value expected by the IBL loader:
|
|
|
|
<15:14> = 01
|
|
<13:12> = 10
|
|
<11:6> = data channel device code
|
|
<5:0> = 00000
|
|
|
|
The data channel implements these registers:
|
|
|
|
name size comments
|
|
|
|
IBUF 16 input buffer
|
|
OBUF 16 output buffer
|
|
DBUF[0:127] 16 sector buffer
|
|
BPTR 7 sector buffer pointer
|
|
CMD 1 channel enable
|
|
CTL 1 interrupt enable
|
|
FLG 1 channel ready
|
|
FBF 1 channel ready buffer
|
|
XFER 1 transfer in progress flag
|
|
WVAL 1 write data valid flag
|
|
|
|
The device controller implements these registers:
|
|
|
|
name size comments
|
|
|
|
OBUF 16 output buffer
|
|
BUSY 2 busy (unit #, + 1, of active unit)
|
|
CNT 9 check record count
|
|
CMD 1 controller enable
|
|
CTL 1 interrupt enable
|
|
FLG 1 controller ready
|
|
FBF 1 controller ready buffer
|
|
RARC[0:1] 8 record address register cylinder, drives 0-1
|
|
RARH[0:1] 5 record address register head, drives 0-1
|
|
RARS[0:1] 5 record address register sector, drives 0-1
|
|
STA[0:1] 16 drive status, drives 0-3
|
|
CTIME 24 data transfer command delay time
|
|
DTIME 24 data channel command delay time
|
|
STIME 24 seek delay time, per cylinder
|
|
XTIME 24 interword transfer time
|
|
|
|
Error handling is as follows:
|
|
|
|
error processed as
|
|
|
|
not attached disk not ready
|
|
|
|
end of file assume rest of disk is zero
|
|
|
|
OS I/O error report error and stop
|
|
|
|
2.7 12606B Fixed Head Disk Controller (DRC, DRD) with 2770/2771 Disk
|
|
12610B Drum Controller (DRC, DRD) with 2773/2774/2775 Drum
|
|
|
|
The 12606B/12610B fixed head disk/drum controller has two separate devices,
|
|
a data channel and a device controller. The device controller includes the
|
|
actual drive. Ten different models are supported:
|
|
|
|
SET DRC 180K 12606B, 180K words
|
|
SET DRC 360K 12606B, 360K words
|
|
SET DRC 720K 12606B, 720K words
|
|
SET DRC 384K 12610B, 84K words
|
|
SET DRC 512K 12610B, 512K words
|
|
SET DRC 640K 12610B, 640K words
|
|
SET DRC 768K 12610B, 768K words
|
|
SET DRC 896K 12610B, 896K words
|
|
SET DRC 1024K 12610B, 1024K words
|
|
SET DRC 1536K 12610B, 1536K words
|
|
|
|
The 12606B/12610B support the BOOT command. The BOOT command loads the
|
|
first sector from the disk or drum into locations 0-77 and then jumps to 77.
|
|
This is very different from the IBL loader protocol used by the 12565A and
|
|
the 12557A/13210A.
|
|
|
|
The data channel implements these registers:
|
|
|
|
name size comments
|
|
|
|
IBUF 16 input buffer
|
|
OBUF 16 output buffer
|
|
CMD 1 channel enable
|
|
CTL 1 interrupt enable
|
|
FLG 1 channel ready
|
|
FBF 1 channel ready buffer
|
|
BPTR 6 sector buffer pointer
|
|
|
|
The device controller implements these registers:
|
|
|
|
name size comments
|
|
|
|
CW 16 command word
|
|
STA 16 status
|
|
CMD 1 controller enable
|
|
CTL 1 interrupt enable
|
|
FLG 1 controller ready
|
|
FBF 1 controller ready buffer
|
|
TIME 24 interword transfer time
|
|
STOP_IOE 1 stop on I/O error
|
|
|
|
Error handling is as follows:
|
|
|
|
error processed as
|
|
|
|
not attached disk not ready
|
|
|
|
12606B/12610B data files are buffered in memory; therefore, end of file
|
|
and OS I/O errors cannot occur.
|
|
|
|
2.8 12559C Magnetic Tape Controller (MTC, MTD) with 3030 Drive
|
|
|
|
Magnetic tape options include the ability to make the unit write enabled
|
|
or write locked.
|
|
|
|
SET MTC LOCKED set unit write locked
|
|
SET MTC WRITEENABLED set unit write enabled
|
|
|
|
The 12559C mag tape drive has two separate devices, a data channel and
|
|
a device controller. The data channel includes a maximum record sized
|
|
buffer for reads and writes. The device controller includes the tape
|
|
unit.
|
|
|
|
The BOOT command is not supported. The 12559C was HP's earliest tape
|
|
drive and is not supported by most of its operating systems. It is
|
|
disabled by default.
|
|
|
|
The data channel implements these registers:
|
|
|
|
name size comments
|
|
|
|
FLG 1 channel ready
|
|
DBUF[0:65535] 8 transfer buffer
|
|
BPTR 16 buffer pointer (reads and writes)
|
|
BMAX 16 buffer size (writes)
|
|
|
|
The device controller implements these registers:
|
|
|
|
name size comments
|
|
|
|
FNC 8 current function
|
|
STA 9 tape status
|
|
BUF 8 buffer
|
|
CTL 1 interrupt enabled
|
|
FLG 1 controller ready
|
|
FBF 1 controller ready buffer
|
|
DTF 1 data transfer flop
|
|
FSVC 1 first service flop
|
|
POS 32 magtape position
|
|
CTIME 24 command delay time
|
|
XTIME 24 interword transfer delay time
|
|
STOP_IOE 1 stop on I/O error
|
|
|
|
Error handling is as follows:
|
|
|
|
error processed as
|
|
|
|
not attached tape not ready; if STOP_IOE, stop
|
|
|
|
end of file parity error
|
|
|
|
OS I/O error parity error; if STOP_IOE, stop
|
|
|
|
2.9 13181A Magnetic Tape Controller (MSC, MSD) with 7970B Drives
|
|
18183A Magnetic Tape Controller (MSC, MSD) with 7970E Drives
|
|
|
|
Magnetic tape options include the ability to make the unit write enabled
|
|
or write locked, and the ability to select the 13181A (800 bpi) controller
|
|
or the 13183A (1600 bpi) controller.
|
|
|
|
SET MTn LOCKED set unit n write locked
|
|
SET MTn WRITEENABLED set unit n write enabled
|
|
SET MT 13181A set controller to 13181A
|
|
SET MT 13183A set controller to 13183A
|
|
|
|
The 13181A/13183A mag tape drive has two separate devices, a data channel
|
|
and a device controller. The data channel includes a maximum record
|
|
sized buffer for reads and writes. The device controller includes the
|
|
tape units.
|
|
|
|
The 13181A/13183A supports the BOOT command. BOOT MS loads the IBL for
|
|
7970B/E magnetic tape drives into memory and starts it running. BOOT -S
|
|
MS causes the loader to space forward the number of files specified in
|
|
the A register before starting to load data. The switch register (S) is
|
|
set automatically to the value expected by the IBL loader:
|
|
|
|
<15:14> = 10
|
|
<13:12> = 00
|
|
<11:6> = data channel device code
|
|
<5:1> = 00000
|
|
<0> = 1 if space forward before loading
|
|
|
|
The data channel implements these registers:
|
|
|
|
name size comments
|
|
|
|
BUF 16 data buffer
|
|
CTL 1 interrupt enabled
|
|
FLG 1 channel ready
|
|
FBF 1 channel ready buffer
|
|
DBUF[0:65535] 8 transfer buffer
|
|
BPTR 17 buffer pointer (reads and writes)
|
|
BMAX 17 buffer size (writes)
|
|
|
|
The device controller implements these registers:
|
|
|
|
name size comments
|
|
|
|
STA 12 tape status
|
|
BUF 16 buffer
|
|
USEL 2 currently selected unit
|
|
FSVC 1 first service flop
|
|
CTL 1 interrupt enabled
|
|
FLG 1 controller ready
|
|
FBF 1 controller ready buffer
|
|
POS[0:3] 32 magtape position
|
|
CTIME 24 command delay time
|
|
XTIME 24 interword transfer delay time
|
|
STOP_IOE 1 stop on I/O error
|
|
|
|
Error handling is as follows:
|
|
|
|
error processed as
|
|
|
|
not attached tape not ready; if STOP_IOE, stop
|
|
|
|
end of file parity error
|
|
|
|
OS I/O error parity error; if STOP_IOE, stop
|
|
|
|
2.10 Symbolic Display and Input
|
|
|
|
The HP2100 simulator implements symbolic display and input. Display is
|
|
controlled by command line switches:
|
|
|
|
-a display as ASCII character
|
|
-c display as two character string
|
|
-m display instruction mnemonics
|
|
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Input parsing is controlled by the first character typed in or by command
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line switches:
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' or -a ASCII character
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" or -c two character sixbit string
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alphabetic instruction mnemonic
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numeric octal number
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Instruction input uses standard HP2100 assembler syntax. There are seven
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instruction classes: memory reference, I/O, shift, alter skip, extended
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shift, extended memory reference, extended two address reference.
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Memory reference instructions have the format
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memref {C/Z} address{,I}
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where I signifies indirect, C a current page reference, and Z a zero page
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reference. The address is an octal number in the range 0 - 077777; if C or
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Z is specified, the address is a page offset in the range 0 - 01777. Normally,
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C is not needed; the simulator figures out from the address what mode to use.
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However, when referencing memory outside the CPU (eg, disks), there is no
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valid PC, and C must be used to specify current page addressing.
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IOT instructions have the format
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io device{,C}
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where C signifies that the device flag is to be cleared. The device is an
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octal number in the range 0 - 77.
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Shift and alter/skip instructions have the format
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sub-op sub-op sub-op...
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The simulator checks that the combination of sub-opcodes is legal.
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Extended shift instructions have the format
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extshift count
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where count is an octal number in the range 1 - 020.
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Extended memory reference instructions have the format
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extmemref address{,I}
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where I signifies indirect addressing. The address is an octal number in
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the range 0 - 077777.
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Extended two address instructions have the format
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ext2addr addr1{,I},addr2{,I}
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where I signifies indirect addressing. Both address 1 and address 2 are
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octal numbers in the range 0 - 077777.
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