folkert/simh-testsetgenerator
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
simh-testsetgenerator/Interdata/id_diag.txt
Bob Supnik 2bcd1e7c4c Notes For V2.10-2 
1. New Features in 2.10-2

The build procedures have changed.  There is only one UNIX makefile.
To compile without Ethernet support, simply type

	gmake {target|all}

To compile with Ethernet support, type

	gmake USE_NETWORK=1 {target|all}

The Mingw batch files require Mingw release 2 and invoke the Unix
makefile.  There are still separate batch files for compilation
with or without Ethernet support.

1.1 SCP and Libraries

- The EVAL command will evaluate a symbolic type-in and display
  it in numeric form.
- The ! command (with no arguments) will launch the host operating
  system command shell.  The ! command (with an argument) executes
  the argument as a host operating system command.  (Code from
  Mark Pizzolato)
- Telnet sessions now recognize BREAK.  How a BREAK is transmitted
  dependent on the particular Telnet client.  (Code from Mark
  Pizzolato)
- The sockets library includes code for active connections as
  well as listening connections.
- The RESTORE command will restore saved memory size, if the
  simulator supports dynamic memory resizing.

1.2 PDP-1

- The PDP-1 supports the Type 24 serial drum (based on recently
  discovered documents).

1.3 18b PDP's

- The PDP-4 supports the Type 24 serial drum (based on recently
  discovered documents).

1.4 PDP-11

- The PDP-11 implements a stub DEUNA/DELUA (XU).  The real XU
  module will be included in a later release.

1.5 PDP-10

- The PDP-10 implements a stub DEUNA/DELUA (XU).  The real XU
  module will be included in a later release.

1.6 HP 2100

- The IOP microinstruction set is supported for the 21MX as well
  as the 2100.
- The HP2100 supports the Access Interprocessor Link (IPL).

1.7 VAX

- If the VAX console is attached to a Telnet session, BREAK is
  interpreted as console halt.
- The SET/SHOW HISTORY commands enable and display a history of
  the most recently executed instructions.  (Code from Mark
  Pizzolato)

1.8 Terminals Multiplexors

- BREAK detection was added to the HP, DEC, and Interdata terminal
  multiplexors.

1.9 Interdata 16b and 32b

- First release.  UNIX is not yet working.

1.10 SDS 940

- First release.

2. Bugs Fixed in 2.10-2

- PDP-11 console must default to 7b for early UNIX compatibility.
- PDP-11/VAX TMSCP emulator was using the wrong packet length for
  read/write end packets.
- Telnet IAC+IAC processing was fixed, both for input and output
  (found by Mark Pizzolato).
- PDP-11/VAX Ethernet setting flag bits wrong for chained
  descriptors (found by Mark Pizzolato).

3. New Features in 2.10 vs prior releases

3.1 SCP and Libraries

- The VT emulation package has been replaced by the capability
  to remote the console to a Telnet session.  Telnet clients
  typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
  in addition to dynamically allocated buffers or disk-based
  data stores.
- The DO command now takes substitutable arguments (max 9).
  In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
  name and substitutable arguments for a DO command.  This is
  backward compatible to prior versions.
- The initial command line parses switches.  -Q is interpreted
  as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument.  HELP <cmd>
  types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
  as well as simulator-specific command extensions.  A few
  internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
  been added to sim_tmxr.c.  The calling sequence for
  sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
  to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.

3.2 VAX

- Non-volatile RAM (NVR) can behave either like a memory or like
  a disk-based peripheral.  If unattached, it behaves like memory
  and is saved and restored by SAVE and RESTORE, respectively.
  If attached, its contents are loaded from disk by ATTACH and
  written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
  now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
  the CPU.
- Device address conflicts are not detected until simulation starts.

3.3 PDP-11

- SHOW <device> VECTOR displays the device's interrupt vector.
  Most devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
  RX211 (double density floppy), and KW11P programmable clock
  have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
  now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
  SET ADDRESS command, rather than just the default CSR.  Note
  that PDP-11 operating systems may NOT support booting with
  non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
  configuration, causes all peripherals that are not compatible
  with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.

3.4 PDP-10

- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
  by default.
- The paper tape now references a common implementation file,
  dec_pt.h.
- Device address conflicts are not detected until simulation starts.

3.5 PDP-1

- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.

3.6 PDP-8

- The RX28 (double density floppy) has been added as an option to
  the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number.  Most
  devices allow the device number to be changed with SET <device>
  DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.

3.7 IBM 1620

- The IBM 1620 simulator has been released.

3.8 AltairZ80

- A hard drive has been added for increased storage.
- Several bugs have been fixed.

3.9 HP 2100

- The 12845A has been added and made the default line printer (LPT).
  The 12653A has been renamed LPS and is off by default.  It also
  supports the diagnostic functions needed to run the DCPC and DMS
  diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
  instructions for the 2116.  These instructions are standard on
  the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
  2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
  instructions for the 21MX.
- The 12539 timebase generator autocalibrates.

3.10 Simulated Magtapes

- Simulated magtapes recognize end of file and the marker
  0xFFFFFFFF as end of medium.  Only the TMSCP tape simulator
  can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
  consistent through all simulators.

3.11 Simulated DECtapes

- Added support for RT11 image file format (256 x 16b) to DECtapes.

4. Bugs Fixed in 2.10 vs prior releases

- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
  under VMS.  In addition, two of the CTL options were coded
  interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
  load mode reads.  This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
  Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
  21MX, DMS, and IOP instructions were fixed.  Bugs were also fixed
  in the memory protect and DMS functions.  The moving head disks
  (DP, DQ) were revised to simulate the hardware more accurately.
  Missing functions in DQ (address skip, read address) were added.
- PDP-10 tape wouldn't boot, and then wouldn't read (reported by
  Michael Thompson and Harris Newman, respectively)
- PDP-1 typewriter is half duplex, with only one shift state for
  both input and output (found by Derek Peschel)

5. General Notes

WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX.  Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.

WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.

WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.

WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file.  Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.
2011-04-15 08:33:56 -07:00

908 lines
17 KiB
Text
Raw Blame History

Interdata Diagnostics
Summary
816E CPU diagnostic, part 1 passed 16b n/a
816E CPU diagnostic, part 2 partial 16b n/a
Series 16 CPU diagnostic, part 1 passed 16b n/a
16b memory diagnostic, part 1 passed 16b n/a
16b memory diagnostic, part 2 passed 16b n/a
816e extended memory diagnostic passed 16b n/a
Series 16 selector channel diagnostic passed 16b n/a
32b CPU diagnostic, part 1 n/a passed 32b
32b CPU diagnostic, part 2 n/a passed 32b
32b CPU diagnostic, part 3 n/a passed 32b
32b memory diagnostic, part 1 n/a passed 32b
32b memory diagnostic, part 2 n/a passed 32b
32b memory diagnostic, part 3 n/a passed 32b
32b memory diagnostic 6a, part 1 n/a passed 32b
32b memory diagnostic 6a, part 2 n/a passed 32b
32b MAC diagnostic, part 1 n/a passed 32b
32b MAC diagnostic, part 2 n/a passed 32b
Common line printer diagnostic passed 16b passed 32b
Common magtape diagnostic passed 16b passed 32b
Common 2.5/10MB disk diagnostic passed 16b passed 32b
32b MSM disk diagnostic passed 32b
Common floppy disk diagnostic passed 16b passed 32b
Common clock diagnostic passed 16b passed 32b
Not tested:
- 16b floating point
- 32b double precision floating point
- IDC
- PASLA
-------------------------------------------------------------------
Operating Instructions
816E CPU diagnostic, part 1
sim> set cpu 816e
sim> att -e pt0 diag.bin
sim> br c2
sim> boot pt0
Breakpoint: PC: 00C2 (EXBR R8,R6)
sim> run 100
MODEL 8/16E PROCESSOR TEST PART 1 06-211R00
CPU
* 8D
ENTER 0 OR 1
1
NO ERROR
CPU
*
---
816E CPU diagnostic, part 2
sim> set cpu 816e
sim> d tt ttime 1000 ; timing dependency
sim> att -e pt0 diag.bin
sim> br c2
sim> boot pt0
Breakpoint: PC: 00C2 (EXBR R8,R6)
sim> run 100
MODEL 8/16E PROCESSOR TEST PART 2 06-212R00
CPU
* 8D
SUBTEST
* (type subtest number)
Subtests 0, 1, 2, 5, 7, 8, 9 run correctly
Subtest 3, 4 cannot be run (initialization, power fail)
Subtest 6 cannot be run (hexadecimal display)
---
Series 16 CPU diagnostic, part 1
(Central error routine is at 21F4)
sim> set cpu 816e
sim> att -e pt0 diag.bin ; diagnostic
sim> br c0
sim> boot pt0
Breakpoint, PC: 00C0 (8800)
sim> d 234a 0202 ; patch to use
sim> d 234c a4a8 ; TTY as console
sim> d 17a b1e4
sim> run 100
SERIES SIXTEEN PROCESSOR TEST PART 1 06-242F01R00
CPU
* 2D
ENTER 0 OR 1
1
1234567890
NO ERROR
000A 0000
CPU
*
---
16b memory diagnostic, part 1
sim> att -e pt0 diag.bin ; diagnostic
sim> br c2
sim> boot pt0
Breakpoint, PC: 00C2 (EPSR R7,R6)
sim> run 100
02-340 PART 1 06-162F01R01
NO ERRORS
---
16b memory diagnostic, part 2
sim> att -e pt0 diag.bin ; diagnostic
sim> br c2
sim> boot pt0
Breakpoint, PC: 00C2 (EPSR R7,R6)
sim> run 1000
02-340 PART 2 06-162F02R01
NO ERRORS
---
816e extended memory diagnostic, parts 1 and 2
sim> set cpu 816e
sim> set cpu 256k
sim> att -e pt0 diag.bin ; diagnostic
sim> br b4
sim> boot pt0
Breakpoint, PC: 00B4 (LPSW R0,B8)
sim> run 1000
8/16 E EXTENDED MEMORY TEST PART 1 06-221R00
NO ERROR
* (CR to repeat part 1)
8/16 E EXTENDED MEMORY TEST PART 1 06-221R00
NO ERROR
* (LF to go on to part 2)
Breakpoint, PC: 00B4 (LPSW R0,B8)
sim> run 100
8/16 E EXTENDED MEMORY TEST PART 2 06-221R00
PROGRAM DETECTED MAXIMUM MEMORY 3FFFE
*TEST ; standard tests
*RUN
SUBTEST 0 NO ERROR
SUBTEST 1 NO ERROR
SUBTEST 2 NO ERROR
SUBTEST 3 NO ERROR
SUBTEST 4 NO ERROR
SUBTEST 6 NO ERROR
SUBTEST 7 NO ERROR
SUBTEST 8 NO ERROR
END OF TEST
*
---
Series 16 selector channel diagnostic
sim> set cpu 816e
sim> set cpu 256k
sim> att -e pt0 diag.bin ; diagnostic
sim> att mt0 foo.tap ; magtape to test
sim> br c0
sim> boot pt0
Breakpoint, PC: 00C0 (LPSW R0,C8)
sim> d 2e68 2 ; console is TTY
sim> run A00
S16 SELCH TEST 06-222 R01
TOP OF MEMORY 3 FFFF
* IODEV1 C5 ; magtape
* DEV1 2
* RUN ; bank 0 by default
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
TEST 04
NO ERROR
* MEMMOD 1 {2,3} ; repeat for banks 1,2,3
* RUN
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
TEST 04
NO ERROR
*
---
32b CPU diagnostic, part 1
sim> att -e mt0 mmd_r07.tap
sim> d -b 7f 7 ; file 8 on MMD R07 tape
sim> boot mt0
S32PT1 06-154 R03
CPU
*7X
NO ERROR
000A 0000
*
---
32b CPU diagnostic, part 2
sim> set tt 7b ; test is parity sensitive
sim> att -e mt0 mmd_r07.tap
sim> d -b 7f 8 ; file 9 on MMD R07 tape
sim> boot mt0
S32PT2R02
CPU
*
7X
SUBTEST
* (type subtest number)
Subtests 1, 3, 4, 5, 9 run correctly
Subtest 2 cannot be run (7/32 with halfword mode only)
Subtest 6 cannot be run (hexadecimal display)
Subtests 7,8 cannot be run (initialization, power fail)
---
32b CPU diagnostic, part 3
sim> att -e mt0 mmd_r07.tap
sim> d -b 7f 9 ; file 10 on MMD R07 tape
sim> boot mt0
S32PT3 R01
CPU
*
8X ; 7X denotes 7/32 with halfword mode
MAC RESPONSE AT 000300
SUBTEST
*
Subtests 1, 2, 3 run correctly
Subtest 4 cannot be run (parity option)
---
32b memory diagnostic, part 1
sim> att -e mt0 mmd_r07.tap
sim> d -b 7f 17 ; file 24 on MMD R07 tape
sim> br 2000
sim> boot mt0
Breakpoint, PC: 02000 (B 2060)
sim> d -w 2010 0202 ; console is TTY
sim> c
S32MT1 06-156F01R04
MAC PRESENT ? (Y OR N)
*
Y
01
02
03
04
05
06
NO ERROR
*
---
32b memory diagnostic, part 2
sim> att -e mt0 c:\temp\mmd_r07.tap
sim> d -b 7f 18 ; file 25 on MMD R07 tape
sim> br a00
sim> boot mt0
Breakpoint, PC: 00A00 (B A60)
sim> d -w a10 0202 ; console is TTY
sim> c
S32MT2 06-156F02R04
AVAILABLE MEMORY
000000 - 0FFFFF
SUBTEST *
0 ; all standard tests
01
TEST STILL RUNNING ; repeated multiple times
:
NO ERROR
02
TEST STILL RUNNING ; repeated multiple times
:
NO ERROR
03
TEST STILL RUNNING ; repeated multiple times
:
NO ERROR
04
TEST STILL RUNNING ; repeated multiple times
:
NO ERROR
05
TEST STILL RUNNING ; repeated multiple times
:
NO ERROR
06
TEST STILL RUNNING ; repeated multiple times
:
NO ERROR
07
TEST STILL RUNNING ; repeated multiple times
:
NO ERROR
SUBTEST *
---
32b memory diagnostic, part 3
sim> att -e mt0 c:\temp\mmd_r07.tap
sim> d -b 7f 19 ; file 26 on MMD R07 tape
sim> br a00
sim> boot mt0
Breakpoint, PC: 00A00 (B A60)
sim> d -w a10 0202 ; console is TTY
sim> c
S32MT3 06-156F03R04
AVAILABLE MEMORY
000000 - 0FFFFF
*
TEST STILL RUNNING ; repeated multiple times
:
NO ERROR
*
---
32b memory diagnostic, 6a, part 1
sim> att -e mt0 c:\temp\mmd_r07.tap
sim> d -b 7f 15 ; file 22 on MMD R07 tape
sim> boot mt0
32 BIT S6A MEMORY TEST 06-157F01R01
AVAILABLE MEMORY
0000-3FFF
MAC ADDRESS = 300
TYPE= 3 ; any value, 0-4
SUBTEST
* 0
01
NO ERROR
02
NO ERROR
03
NO ERROR
04
NO ERROR
05
NO ERROR
06
NO ERROR
07
NO ERROR
08
NO ERROR
SUBTEST
*
---
32b memory diagnostic, 6a, part 2
sim> att -e mt0 c:\temp\mmd_r07.tap
sim> d -b 7f 16 ; file 23 on MMD R07 tape
sim> boot mt0
32 BIT S6A MEMORY TEST 06-157F02R01
AVAILABLE MEMORY
0000f-FFFFF
TYPE= 2 ; any value, 0-4
SUBTEST
* 0
01
NO ERROR
02
NO ERROR
03
NO ERROR
04
NO ERROR
05
NO ERROR
06
NO ERROR
07
NO ERROR
08
NO ERROR
SUBTEST
*
---
32b MAC diagnostic, part 1
sim> att -e mt0 c:\temp\mmd_r07.tap
sim> d -b 7f 24 ; file 37 on MMD R07 tape
sim> boot mt0
MACT 06-160F01R03
AVAILABLE MEMORY
00000- FFFFF
* RUN
TEST 00 NO ERROR
TEST 01 NO ERROR
TEST 02 NO ERROR
TEST 03 NO ERROR
TEST 04 NO ERROR
TEST 05 NO ERROR
TEST 06 NO ERROR
TEST 07 NO ERROR
TEST 08 NO ERROR
TEST 09 NO ERROR
TEST 0B NO ERROR
*
---
sim> att -e mt0 c:\temp\mmd_r07.tap
sim> d -b 7f 25 ; file 38 on MMD R07 tape
sim> br ffd0 ; start != load point
sim> boot mt0
Breakpoint, PC: 0FFD0 (B 1093E)
sim> run 10010
MACT 06-160F02R03
* RUN
TEST 00 NO ERROR
TEST 01 NO ERROR
TEST 02 NO ERROR
TEST 03 NO ERROR
TEST 04 NO ERROR
TEST 05 NO ERROR
TEST 06 NO ERROR
TEST 07 NO ERROR
TEST 08 NO ERROR
*
---
Common line printer diagnostic
sim> att -e pt0 diag.bin
sim> br c2
sim> boot pt0
Breakpoint: PC: 00C2 (EXBR R8,R6)
sim> run a00 ; 32b
sim> run a04 ; 16b
COMMON LINE PRINTER TEST 06-170R02
*TEST 0,1,2,3
*RUN
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
END OF TEST
*INTRPT 1
*RUN
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
END OF TEST
*
---
Common magtape diagnostic
sim> set mt dev=85 ; 800 bpi default
sim> att -e pt0 diag.bin
sim> br c4
sim> boot pt0
Breakpoint, PC: 00C4 (EXBR R8,R6)
sim> run a00 ; 32b
sim> run a04 ; 16b
COMMON MAGNETIC TAPE TEST PROGRAM 06-172R02
*TEST 0,1,2,3,4,5
*MODE 0 ; prog i/o and selch
*RUN
*MODE 0
*RUN
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
TEST 04
NO ERROR
TEST 05
NO ERROR
END OF TEST
*
---
Common 2.5/10MB disk diagnostic
sim> att -e pt0 diag.bin
sim> br c2
sim> boot pt0
Breakpoint, PC: 00C2 (EXBR R8,R6)
sim> set dp0 5440
sim> set dp1 5440
sim> att dp0 test0.dsk
sim> att dp1 test1.dsk
sim> run a00 ; 32b
sim> run a04 ; 16b
COMMON DISC TEST 06-173R01F01
*FILE 2 ; FILE 1 to test fixed platter
*LOCYL 0
*HICYL 197
*TIMCON 1C0
*TEST 0,1,2,3,4,6,7,8,9,A,C ; test 5 requires format capability
; test B requires manual intervention
*RUN
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
TEST 04
NO ERROR
TEST 06
NO ERROR
TEST 07
NO ERROR
TEST 08
NO ERROR
TEST 09
NO ERROR
TEST 0A
NO ERROR
TEST 0C
NO ERROR
END OF TEST
*
---
32b MSM disk diagnostic
sim> att -e mt0 c:\temp\mmd_r07.tap
sim> d -b 7f 45 ; file 70 on MMD R07 tape
sim> br a00
sim> boot mt0
Breakpoint, PC: 00A00 (B A5E)
sim> d -w a10 0101 ; patch for TTY console
sim> att dm0 foo.dsk
sim> att dm1 foo1.dsk
sim> c
MSM DISC TEST 06-200F02R04 (32-BIT)
*LOCYL 0
*HICYL 336 ; tests 8,9,A will run a very long
; time, use 40 to shorten test
*DRIVE 0
*PACTYP 0
*TIMVAL 14D
*XFILE 1
*TEST 0,1,2,3,4,6,7,8,9,A,C ; test 5 requires format capability
; test B requires manual intervention
*RUN
TEST 00
TEST 01
TEST 02
TEST 03
TEST 04
TEST 06
TEST 07
TEST 08
TEST 09
TEST 0A
TEST 0C
---
Common floppy disk diagnostic
sim> att -e pt0 diag.bin
sim> att fd0 foo0.flp
sim> att fd1 foo1.flp
sim> br b8
sim> boot pt0
Breakpoint, PC: 000B8 (BS B2)
sim> d 2a72 bal r15,320a ; patch for multidrive test
sim> run a00 ; 32b
sim> run a04 ; 16b
COMMON FLOPPY DISC TEST 06-198R00
UNPROTECT DISKETTE
*DRIVE AB
*RUN
DRIVE A UNDER TEST
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
TEST 04
NO ERROR
TEST 05
NO ERROR
TEST 06
NO ERROR
TEST 07
NO ERROR
DRIVE B UNDER TEST
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
TEST 04
NO ERROR
TEST 05
NO ERROR
TEST 06
NO ERROR
TEST 07
NO ERROR
END OF TEST
*TEST 9 ; test 8 requires formatting
*RUN
TEST 09
NO ERROR
END OF TEST
*
---
Common clock diagnostic
sim> att -e pt0 diag.bin
sim> br c4
sim> boot pt0
Breakpoint, PC: 00C4 (EXBR R8,R6)
sim> d -w e28 4300 ; R09 patches
sim> d -w e2a 10f4
sim> id -w 10f4:110a
10f4: 4840
10f6: 188a
10f8: 4850
10fa: 188c
10fc: de40
10fe: 1eaf
1100: de50
1102: 1eaf
1104: 4810
1106: 0a24
1108: 4300
1110: 0e2c
sim> d 1b9c bs 1ba6
sim> d -w 1102 1eaf
sim> run a00 ; 32b
sim> run a04 ; 16b
COMMON UNIVERSAL CLOCK MODULE TEST 06-133R05
*TIMVAL 1A4 ; simulator is a fast CPU
*RUN
TEST 00
NO ERROR
TEST 01
NO ERROR
TEST 02
NO ERROR
TEST 03
NO ERROR
TEST 04
NO ERROR
TEST 05
NO ERROR
TEST 06
NO ERROR
TEST 07
NO ERROR
END OF TEST
*
-------------------------------------------------------------------
Bugs found
1. CPU16: instruction decoding interpreting CPU models incorrectly
2. CPU16: SINT should not be conditional on device existing
3. CPU16: immediate interrupts do not do a PSW swap, new PC is block+6
4. CPU16: SLA, SLHA setting C incorrectly
5. CPU16: diagnostic requires 816E extended memory to run
6. CPU16: CCW16_OC defined incorrectly
7. CPU16, CPU32: autoload not fetching or outputing OC
8. CPU16, CPU32: block I/O completion is off by 1
9. CPU16, CPU32: ESPR broken, EPSR rx,rx should copy PSW to rx
10. CPU16, CPU32: PCQ displays in octal instead of hexadecimal
11. CPU16, CPU32: SH and variations overflow calculation wrong
12. CPU16, CPU32: SCH overflow calculation wrong
13. CPU16, CPU32: CH and CLH overflow calculation wrong
14. CPU16, CPU32: CH or'ing into CC's instead of loading
15. CPU16, CPU32: RD, RH, SS, AI store some data on non-existent device
16. CPU16, CPU32: console interrupt not implemented
17. CPU16, CPU32: SRHL(s) setting C incorrectly
18. CPU16, CPU32: WDR, OCR not masking register data to 8b
19. CPU32: WH not masking data to 8b or 16b as required
20. CPU32: 32b register sets ordered incorrectly in memory
21. CPU32: wrong slot length in queue instructions
22. CPU32: display device missing its interrupt declaration
23. CPU32: LPSW(R) must load PC before changing PSW
24. CPU32: SLL setting C incorrectly
25. CPU32: bit instructions use halfword memory access and offsets
26. CPU32: CRC sign-extending rather than zero-extending operands
27. CPU32: SCP incrementing counts before, not after, transfer
28. CPU32: CHVR not implemented
29. CPU32: M(R) algorithm wrong
30. CPU32: M(R) using wrong register as first operand
31. CPU32: memory accesses were fullword rather than halfword aligned
32. CPU32: D(R) overflow calculation incorrect
33. CPU32: on 7/32, exceptions use register set 0, regardless of new PSW
34. CPU32: system queue PSW location misdefined
35. CPU32: autodriver channel not shifting bytes left before use as
translation table index
36. CPU32: MAC, LRA using wrong value for limit test
37. CPU32: LRA using wrong value for segment base
38. CPU32: MAC registers are accessible only if protection is off
39. CPU32: MAC status clears only on write, not read
40. CPU32: MAC write protect abort and interrupts implemented incorrectly
41. CPU32: ex/dep -v test used & instead of &&
42. CPU32: fetch tests for MAC abort at end of fetch, not per halfword
43. FP: unpack and pack detecting RR format incorrectly
44. FP: need separate microcode/hardware algorithms for add/sub denormalization
45. FP: multiply and divide have 'early out' detection of overflow/underflow
46. FP: compare less than not setting C
47. FP: fix overflow not setting V
48. FP: fix shift needed to be hex digits not binary digits
49. IO: interrupt evaluation routine never sets an interrupt
50. SELCH: transfer count calculation off by 1
51. SELCH: device data structure set up incorrectly (reset routine)
52. SELCH: stop clears pending interrupts
53. SELCH: register load algorithm incorrect for 6 byte loads
54. PT, LPT, FD: OR'ing status mask instead of AND'ing
55. PT, TT: SET_INT on status change not conditioned on interrupt armed
56. TT: input char converted to UC incorrectly
57. TT: need SET TT BREAK to run CPU test part 2
58. LPT: not clearing spacing done
59. MT: WREOF not setting EOF status
60. MT: CMD register pointer to wrong place
61. MT: write record byte count taken from wrong variable
62. MT: overrun processing incorrect for selector channel mode
63. PIC, LFC: write data and overflow detection incorrect
64. PIC, LFC: interpolation algorithm for cic read incorrect
65. PIC, LFC: ric reloaded from output buffer on count overflow
66. PIC, LFC: added diagnostic mode, revised use of count vs timer
67. DP: track increment algorithm incorrect
68. DP,IDC: incorrectly setting overrun for less than full sector reads
69. DP: should interrupt on detach (offline)
70. FD: high water mark not updated on write
71. FD: deleted data not implemented, required for diagnostic
72. FD: header CRC not implemented, required for diagnostic
73. FD: function code not stored for service routine
74. FD: LRN to track and sector conversions incorrect
75. FD: reset status incorrect (should be not busy, LRN = 1)
76. FD: extended status track 0 calculation wrong
77. FD: reset does not clear interrupts, requires delay
78. FD: read/write sequencing incorrect
79. FD: command without write data uses implicit LRN
80. FD: extended status is per drive not per controller
81. FD: command start clears only extended status bytes 0,1
82. FD: IDLE sets after BUSY drops and generates a separate interrupt
83. SYS16, SYS32: WH mistyped as WD in symbol table
84. SYS32: MHR, DHR misdefined
85. PAS: busy set instead of cleared initially
86. IDC: busy set instead of cleared initially
87. IDC, DP: busy not cleared at transfer command complete
88. IDC: busy is not cleared at drive command complete
89. IDC: for MSM compatibility, must absorb WH of head/cylinder
90. IDC: drive command 0x30 is an instant NOP
91. IDC: set cylinder with invalid cylinder sets SKI
92. IDC: read with invalid head sets ACF, not DTE
Reference in a new issue View git blame Copy permalink