7d432406b6
Remove explicit redundant extern declarations in source files that are defined in processor include files.
392 lines
18 KiB
C
392 lines
18 KiB
C
/* vax730_defs.h: VAX 730 model-specific definitions file
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Copyright (c) 2010-2011, Matt Burke
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This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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29-Mar-2011 MB First Version
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This file covers the VAX 11/730, the third VAX.
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System memory map
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00 0000 - EF FFFF main memory
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F0 0000 - F1 FFFF reserved
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F2 0000 - F3 FFFF nexus register space
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F4 0000 - FB FFFF reserved
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FC 0000 - FF FFFF Unibus address space
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*/
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#ifndef FULL_VAX
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#define FULL_VAX 1
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#endif
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#ifndef VAX_730_DEFS_H_
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#define VAX_730_DEFS_H_ 1
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/* Microcode constructs */
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#define VAX730_SID (3 << 24) /* system ID */
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#define VAX730_MICRO (123 << 8) /* ucode revision */
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#define CON_HLTPIN 0x0200 /* external CPU halt */
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#define CON_HLTINS 0x0600 /* HALT instruction */
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#define MCHK_NXM 0x08 /* NXM */
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#define MCHK_IIA 0x0A /* illegal i/o addr */
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#define MCHK_IUA 0x0B /* illegal unibus addr */
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/* Interrupts */
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#define IPL_HMAX 0x17 /* highest hwre level */
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#define IPL_HMIN 0x14 /* lowest hwre level */
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#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
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#define IPL_SMAX 0xF /* highest swre level */
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/* Nexus constants */
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#define NEXUS_NUM 16 /* number of nexus */
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#define TR_MCTL 0 /* nexus assignments */
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#define TR_UBA 3
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#define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1)
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#define SCB_NEXUS 0x100 /* nexus intr base */
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/* Internal I/O interrupts - relative except for clock and console */
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#define IPL_CLKINT 0x18 /* clock IPL */
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#define IPL_TTINT 0x14 /* console IPL */
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#define IPL_CSINT 0x14 /* console storage IPL */
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#define IPL_UBA (0x15 - IPL_HMIN)
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/* Machine specific IPRs */
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#define MT_CSRS 28 /* Console storage */
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#define MT_CSRD 29
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#define MT_CSTS 30
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#define MT_CSTD 31
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#define MT_CDR 37 /* Cache disable */
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#define MT_MCESR 38 /* MCHK err sts */
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#define MT_ACCS 40 /* FPA control */
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#define MT_ACCR 41 /* FPA maint */
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#define MT_SBIFS 48 /* SBI fault status */
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#define MT_SBIS 49 /* SBI silo */
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#define MT_SBISC 50 /* SBI silo comparator */
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#define MT_SBIMT 51 /* SBI maint */
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#define MT_SBIER 52 /* SBI error */
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#define MT_SBITA 53 /* SBI timeout addr */
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#define MT_SBIQC 54 /* SBI timeout clear */
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#define MT_UBINIT 55 /* Unibus Init */
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#define MT_MAX 63 /* last valid IPR */
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/* Machine specific reserved operand tests */
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/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
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#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
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/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
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#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
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((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
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#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
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/* 780 microcode patch 78 - test xCBB<1:0> = 0 */
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#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
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#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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/* Memory */
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#define MAXMEMWIDTH 21 /* max mem, 16k chips */
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#define MAXMEMSIZE (1 << MAXMEMWIDTH)
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#define MAXMEMWIDTH_X 23 /* max mem, 64k chips */
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#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)
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#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
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#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \
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{ UNIT_MSIZE, (2u << 20), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
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{ UNIT_MSIZE, (3u << 20), NULL, "3M", &cpu_set_size, NULL, NULL, "Set Memory to 3M bytes" }, \
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{ UNIT_MSIZE, (4u << 20), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \
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{ UNIT_MSIZE, (5u << 20), NULL, "5M", &cpu_set_size, NULL, NULL, "Set Memory to 5M bytes" }, \
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "MEMORY", NULL, NULL, &cpu_show_memory, NULL, "Display memory configuration" }
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extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc);
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#define CPU_MODEL_MODIFIERS \
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{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
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NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }
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/* Unibus I/O registers */
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#define UBADDRWIDTH 18 /* Unibus addr width */
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#define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */
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#define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */
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#define IOPAGEAWIDTH 13 /* IO addr width */
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#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */
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#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */
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#define UBAMAPWIDTH 11 /* Unibus map width */
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#define UBAMAPSIZE 0x7FC /* Unibus map length */
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#define UBADDRBASE 0xFC0000 /* Unibus addr base */
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#define IOPAGEBASE 0xFFE000 /* IO page base */
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#define UBAMAPBASE 0xF26800 /* Unibus map base */
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#define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \
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(((uint32) (x)) < (UBADDRBASE + UBADDRSIZE)))
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#define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE)
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#define ADDR_IS_IOM(x) ((((uint32) (x)) >= UBAMAPBASE) && \
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(((uint32) (x)) < (UBAMAPBASE + UBAMAPSIZE)))
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/* Nexus register space */
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#define REGAWIDTH 19 /* REG addr width */
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#define REG_V_NEXUS 13 /* nexus number */
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#define REG_M_NEXUS 0xF
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#define REG_V_OFS 2 /* register number */
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#define REG_M_OFS 0x7FF
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#define REGSIZE (1u << REGAWIDTH) /* REG length */
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#define REGBASE 0xF00000 /* REG addr base */
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#define NEXUSBASE REGBASE /* NEXUS addr base */
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#define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \
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(((uint32) (x)) < (REGBASE + REGSIZE)))
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#define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS)
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#define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS)
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/* Other address spaces */
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#define ADDR_IS_ROM(x) (0)
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#define ADDR_IS_CDG(x) (0)
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#define ADDR_IS_NVR(x) (0)
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/* Unibus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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#define WRITE (L_WORD)
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#define WRITEB (L_BYTE)
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/* Common CSI flags */
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#define CSR_V_GO 0 /* go */
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#define CSR_V_IE 6 /* interrupt enable */
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#define CSR_V_DONE 7 /* done */
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#define CSR_V_BUSY 11 /* busy */
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#define CSR_V_ERR 15 /* error */
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#define CSR_GO (1u << CSR_V_GO)
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#define CSR_IE (1u << CSR_V_IE)
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#define CSR_DONE (1u << CSR_V_DONE)
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#define CSR_BUSY (1u << CSR_V_BUSY)
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#define CSR_ERR (1u << CSR_V_ERR)
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/* Timers */
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#define TMR_CLK 0 /* 100Hz clock */
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/* I/O system definitions */
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#define DZ_MUXES 4 /* max # of DZV muxes */
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#define DZ_LINES 8 /* lines per DZV mux */
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#define VH_MUXES 4 /* max # of DHQ muxes */
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#define DLX_LINES 16 /* max # of KL11/DL11's */
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#define DCX_LINES 16 /* max # of DC11's */
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#define DUP_LINES 8 /* max # of DUP11's */
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#define MT_MAXFR (1 << 16) /* magtape max rec */
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#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
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#define DEV_V_NEXUS (DEV_V_UF + 1) /* Nexus */
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#define DEV_V_FFUF (DEV_V_UF + 2) /* first free flag */
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#define DEV_UBUS (1u << DEV_V_UBUS)
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#define DEV_NEXUS (1u << DEV_V_NEXUS)
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#define DEV_QBUS (0)
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#define DEV_Q18 (0)
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#define UNIBUS TRUE /* Unibus only */
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#define DEV_RDX 16 /* default device radix */
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/* Device information block
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For Nexus devices,
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ba = Nexus number
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lnt = number of consecutive nexi */
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#define VEC_DEVMAX 4 /* max device vec */
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typedef struct {
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uint32 ba; /* base addr */
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uint32 lnt; /* length */
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t_stat (*rd)(int32 *dat, int32 ad, int32 md);
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t_stat (*wr)(int32 dat, int32 ad, int32 md);
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int32 vnum; /* vectors: number */
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int32 vloc; /* locator */
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int32 vec; /* value */
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int32 (*ack[VEC_DEVMAX])(void); /* ack routine */
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uint32 ulnt; /* IO length per-device */
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/* Only need to be populated */
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/* when numunits != num devices */
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int32 numc; /* Number of controllers */
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/* this field handles devices */
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/* where multiple instances are */
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/* simulated through a single */
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/* DEVICE structure (e.g., DZ, VH, DL, DC). */
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/* Populated by auto-configure */
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} DIB;
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/* Unibus I/O page layout - see pdp11_io_lib.c for address layout details */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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/* Interrupt assignments; within each level, priority is right to left */
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#define INT_V_DTA 0 /* BR6 */
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#define INT_V_CR 1
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#define INT_V_DZRX 0 /* BR5 */
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#define INT_V_DZTX 1
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#define INT_V_HK 2
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#define INT_V_RL 3
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#define INT_V_RB 4
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#define INT_V_RQ 5
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#define INT_V_TQ 6
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#define INT_V_TS 7
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#define INT_V_RY 8
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#define INT_V_XU 9
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#define INT_V_DMCRX 10
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#define INT_V_DMCTX 11
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#define INT_V_DUPRX 12
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#define INT_V_DUPTX 13
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#define INT_V_RK 14
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#define INT_V_LPT 0 /* BR4 */
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#define INT_V_PTR 1
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#define INT_V_PTP 2
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//#define XXXXXXXX 3 /* Former CR */
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#define INT_V_VHRX 4
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#define INT_V_VHTX 5
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#define INT_V_TDRX 6
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#define INT_V_TDTX 7
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#define INT_DTA (1u << INT_V_DTA)
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#define INT_CR (1u << INT_V_CR)
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_HK (1u << INT_V_HK)
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#define INT_RL (1u << INT_V_RL)
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#define INT_RQ (1u << INT_V_RQ)
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#define INT_TQ (1u << INT_V_TQ)
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#define INT_TS (1u << INT_V_TS)
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#define INT_RY (1u << INT_V_RY)
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#define INT_XU (1u << INT_V_XU)
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#define INT_RB (1u << INT_V_RB)
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#define INT_LPT (1u << INT_V_LPT)
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#define INT_VHRX (1u << INT_V_VHRX)
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#define INT_VHTX (1u << INT_V_VHTX)
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#define INT_PTR (1u << INT_V_PTR)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_DMCRX (1u << INT_V_DMCRX)
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#define INT_DMCTX (1u << INT_V_DMCTX)
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#define INT_DUPRX (1u << INT_V_DUPRX)
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#define INT_DUPTX (1u << INT_V_DUPTX)
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#define INT_RK (1u << INT_V_RK)
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#define INT_TDRX (1u << INT_V_TDRX)
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#define INT_TDTX (1u << INT_V_TDTX)
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#define IPL_DTA (0x16 - IPL_HMIN)
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#define IPL_CR (0x16 - IPL_HMIN)
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#define IPL_DZRX (0x15 - IPL_HMIN)
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#define IPL_DZTX (0x15 - IPL_HMIN)
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#define IPL_HK (0x15 - IPL_HMIN)
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#define IPL_RL (0x15 - IPL_HMIN)
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#define IPL_RQ (0x15 - IPL_HMIN)
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#define IPL_TQ (0x15 - IPL_HMIN)
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#define IPL_TS (0x15 - IPL_HMIN)
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#define IPL_RY (0x15 - IPL_HMIN)
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#define IPL_XU (0x15 - IPL_HMIN)
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#define IPL_RB (0x15 - IPL_HMIN)
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#define IPL_LPT (0x14 - IPL_HMIN)
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#define IPL_PTR (0x14 - IPL_HMIN)
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#define IPL_PTP (0x14 - IPL_HMIN)
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#define IPL_VHRX (0x14 - IPL_HMIN)
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#define IPL_VHTX (0x14 - IPL_HMIN)
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#define IPL_DMCRX (0x15 - IPL_HMIN)
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#define IPL_DMCTX (0x15 - IPL_HMIN)
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#define IPL_DUPRX (0x15 - IPL_HMIN)
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#define IPL_DUPTX (0x15 - IPL_HMIN)
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#define IPL_RK (0x15 - IPL_HMIN)
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#define IPL_TDRX (0x14 - IPL_HMIN)
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#define IPL_TDTX (0x14 - IPL_HMIN)
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/* Device vectors */
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#define VEC_AUTO (0) /* Assigned by Auto Configure */
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#define VEC_FLOAT (0) /* Assigned by Auto Configure */
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#define VEC_QBUS 0 /* Unibus system */
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#define VEC_SET 0x200 /* Vector bits to set in Unibus vectors */
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/* Interrupt macros */
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#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)
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#define NVCL(dv) ((IPL_##dv * 32) + TR_##dv)
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#define IREQ(dv) int_req[IPL_##dv]
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#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
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#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
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/* Logging */
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#define LOG_CPU_I 0x1 /* intexc */
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#define LOG_CPU_R 0x2 /* REI */
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#define LOG_CPU_P 0x4 /* context */
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/* Boot definitions */
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#define BOOT_HK 1 /* device codes */
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#define BOOT_RL 2 /* for VMB */
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#define BOOT_RB 3
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#define BOOT_UDA 17
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#define BOOT_TD 64
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/* Function prototypes for I/O */
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
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int32 Map_WriteB (uint32 ba, int32 bc, const uint8 *buf);
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int32 Map_WriteW (uint32 ba, int32 bc, const uint16 *buf);
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t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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void sbi_set_errcnf (void);
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/* Function prototypes for system-specific unaligned support
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11/730 treats unaligned like aligned */
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#define ReadIOU(p,l) ReadIO (p,l)
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#define ReadRegU(p,l) ReadReg (p,l)
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#define WriteIOU(p,v,l) WriteIO (p, v, l)
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#define WriteRegU(p,v,l) WriteReg (p, v, l)
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#include "pdp11_io_lib.h"
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/* Function prototypes for virtual and physical memory interface (inlined) */
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#include "vax_mmu.h"
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#endif
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