39d2944ede
Asynchronous clocks are now built for all simulators which are built with SIM_ASYNCH_IO defined. The default behavior has asynchronous clocks disabled since this is still experimental, but it can be enabled with SET TIMER ASYNC. Catchup clock ticks are now available, but since they're experimental, they aren't enabled by default. Catchup ticks are only available if the simulators clock device calls sim_rtcn_tick_ack to acknowledge processing of clock ticks. The VAX simulators have been modified to leverage this. Catchup clock ticks can be enabled with SET TIMER CATCHUP Additionally, an idle threshold is provided which can be used to influence when clock calibration may be suppressed. The default is not to suppress calibration activities. The various timer behaviors are visible with the SHOW TIMER command. The state of the operating timer facilities is visible with: SHOW CLOCK Timer events which are queued are visible with the SHOW QUEUE command.
413 lines
14 KiB
C
413 lines
14 KiB
C
/* vax630_stddev.c: MicroVAX II standard I/O devices
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Copyright (c) 2009-2012, Matt Burke
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This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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tti terminal input
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tto terminal output
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clk 100Hz and TODR clock
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08-Nov-2012 MB First version
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*/
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#include "vax_defs.h"
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#include "sim_tmxr.h"
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#include <time.h>
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#define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */
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#define TTICSR_RW (CSR_IE)
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#define TTIBUF_ERR 0x8000 /* error */
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#define TTIBUF_OVR 0x4000 /* overrun */
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#define TTIBUF_FRM 0x2000 /* framing error */
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#define TTIBUF_RBR 0x0400 /* receive break */
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#define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */
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#define TTOCSR_RW (CSR_IE)
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#define CLKCSR_IMP (CSR_IE) /* real-time clock */
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#define CLKCSR_RW (CSR_IE)
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#define CLK_DELAY 5000 /* 100 Hz */
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#define TMXR_MULT 1 /* 100 Hz */
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int32 tti_csr = 0; /* control/status */
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uint32 tti_buftime; /* time input character arrived */
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int32 tto_csr = 0; /* control/status */
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int32 clk_csr = 0; /* control/status */
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int32 clk_tps = 100; /* ticks/second */
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int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */
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int32 tmr_poll = CLK_DELAY; /* pgm timer poll */
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t_stat tti_svc (UNIT *uptr);
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t_stat tto_svc (UNIT *uptr);
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t_stat clk_svc (UNIT *uptr);
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t_stat tti_reset (DEVICE *dptr);
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t_stat tto_reset (DEVICE *dptr);
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t_stat clk_reset (DEVICE *dptr);
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const char *tti_description (DEVICE *dptr);
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const char *tto_description (DEVICE *dptr);
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const char *clk_description (DEVICE *dptr);
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t_stat tti_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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t_stat tto_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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extern int32 sysd_hlt_enb (void);
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/* TTI data structures
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tti_dev TTI device descriptor
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tti_unit TTI unit descriptor
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tti_reg TTI register list
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*/
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DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
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UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
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REG tti_reg[] = {
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{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
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{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
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{ FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") },
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{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") },
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{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
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{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
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{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
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{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
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{ NULL }
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};
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MTAB tti_mod[] = {
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
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{ 0 }
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};
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DEVICE tti_dev = {
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"TTI", &tti_unit, tti_reg, tti_mod,
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1, 10, 31, 1, 16, 8,
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NULL, NULL, &tti_reset,
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NULL, NULL, NULL,
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&tti_dib, 0, 0, NULL, NULL, NULL, &tti_help, NULL, NULL,
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&tti_description
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};
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/* TTO data structures
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tto_dev TTO device descriptor
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tto_unit TTO unit descriptor
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tto_reg TTO register list
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*/
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DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } };
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UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
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REG tto_reg[] = {
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{ HRDATAD (BUF, tto_unit.buf, 8, "last data item processed") },
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{ HRDATAD (CSR, tto_csr, 16, "control/status register") },
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{ FLDATAD (INT, int_req[IPL_TTO], INT_V_TTO, "interrupt pending flag") },
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{ FLDATAD (ERR, tto_csr, CSR_V_ERR, "error flag (CSR<15>)") },
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{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
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{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
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{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
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{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
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{ NULL }
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};
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MTAB tto_mod[] = {
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing)" },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
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{ 0 }
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};
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DEVICE tto_dev = {
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"TTO", &tto_unit, tto_reg, tto_mod,
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1, 10, 31, 1, 16, 8,
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NULL, NULL, &tto_reset,
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NULL, NULL, NULL,
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&tto_dib, 0, 0, NULL, NULL, NULL, &tto_help, NULL, NULL,
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&tto_description
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};
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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*/
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DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } };
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UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };
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REG clk_reg[] = {
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{ HRDATAD (CSR, clk_csr, 16, "control/status register") },
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{ FLDATAD (INT, int_req[IPL_CLK], INT_V_CLK, "interrupt pending flag") },
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{ FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
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{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
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{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
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{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
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#if defined (SIM_ASYNCH_IO)
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{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
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{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
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{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
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#endif
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{ NULL }
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, NULL,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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&clk_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
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&clk_description
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};
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/* Clock and terminal MxPR routines
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iccs_rd/wr interval timer
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todr_rd/wr time of year clock
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rxcs_rd/wr input control/status
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rxdb_rd input buffer
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txcs_rd/wr output control/status
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txdb_wr output buffer
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*/
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int32 iccs_rd (void)
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{
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return (clk_csr & CLKCSR_IMP);
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}
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int32 rxcs_rd (void)
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{
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return (tti_csr & TTICSR_IMP);
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}
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int32 rxdb_rd (void)
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{
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int32 t = tti_unit.buf; /* char + error */
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if (tti_csr & CSR_DONE) { /* Input pending ? */
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tti_csr = tti_csr & ~CSR_DONE; /* clr done */
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tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
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CLR_INT (TTI);
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sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
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}
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return t;
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}
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int32 txcs_rd (void)
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{
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return (tto_csr & TTOCSR_IMP);
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}
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void iccs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (CLK);
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if (data & CSR_DONE) /* Interrupt Acked? */
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sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
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clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
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return;
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}
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void rxcs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (TTI);
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else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
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SET_INT (TTI);
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tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW);
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return;
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}
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void txcs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (TTO);
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else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
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SET_INT (TTO);
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tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);
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return;
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}
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void txdb_wr (int32 data)
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{
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tto_unit.buf = data & 0377;
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tto_csr = tto_csr & ~CSR_DONE;
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CLR_INT (TTO);
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sim_activate (&tto_unit, tto_unit.wait);
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return;
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}
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/* Terminal input routines
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tti_svc process event (character ready)
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tti_reset process reset
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*/
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t_stat tti_svc (UNIT *uptr)
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{
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int32 c;
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sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */
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if ((tti_csr & CSR_DONE) && /* input still pending and < 500ms? */
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((sim_os_msec () - tti_buftime) < 500))
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return SCPE_OK;
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if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
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return c;
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if (c & SCPE_BREAK) { /* break? */
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if (sysd_hlt_enb ()) /* if enabled, halt */
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hlt_pin = 1;
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tti_unit.buf = TTIBUF_ERR | TTIBUF_FRM | TTIBUF_RBR;
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}
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else tti_unit.buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));
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tti_buftime = sim_os_msec ();
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uptr->pos = uptr->pos + 1;
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tti_csr = tti_csr | CSR_DONE;
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if (tti_csr & CSR_IE)
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SET_INT (TTI);
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return SCPE_OK;
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}
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t_stat tti_reset (DEVICE *dptr)
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{
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tmxr_set_console_units (&tti_unit, &tto_unit);
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tti_unit.buf = 0;
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tti_csr = 0;
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CLR_INT (TTI);
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sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
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return SCPE_OK;
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}
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t_stat tti_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf (st, "Console Terminal Input (TTI)\n\n");
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fprintf (st, "The terminal input (TTI) polls the console keyboard for input.\n\n");
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fprintf (st, "When the console terminal is attached to a Telnet session or the simulator is\n");
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fprintf (st, "running from a Windows command prompt, it recognizes BREAK. If BREAK is\n");
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fprintf (st, "entered, and BDR<7> is set (also known as SET CPU NOAUTOBOOT), control returns\n");
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fprintf (st, "to the console firmware; otherwise, BREAK is treated as a normal terminal\n");
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fprintf (st, "input condition.\n\n");
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fprint_set_help (st, dptr);
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fprint_show_help (st, dptr);
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fprint_reg_help (st, dptr);
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return SCPE_OK;
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}
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const char *tti_description (DEVICE *dptr)
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{
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return "console terminal input";
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}
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/* Terminal output routines
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tto_svc process event (character typed)
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tto_reset process reset
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*/
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t_stat tto_svc (UNIT *uptr)
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{
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int32 c;
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t_stat r;
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c = sim_tt_outcvt (tto_unit.buf, TT_GET_MODE (uptr->flags));
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if (c >= 0) {
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if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
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sim_activate (uptr, uptr->wait); /* retry */
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return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
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}
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}
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tto_csr = tto_csr | CSR_DONE;
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if (tto_csr & CSR_IE)
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SET_INT (TTO);
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uptr->pos = uptr->pos + 1;
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return SCPE_OK;
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}
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t_stat tto_reset (DEVICE *dptr)
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{
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tto_unit.buf = 0;
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tto_csr = CSR_DONE;
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CLR_INT (TTO);
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sim_cancel (&tto_unit); /* deactivate unit */
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return SCPE_OK;
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}
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t_stat tto_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf (st, "Console Terminal Output (TTO)\n\n");
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fprintf (st, "The terminal output (TTO) writes to the simulator console.\n\n");
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fprint_set_help (st, dptr);
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fprint_show_help (st, dptr);
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fprint_reg_help (st, dptr);
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return SCPE_OK;
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}
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const char *tto_description (DEVICE *dptr)
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{
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return "console terminal output";
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}
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/* Clock routines
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clk_svc process event (clock tick)
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clk_reset process reset
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todr_powerup powerup for TODR (get date from system)
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*/
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t_stat clk_svc (UNIT *uptr)
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{
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int32 t;
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if (clk_csr & CSR_IE)
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SET_INT (CLK);
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t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
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sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
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tmr_poll = t; /* set tmr poll */
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tmxr_poll = t * TMXR_MULT; /* set mux poll */
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AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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clk_csr = 0;
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CLR_INT (CLK);
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t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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tmr_poll = t; /* set tmr poll */
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tmxr_poll = t * TMXR_MULT; /* set mux poll */
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return SCPE_OK;
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}
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const char *clk_description (DEVICE *dptr)
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{
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return "100hz clock tick";
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}
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