f59d86d7c0
When the conversational boot is waiting for input it uses a BLBC instruction to read the DUART status register and test the RXR bit. This generates an unaligned longword read in Qbus I/O space (Yuk!). I realised that the code to read unaligned data in vax_mmu is broken. It attempts to read the aligned longwords that the data spans, but there was no code to convert the unaligned pa passed in to it's aligned form, thus the wrong bytes are returned and the BLBC never sees the RXR bit.
640 lines
20 KiB
C
640 lines
20 KiB
C
/* vax_mmu.c - VAX memory management
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Copyright (c) 1998-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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09-Nov-13 MB Fixed reading/writing of unaligned data
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24-Oct-12 MB Added support for KA620 virtual addressing
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21-Jul-08 RMS Removed inlining support
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28-May-08 RMS Inlined physical memory routines
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29-Apr-07 RMS Added address masking for system page table reads
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22-Sep-05 RMS Fixed declarations (Sterling Garwood)
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30-Sep-04 RMS Comment and formating changes
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19-Sep-03 RMS Fixed upper/lower case linkage problems on VMS
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01-Jun-03 RMS Fixed compilation problem with USE_ADDR64
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This module contains the instruction simulators for
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Read - read virtual
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Write - write virtual
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ReadL(P) - read aligned physical longword (physical context)
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WriteL(P) - write aligned physical longword (physical context)
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ReadB(W) - read aligned physical byte (word)
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WriteB(W) - write aligned physical byte (word)
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Test - test acccess
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zap_tb - clear TB
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zap_tb_ent - clear TB entry
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chk_tb_ent - check TB entry
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set_map_reg - set up working map registers
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*/
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#include "vax_defs.h"
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#include <setjmp.h>
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typedef struct {
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int32 tag; /* tag */
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int32 pte; /* pte */
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} TLBENT;
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extern uint32 *M;
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extern const uint32 align[4];
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extern int32 PSL;
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extern int32 mapen;
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extern int32 p1, p2;
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extern int32 P0BR, P0LR;
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extern int32 P1BR, P1LR;
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extern int32 SBR, SLR;
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extern int32 SISR;
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extern jmp_buf save_env;
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extern UNIT cpu_unit;
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int32 d_p0br, d_p0lr; /* dynamic copies */
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int32 d_p1br, d_p1lr; /* altered per ucode */
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int32 d_sbr, d_slr;
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extern int32 mchk_va, mchk_ref; /* for mcheck */
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TLBENT stlb[VA_TBSIZE], ptlb[VA_TBSIZE];
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static const int32 insert[4] = {
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0x00000000, 0x000000FF, 0x0000FFFF, 0x00FFFFFF
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};
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static const int32 cvtacc[16] = { 0, 0,
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TLB_ACCW (KERN)+TLB_ACCR (KERN),
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TLB_ACCR (KERN),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+TLB_ACCW (SUPV)+TLB_ACCW (USER)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+TLB_ACCR (KERN)+TLB_ACCR (EXEC),
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TLB_ACCW (KERN)+TLB_ACCR (KERN)+TLB_ACCR (EXEC),
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TLB_ACCR (KERN)+TLB_ACCR (EXEC),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+TLB_ACCW (SUPV)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV),
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TLB_ACCW (KERN)+TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV),
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+TLB_ACCW (SUPV)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER),
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TLB_ACCW (KERN)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER),
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER)
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};
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t_stat tlb_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat tlb_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat tlb_reset (DEVICE *dptr);
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char *tlb_description (DEVICE *dptr);
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TLBENT fill (uint32 va, int32 lnt, int32 acc, int32 *stat);
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extern int32 ReadIO (uint32 pa, int32 lnt);
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extern void WriteIO (uint32 pa, int32 val, int32 lnt);
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extern int32 ReadReg (uint32 pa, int32 lnt);
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extern void WriteReg (uint32 pa, int32 val, int32 lnt);
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/* TLB data structures
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tlb_dev pager device descriptor
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tlb_unit pager units
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pager_reg pager register list
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*/
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UNIT tlb_unit[] = {
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{ UDATA (NULL, UNIT_FIX, VA_TBSIZE * 2) },
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{ UDATA (NULL, UNIT_FIX, VA_TBSIZE * 2) }
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};
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REG tlb_reg[] = {
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{ NULL }
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};
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DEVICE tlb_dev = {
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"TLB", tlb_unit, tlb_reg, NULL,
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2, 16, VA_N_TBI * 2, 1, 16, 32,
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&tlb_ex, &tlb_dep, &tlb_reset,
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NULL, NULL, NULL, NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
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&tlb_description
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};
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/* Read and write virtual
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These routines logically fall into three phases:
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1. Look up the virtual address in the translation buffer, calling
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the fill routine on a tag mismatch or access mismatch (invalid
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tlb entries have access = 0 and thus always mismatch). The
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fill routine handles all errors. If the resulting physical
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address is aligned, do an aligned physical read or write.
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2. Test for unaligned across page boundaries. If cross page, look
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up the physical address of the second page. If not cross page,
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the second physical address is the same as the first.
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3. Using the two physical addresses, do an unaligned read or
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write, with three cases: unaligned long, unaligned word within
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a longword, unaligned word crossing a longword boundary.
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Note that these routines do not handle quad or octa references.
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*/
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/* Read virtual
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Inputs:
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va = virtual address
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lnt = length code (BWL)
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acc = access code (KESU)
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Output:
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returned data, right justified in 32b longword
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*/
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int32 Read (uint32 va, int32 lnt, int32 acc)
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{
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int32 vpn, off, tbi, pa;
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int32 pa1, bo, sc, wl, wh;
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TLBENT xpte;
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mchk_va = va;
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if (mapen) { /* mapping on? */
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vpn = VA_GETVPN (va); /* get vpn, offset */
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off = VA_GETOFF (va);
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tbi = VA_GETTBI (vpn);
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xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
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if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
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((acc & TLB_WACC) && ((xpte.pte & TLB_M) == 0)))
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xpte = fill (va, lnt, acc, NULL); /* fill if needed */
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pa = (xpte.pte & TLB_PFN) | off; /* get phys addr */
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}
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else {
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pa = va & PAMASK;
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off = 0;
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}
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if ((pa & (lnt - 1)) == 0) { /* aligned? */
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if (lnt >= L_LONG) /* long, quad? */
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return ReadL (pa);
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if (lnt == L_WORD) /* word? */
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return ReadW (pa);
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return ReadB (pa); /* byte */
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}
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if (mapen && ((uint32)(off + lnt) > VA_PAGSIZE)) { /* cross page? */
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vpn = VA_GETVPN (va + lnt); /* vpn 2nd page */
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tbi = VA_GETTBI (vpn);
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xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
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if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
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((acc & TLB_WACC) && ((xpte.pte & TLB_M) == 0)))
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xpte = fill (va + lnt, lnt, acc, NULL); /* fill if needed */
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pa1 = (xpte.pte & TLB_PFN) | VA_GETOFF (va + 4);
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}
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else pa1 = (pa + 4) & PAMASK; /* not cross page */
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bo = pa & 3;
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pa = pa & ~3; /* convert to aligned */
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pa1 = pa1 & ~3;
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if (lnt >= L_LONG) { /* lw unaligned? */
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sc = bo << 3;
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wl = ReadL (pa); /* read both lw */
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wh = ReadL (pa1); /* extract */
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return ((((wl >> sc) & align[bo]) | (wh << (32 - sc))) & LMASK);
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}
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else if (bo == 1)
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return ((ReadL (pa) >> 8) & WMASK);
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else {
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wl = ReadL (pa); /* word cross lw */
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wh = ReadL (pa1); /* read, extract */
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return (((wl >> 24) & 0xFF) | ((wh & 0xFF) << 8));
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}
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}
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/* Write virtual
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Inputs:
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va = virtual address
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val = data to be written, right justified in 32b lw
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lnt = length code (BWL)
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acc = access code (KESU)
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Output:
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none
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*/
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void Write (uint32 va, int32 val, int32 lnt, int32 acc)
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{
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int32 vpn, off, tbi, pa;
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int32 pa1, bo, sc, wl, wh;
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TLBENT xpte;
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mchk_va = va;
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if (mapen) {
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vpn = VA_GETVPN (va);
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off = VA_GETOFF (va);
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tbi = VA_GETTBI (vpn);
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xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
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if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
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((xpte.pte & TLB_M) == 0))
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xpte = fill (va, lnt, acc, NULL);
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pa = (xpte.pte & TLB_PFN) | off;
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}
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else {
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pa = va & PAMASK;
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off = 0;
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}
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if ((pa & (lnt - 1)) == 0) { /* aligned? */
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if (lnt >= L_LONG) /* long, quad? */
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WriteL (pa, val);
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else if (lnt == L_WORD) /* word? */
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WriteW (pa, val);
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else WriteB (pa, val); /* byte */
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return;
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}
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if (mapen && ((uint32)(off + lnt) > VA_PAGSIZE)) {
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vpn = VA_GETVPN (va + 4);
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tbi = VA_GETTBI (vpn);
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xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
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if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
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((xpte.pte & TLB_M) == 0))
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xpte = fill (va + lnt, lnt, acc, NULL);
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pa1 = (xpte.pte & TLB_PFN) | VA_GETOFF (va + 4);
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}
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else pa1 = (pa + 4) & PAMASK;
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bo = pa & 3;
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pa = pa & ~3; /* convert to aligned */
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pa1 = pa1 & ~3;
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wl = ReadL (pa);
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if (lnt >= L_LONG) {
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sc = bo << 3;
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wh = ReadL (pa1);
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wl = (wl & insert[bo]) | ((val << sc) & LMASK);
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wh = (wh & ~insert[bo]) | ((val >> (32 - sc)) & insert[bo]);
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WriteL (pa, wl);
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WriteL (pa1, wh);
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}
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else if (bo == 1) {
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wl = (wl & 0xFF0000FF) | (val << 8);
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WriteL (pa, wl);
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}
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else {
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wh = ReadL (pa1);
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wl = (wl & 0x00FFFFFF) | ((val & 0xFF) << 24);
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wh = (wh & 0xFFFFFF00) | ((val >> 8) & 0xFF);
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WriteL (pa, wl);
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WriteL (pa1, wh);
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}
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return;
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}
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/* Test access to a byte (VAX PROBEx) */
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int32 Test (uint32 va, int32 acc, int32 *status)
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{
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int32 vpn, off, tbi;
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TLBENT xpte;
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*status = PR_OK; /* assume ok */
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if (mapen) { /* mapping on? */
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vpn = VA_GETVPN (va); /* get vpn, off */
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off = VA_GETOFF (va);
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tbi = VA_GETTBI (vpn);
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xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
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if ((xpte.pte & acc) && (xpte.tag == vpn)) /* TB hit, acc ok? */
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return (xpte.pte & TLB_PFN) | off;
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xpte = fill (va, L_BYTE, acc, status); /* fill TB */
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if (*status == PR_OK)
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return (xpte.pte & TLB_PFN) | off;
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else return -1;
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}
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return va & PAMASK; /* ret phys addr */
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}
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/* Read aligned physical (in virtual context, unless indicated)
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Inputs:
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pa = physical address, naturally aligned
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Output:
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returned data, right justified in 32b longword
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*/
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SIM_INLINE int32 ReadB (uint32 pa)
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{
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int32 dat;
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if (ADDR_IS_MEM (pa))
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dat = M[pa >> 2];
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else {
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mchk_ref = REF_V;
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if (ADDR_IS_IO (pa))
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dat = ReadIO (pa, L_BYTE);
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else dat = ReadReg (pa, L_BYTE);
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}
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return ((dat >> ((pa & 3) << 3)) & BMASK);
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}
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SIM_INLINE int32 ReadW (uint32 pa)
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{
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int32 dat;
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if (ADDR_IS_MEM (pa))
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dat = M[pa >> 2];
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else {
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mchk_ref = REF_V;
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if (ADDR_IS_IO (pa))
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dat = ReadIO (pa, L_WORD);
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else dat = ReadReg (pa, L_WORD);
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}
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return ((dat >> ((pa & 2)? 16: 0)) & WMASK);
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}
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SIM_INLINE int32 ReadL (uint32 pa)
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{
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if (ADDR_IS_MEM (pa))
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return M[pa >> 2];
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mchk_ref = REF_V;
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if (ADDR_IS_IO (pa)) return ReadIO (pa, L_LONG);
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return ReadReg (pa, L_LONG);
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}
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SIM_INLINE int32 ReadLP (uint32 pa)
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{
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if (ADDR_IS_MEM (pa))
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return M[pa >> 2];
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mchk_va = pa;
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mchk_ref = REF_P;
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if (ADDR_IS_IO (pa))
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return ReadIO (pa, L_LONG);
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return ReadReg (pa, L_LONG);
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}
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/* Write aligned physical (in virtual context, unless indicated)
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Inputs:
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pa = physical address, naturally aligned
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val = data to be written, right justified in 32b longword
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Output:
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none
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*/
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SIM_INLINE void WriteB (uint32 pa, int32 val)
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{
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if (ADDR_IS_MEM (pa)) {
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int32 id = pa >> 2;
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int32 sc = (pa & 3) << 3;
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int32 mask = 0xFF << sc;
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M[id] = (M[id] & ~mask) | (val << sc);
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}
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else {
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mchk_ref = REF_V;
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if (ADDR_IS_IO (pa))
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WriteIO (pa, val, L_BYTE);
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else WriteReg (pa, val, L_BYTE);
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}
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return;
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}
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SIM_INLINE void WriteW (uint32 pa, int32 val)
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{
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if (ADDR_IS_MEM (pa)) {
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int32 id = pa >> 2;
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M[id] = (pa & 2)? (M[id] & 0xFFFF) | (val << 16):
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(M[id] & ~0xFFFF) | val;
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}
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else {
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mchk_ref = REF_V;
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if (ADDR_IS_IO (pa))
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WriteIO (pa, val, L_WORD);
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else WriteReg (pa, val, L_WORD);
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}
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return;
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}
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SIM_INLINE void WriteL (uint32 pa, int32 val)
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{
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if (ADDR_IS_MEM (pa))
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M[pa >> 2] = val;
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else {
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mchk_ref = REF_V;
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if (ADDR_IS_IO (pa))
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WriteIO (pa, val, L_LONG);
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else WriteReg (pa, val, L_LONG);
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}
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return;
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}
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void WriteLP (uint32 pa, int32 val)
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{
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if (ADDR_IS_MEM (pa))
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M[pa >> 2] = val;
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else {
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mchk_va = pa;
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mchk_ref = REF_P;
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if (ADDR_IS_IO (pa))
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WriteIO (pa, val, L_LONG);
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else WriteReg (pa, val, L_LONG);
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}
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return;
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}
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/* TLB fill
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This routine fills the TLB after a tag or access mismatch, or
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on a write if pte<m> = 0. It fills the TLB and returns the
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pte to the caller. On an error, it aborts directly to the
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fault handler in the CPU.
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If called from map (VAX PROBEx), the error status is returned
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to the caller, and no fault occurs.
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*/
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#define MM_ERR(param) { \
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if (stat) { \
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*stat = param; \
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|
return zero_pte; \
|
|
} \
|
|
p1 = MM_PARAM (acc & TLB_WACC, param); \
|
|
p2 = va; \
|
|
ABORT ((param & PR_TNV)? ABORT_TNV: ABORT_ACV); }
|
|
|
|
TLBENT fill (uint32 va, int32 lnt, int32 acc, int32 *stat)
|
|
{
|
|
int32 ptidx = (((uint32) va) >> 7) & ~03;
|
|
int32 tlbpte, ptead, pte, tbi, vpn;
|
|
static TLBENT zero_pte = { 0, 0 };
|
|
|
|
if (va & VA_S0) { /* system space? */
|
|
if (ptidx >= d_slr) /* system */
|
|
MM_ERR (PR_LNV);
|
|
ptead = (d_sbr + ptidx) & PAMASK;
|
|
}
|
|
else {
|
|
if (va & VA_P1) { /* P1? */
|
|
if (ptidx < d_p1lr)
|
|
MM_ERR (PR_LNV);
|
|
ptead = d_p1br + ptidx;
|
|
}
|
|
else { /* P0 */
|
|
if (ptidx >= d_p0lr)
|
|
MM_ERR (PR_LNV);
|
|
ptead = d_p0br + ptidx;
|
|
}
|
|
#if !defined (VAX_620)
|
|
if ((ptead & VA_S0) == 0)
|
|
ABORT (STOP_PPTE); /* ppte must be sys */
|
|
vpn = VA_GETVPN (ptead); /* get vpn, tbi */
|
|
tbi = VA_GETTBI (vpn);
|
|
if (stlb[tbi].tag != vpn) { /* in sys tlb? */
|
|
ptidx = ((uint32) ptead) >> 7; /* xlate like sys */
|
|
if (ptidx >= d_slr)
|
|
MM_ERR (PR_PLNV);
|
|
pte = ReadLP ((d_sbr + ptidx) & PAMASK); /* get system pte */
|
|
#if defined (VAX_780)
|
|
if ((pte & PTE_ACC) == 0) /* spte ACV? */
|
|
MM_ERR (PR_PACV);
|
|
#endif
|
|
if ((pte & PTE_V) == 0) /* spte TNV? */
|
|
MM_ERR (PR_PTNV);
|
|
stlb[tbi].tag = vpn; /* set stlb tag */
|
|
stlb[tbi].pte = cvtacc[PTE_GETACC (pte)] |
|
|
((pte << VA_N_OFF) & TLB_PFN); /* set stlb data */
|
|
}
|
|
ptead = (stlb[tbi].pte & TLB_PFN) | VA_GETOFF (ptead);
|
|
#endif
|
|
}
|
|
pte = ReadL (ptead); /* read pte */
|
|
tlbpte = cvtacc[PTE_GETACC (pte)] | /* cvt access */
|
|
((pte << VA_N_OFF) & TLB_PFN); /* set addr */
|
|
if ((tlbpte & acc) == 0) /* chk access */
|
|
MM_ERR (PR_ACV);
|
|
if ((pte & PTE_V) == 0) /* check valid */
|
|
MM_ERR (PR_TNV);
|
|
if (acc & TLB_WACC) { /* write? */
|
|
if ((pte & PTE_M) == 0)
|
|
WriteL (ptead, pte | PTE_M);
|
|
tlbpte = tlbpte | TLB_M; /* set M */
|
|
}
|
|
vpn = VA_GETVPN (va);
|
|
tbi = VA_GETTBI (vpn);
|
|
if ((va & VA_S0) == 0) { /* process space? */
|
|
ptlb[tbi].tag = vpn; /* store tlb ent */
|
|
ptlb[tbi].pte = tlbpte;
|
|
return ptlb[tbi];
|
|
}
|
|
stlb[tbi].tag = vpn; /* system space */
|
|
stlb[tbi].pte = tlbpte; /* store tlb ent */
|
|
return stlb[tbi];
|
|
}
|
|
|
|
/* Utility routines */
|
|
|
|
extern void set_map_reg (void)
|
|
{
|
|
d_p0br = P0BR & ~03;
|
|
d_p1br = (P1BR - 0x800000) & ~03; /* VA<30> >> 7 */
|
|
d_sbr = (SBR - 0x1000000) & ~03; /* VA<31> >> 7 */
|
|
d_p0lr = (P0LR << 2);
|
|
d_p1lr = (P1LR << 2) + 0x800000; /* VA<30> >> 7 */
|
|
d_slr = (SLR << 2) + 0x1000000; /* VA<31> >> 7 */
|
|
return;
|
|
}
|
|
|
|
/* Zap process (0) or whole (1) tb */
|
|
|
|
void zap_tb (int stb)
|
|
{
|
|
size_t i;
|
|
|
|
for (i = 0; i < VA_TBSIZE; i++) {
|
|
ptlb[i].tag = ptlb[i].pte = -1;
|
|
if (stb)
|
|
stlb[i].tag = stlb[i].pte = -1;
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Zap single tb entry corresponding to va */
|
|
|
|
void zap_tb_ent (uint32 va)
|
|
{
|
|
int32 tbi = VA_GETTBI (VA_GETVPN (va));
|
|
|
|
if (va & VA_S0)
|
|
stlb[tbi].tag = stlb[tbi].pte = -1;
|
|
else ptlb[tbi].tag = ptlb[tbi].pte = -1;
|
|
return;
|
|
}
|
|
|
|
/* Check for tlb entry corresponding to va */
|
|
|
|
t_bool chk_tb_ent (uint32 va)
|
|
{
|
|
int32 vpn = VA_GETVPN (va);
|
|
int32 tbi = VA_GETTBI (vpn);
|
|
TLBENT xpte;
|
|
|
|
xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi];
|
|
if (xpte.tag == vpn)
|
|
return TRUE;
|
|
return FALSE;
|
|
}
|
|
|
|
/* TLB examine */
|
|
|
|
t_stat tlb_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
int32 tlbn = uptr - tlb_unit;
|
|
uint32 idx = (uint32) addr >> 1;
|
|
|
|
if (idx >= VA_TBSIZE)
|
|
return SCPE_NXM;
|
|
if (addr & 1)
|
|
*vptr = ((uint32) (tlbn? stlb[idx].pte: ptlb[idx].pte));
|
|
else *vptr = ((uint32) (tlbn? stlb[idx].tag: ptlb[idx].tag));
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* TLB deposit */
|
|
|
|
t_stat tlb_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
int32 tlbn = uptr - tlb_unit;
|
|
uint32 idx = (uint32) addr >> 1;
|
|
|
|
if (idx >= VA_TBSIZE)
|
|
return SCPE_NXM;
|
|
if (addr & 1) {
|
|
if (tlbn) stlb[idx].pte = (int32) val;
|
|
else ptlb[idx].pte = (int32) val;
|
|
}
|
|
else {
|
|
if (tlbn) stlb[idx].tag = (int32) val;
|
|
else ptlb[idx].tag = (int32) val;
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* TLB reset */
|
|
|
|
t_stat tlb_reset (DEVICE *dptr)
|
|
{
|
|
size_t i;
|
|
|
|
for (i = 0; i < VA_TBSIZE; i++)
|
|
stlb[i].tag = ptlb[i].tag = stlb[i].pte = ptlb[i].pte = -1;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
char *tlb_description (DEVICE *dptr)
|
|
{
|
|
return "translation buffer";
|
|
}
|