5cda68abce
Can now boot the last test programs from floppy, and runs INSTRUCTION-C and PAGING-C without errors.
294 lines
8.1 KiB
C
294 lines
8.1 KiB
C
/*
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* Copyright (c) 2023 Anders Magnusson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "sim_defs.h"
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#include "sim_tmxr.h"
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#include "nd100_defs.h"
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struct intr tti_int = { 0, 1 };
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struct intr tto_int = { 0, 1 };
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MTAB ttx_mod[];
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int tti_status, tti_ctrl;
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int tto_status, tto_ctrl;
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t_stat tti_svc(UNIT *uptr);
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t_stat tto_svc(UNIT *uptr);
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t_stat tti_reset(DEVICE *dptr);
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t_stat tto_reset(DEVICE *dptr);
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t_stat tty_setpar(UNIT *uptr);
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#define TT_ICTRL_EIRDY 0000001 /* enable int on dev ready */
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#define TT_ICTRL_EIERR 0000002 /* enable int on error */
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#define TT_ICTRL_ACT 0000004 /* set device active */
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#define TT_ISTAT_IRDY 0000001 /* device ready gives interrupt */
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#define TT_ISTAT_RDY 0000010 /* device ready for transfer */
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#define TT_OCTRL_EIRDY 0000001 /* enable int on dev ready */
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#define TT_OCTRL_EIERR 0000002 /* enable int on error */
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#define TT_OCTRL_ACT 0000004 /* set device active */
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#define TT_OSTAT_IRDY 0000001 /* device ready gives interrupt */
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#define TT_OSTAT_EINT 0000002 /* error interrupt enabled */
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#define TT_OSTAT_ACT 0000004 /* device active */
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#define TT_OSTAT_RDY 0000010 /* device ready for transfer */
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UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT };
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REG tti_reg[] = {
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{ ORDATA(BUF, tti_unit.buf, 8) },
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{ ORDATA(ISTATUS, tti_status, 16) },
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{ ORDATA(ICTRL, tti_ctrl, 16) },
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{ DRDATA (TIME, tti_unit.wait, 24), },
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{ NULL }
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};
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DEVICE tti_dev = {
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"TTI", &tti_unit, tti_reg, ttx_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tti_reset,
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NULL, NULL, NULL,
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NULL, 0
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};
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UNIT tto_unit = { UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT };
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REG tto_reg[] = {
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{ ORDATA(OSTATUS, tto_status, 16) },
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{ ORDATA(OCTRL, tto_ctrl, 16) },
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{ DRDATA(POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA(TIME, tto_unit.wait, 24), REG_NZ + PV_LEFT },
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{ NULL }
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};
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MTAB ttx_mod[] = {
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#if 0
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{ TT_PAR, TT_PAR_EVEN, "even parity", "EVEN", &tty_setpar },
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{ TT_PAR, TT_PAR_ODD, "odd parity", "ODD", &tty_setpar },
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{ TT_PAR, TT_PAR_MARK, "mark parity", "MARK", &tty_setpar },
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{ TT_PAR, TT_PAR_SPACE, "no parity", "NONE", &tty_setpar },
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#endif
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{ 0 }
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};
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DEVICE tto_dev = {
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"TTO", &tto_unit, tto_reg, ttx_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tto_reset,
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NULL, NULL, NULL,
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NULL, 0
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};
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t_stat
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tti_reset(DEVICE *dptr)
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{
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sim_cancel(&tti_unit);
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return SCPE_OK;
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}
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t_stat
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tto_reset(DEVICE *dptr)
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{
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sim_cancel(&tto_unit);
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tto_status |= TT_OSTAT_RDY;
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return SCPE_OK;
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}
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t_stat
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tti_svc(UNIT *uptr)
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{
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int temp;
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sim_activate (&tti_unit, tti_unit.wait);
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if ((temp = sim_poll_kbd()) < SCPE_KFLAG)
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return temp;
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tti_unit.buf = temp & 0177;
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if (tti_ctrl & TT_ICTRL_ACT) {
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tti_status |= TT_ISTAT_RDY;
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if (tti_ctrl & TT_ICTRL_EIRDY)
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extint(12, &tti_int);
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}
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return SCPE_OK;
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}
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t_stat
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tto_svc(UNIT *uptr)
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{
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int32 c;
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t_stat r;
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c = tto_unit.buf & 0177;
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if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
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sim_activate (uptr, uptr->wait); /* try again */
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return ((r == SCPE_STALL)? SCPE_OK : r);/* !stall? report */
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}
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tto_status &= ~TT_OSTAT_ACT;
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tto_status |= TT_OSTAT_RDY;
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if (tto_ctrl & TT_OCTRL_EIRDY)
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extint(10, &tto_int);
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return SCPE_OK;
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}
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int
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iox_tty(int addr)
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{
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int rv = 0;
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/*
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* First four addresses are input, following four are output.
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*/
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switch (addr & 07) {
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case 0: /* read data */
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regA = tti_unit.buf;
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tti_status &= ~TT_ISTAT_RDY;
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break;
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case 1: /* Ignored */
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break;
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case 2: /* read input status reg */
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regA = tti_status;
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break;
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case 3: /* Write control reg */
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if ((tti_ctrl & TT_ICTRL_ACT) == 0 && (regA & TT_ICTRL_ACT))
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sim_activate (&tti_unit, tti_unit.wait);
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if ((regA & TT_ICTRL_ACT) == 0)
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sim_cancel(&tti_unit);
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tti_ctrl = regA;
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if (tti_ctrl & TT_ICTRL_EIRDY)
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tti_status |= TT_ISTAT_IRDY;
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else
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tti_status &= ~TT_ISTAT_IRDY;
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break;
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case 4: /* Ignored */
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break;
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case 5: /* Write data */
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tto_unit.buf = regA & 0177;
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tto_status &= ~TT_OSTAT_RDY;
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tto_status |= TT_OSTAT_ACT;
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sim_activate (&tto_unit, tto_unit.wait);
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break;
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case 6: /* Read output status */
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regA = tto_status;
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break;
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case 7: /* Write output control reg */
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/* Only interrupts are controlled */
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tto_status = (tto_status & ~03) | (regA & 03);
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break;
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}
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return rv;
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}
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/*
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* Real-time clock.
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*/
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#define CLK_PER_SEC 50
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int int_enabled, dev_ready;
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struct intr rtc_int = { 0, 1 };
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t_stat clk_reset(DEVICE *dptr);
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t_stat clk_svc(UNIT *uptr);
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UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };
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REG clk_reg[] = {
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{ FLDATA (INTENB, int_enabled, 0) },
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{ FLDATA (DEVRDY, dev_ready, 0) },
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{ NULL }
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};
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MTAB clk_mod[] = {
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{ 0 }
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};
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DEVICE clk_dev = {
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"RTC", &clk_unit, clk_reg, clk_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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0, 0
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};
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int
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iox_clk(int addr)
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{
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int rv = 0;
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switch (addr & 3) {
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case 0: /* return 0 in A */
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regA = 0;
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break;
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case 1: /* Reset counter */
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sim_activate_after_abs(&clk_unit, 1000000/CLK_PER_SEC);
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break;
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case 2: /* read status */
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regA = (dev_ready << 3) | int_enabled;
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break;
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case 3: /* set status */
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sim_activate_after_abs(&clk_unit, 1000000/CLK_PER_SEC);
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int_enabled = regA & 1;
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if (BIT13(regA))
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dev_ready = 0;
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break;
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default:
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rv = STOP_UNHIOX;
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}
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return rv;
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}
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t_stat
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clk_reset (DEVICE *dptr)
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{
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sim_rtc_init(1000000/CLK_PER_SEC);
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return SCPE_OK;
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}
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t_stat
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clk_svc(UNIT *uptr)
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{
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sim_rtc_calb(CLK_PER_SEC);
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sim_activate_after(&clk_unit, 1000000/CLK_PER_SEC);
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dev_ready = 1;
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if (int_enabled)
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extint(13, &rtc_int);
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return SCPE_OK;
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}
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