simh-testsetgenerator/HP2100/hp2100_doc.txt

To:	Users
From:	Bob Supnik
Subj:	HP2100 Simulator Usage
Date:	15-Jul-2003

			COPYRIGHT NOTICE

The following copyright notice applies to both the SIMH source and binary:

   Original code published in 1993-2002, written by Robert M Supnik
   Copyright (c) 1993-2003, Robert M Supnik

   Permission is hereby granted, free of charge, to any person obtaining a
   copy of this software and associated documentation files (the "Software"),
   to deal in the Software without restriction, including without limitation
   the rights to use, copy, modify, merge, publish, distribute, sublicense,
   and/or sell copies of the Software, and to permit persons to whom the
   Software is furnished to do so, subject to the following conditions:

   The above copyright notice and this permission notice shall be included in
   all copies or substantial portions of the Software.

   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

   Except as contained in this notice, the name of Robert M Supnik shall not
   be used in advertising or otherwise to promote the sale, use or other dealings
   in this Software without prior written authorization from Robert M Supnik.

This memorandum documents the HP 2100 simulator.


1. Simulator Files

sim/		sim_defs.h
		sim_rev.h
		sim_sock.h
		sim_tape.h
		sim_tmxr.h
		scp.c
		scp_tty.c
		sim_sock.c
		sim_tape.c
		sim_tmxr.c

sim/hp2100/	hp2100_defs.h
		hp2100_cpu.c
		hp2100_fp.c
		hp2100_dp.c
		hp2100_dq.c
		hp2100_dr.c
		hp2100_ipl.c
		hp2100_lps.c
		hp2100_lpt.c
		hp2100_mt.c
		hp2100_ms.c
		hp2100_mux.c
		hp2100_stddev.c
		hp2100_sys.c

2. HP2100 Features

The HP2100 simulator is configured as follows:

device		simulates
name(s)

CPU		2116 CPU with 32KW memory
		2100 CPU with 32KW memory, FP or IOP instructions
		21MX CPU with 1024KW memory, FP or DMS instructions
DMA0, DMA1	dual channel DMA controller
PTR,PTP		12597A paper tape reader/punch
TTY		12631C buffered terminal controller
LPS		12653A printer controller with 2767 printer
		12566B microcircuit interface for diagnostics
LPT		12845A printer controller with 2607 printer
CLK		12539A/B/C time base generator
MUXL,MUXU,MUXC	12920A terminal multiplexor
DP		12557A disk controller with four 2871 drives
		13210A disk controller with four 7900 drives
DQ		12565A disk controller with two 2883 drives
DR		12606B fixed head disk controller with 2770/2771 disks
		12610B drum controller with 2773/2774/2775 drums
MT		12559C magnetic tape controller with one 3030 drive
MS		13181A magnetic tape controller with four 7970B drives
		13183A magnetic tape controller with four 7970E drives
IPLI		12556B interprocessor link, input side
IPLO		12556B interprocessor link, output side

The HP2100 simulator implements several unique stop conditions:

	- decode of an undefined instruction, and STOP_INST is et
	- reference to an undefined I/O device, and STOP_DEV is set
	- more than INDMAX indirect references are detected during
	  memory reference address decoding

The HP2100 loader supports standard absolute binary format.  The DUMP
command is not implemented.

2.1 CPU

CPU options include choice of instruction set and memory size.

	SET CPU 2116		2116 CPU
	SET CPU 2100		2100 CPU
	SET CPU 21MX		21MX CPU
	SET CPU EAU		EAU instructions (2116 only)
	SET CPU NOEAU		no EAU instructions (2116 only)
	SET CPU FP		FP instructions (2100 only)
	SET CPU NOFP		no FP instructions (2100 only)
	SET CPU IOP		IOP instructions (2100, 21MX only)
	SET CPU NOIOP		no IOP instructions (2100, 21MX only)
	SET CPU DMS		DMS instructions (21MX only)
	SET CPU NODMS		no DMS instructions (21MX only)
	SET CPU 4K		set memory size = 4K
	SET CPU 8K		set memory size = 8K
	SET CPU 16K		set memory size = 16K
	SET CPU 32K		set memory size = 32K
	SET CPU 64K		set memory size = 64K (21MX only)
	SET CPU 128K		set memory size = 128K (21MX only)
	SET CPU 256K		set memory size = 256K (21MX only)
	SET CPU 512K		set memory size = 512K (21MX only)
	SET CPU 1024K		set memory size = 1024K (21MX only)

On the 2100, EAU is standard, and the FP and IOP options are mutually
exclusive.  On the 21MX, EAU and FP are standard.  The 2100 and 21MX
include memory protection as standard; the 21MX optionally includes
DMS (dynamic memory system).

If memory size is being reduced, and the memory being truncated contains
non-zero data, the simulator asks for confirmation.  Data in the truncated
portion of memory is lost.  Initial memory size is 32K.

These switches are recognized when examining or depositing in CPU memory:

	-v			if DMS enabled, interpret address as virtual
	-s			if DMS enabled, force system map
	-u			if DMS enabled, force user map
	-p			if DMS enabled, force port A map
	-q			if DMS enabled, force port B map

CPU registers include the visible state of the processor as well as the
control registers for the interrupt system.

	name		models		size	comments

	P		all		15	program counter
	A		all		16	A register
	B		all		16	B register
	X		21MX		16	X index register
	Y		21MX		16	Y index register
	S		all		16	switch/display register
	F		2100,21MX	15	memory protection fence
	E		all		1	extend flag
	O		all		1	overflow flag
	ION		all		1	interrupt enable flag
	ION_DEFER	all		1	interrupt defer flag
	IADDR		all		6	most recent interrupting device
	MPCTL		2100,21MX	1	memory protection enable
	MPFLG		2100,21MX	1	memory protection flag
	MPFBF		2100,21MX	1	memory protection flag buffer
	MPVR		2100,21MX	16	memory protection violation reg
	MPEVR		2100,21MX	1	memory protection freeze flag
	MPMEV		2100,21MX	1	memory protection DMS error flag
	DMSENB		21MX		1	DMS enable
	DMSCUR		21MX		1	DMS current mode
	DMSSR		21MX		16	DMS status register
	DMSVR		21MX		16	DMS violation register
	DMSMAP[4][32]	21MX		20	DMS maps
	STOP_INST	all		1	stop on undefined instruction
	STOP_DEV	all		1	stop on undefined device
	INDMAX		all		16	indirect address limit
	PCQ[0:63]	all		15	P of last JMP, JSB, or interrupt;
						most recent P change first
	WRU		all		8	interrupt character

2.2 DMA Controllers

The HP2100 includes two DMA channel controllers (DMA0 and DMA1).  Each
DMA channel has the following visible state:

	name		size	comments

	CMD		1	channel enabled
	CTL		1	interrupt enabled
	FLG		1	channel ready
	FBF		1	channel ready buffer
	CW1		16	command word 1
	CW2		16	command word 2
	CW3		16	command word 3

2.3 Variable Device Assignments

On the HP2100, I/O device take their device numbers from the backplane
slot they are plugged into.  Thus, device number assignments vary
considerably from system to system, and software package to software
package.  The HP2100 simulator supports dynamic device number assignment.
To show the current device number, use the SHOW <dev> DEVNO command:

	sim> SHOW PTR DEV
	device=10

To change the device number, use the SET <dev> DEVNO=<num> command:

	sim> SET PTR DEV=30
	sim> SHOW PTR DEV
	device=30

The new device number must be in the range 010..077 (octal).  For devices
with two device numbers, only the lower numbered device number can be
changed; the higher is automatically set to the lower + 1.  If a
device number conflict occurs, the simulator will return an error
when started.

In addition, most devices can be enabled or disabled.  To enable a
device, use the SET <dev> ENABLED command:

	sim> SET DP ENABLED

To disable a device, use the SET <dev> DISABLED command:

	sim> SET DP DISABLED

For devices with more than one device number, disabling or enabling any
device in the set disables all the devices.

2.4 Programmed I/O Devices

2.4.1 12597A-002 Paper Tape Reader (PTR)

The paper tape reader (PTR) reads data from a disk file.  The POS
register specifies the number of the next data item to be read.
Thus, by changing POS, the user can backspace or advance the reader.

The paper tape reader supports the BOOT command.  BOOT PTR copies the
absolute binary loader into memory and starts it running.

The paper tape reader implements these registers:

	name		size	comments

	BUF		8	last data item processed
	CMD		1	reader enable
	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	POS		32	position in the input file
	TIME		24	time from I/O initiation to interrupt
	STOP_IOE	1	stop on I/O error

Error handling is as follows:

	error	     STOP_IOE	processed as

	not attached	1	report error and stop
			0	out of tape

	end of file	1	report error and stop
			0	out of tape or paper

	OS I/O error	x	report error and stop

2.4.2 12597A-005 Paper Tape Punch (PTP)

The paper tape punch (PTP) writes data to a disk file.  The POS
register specifies the number of the next data item to be written.
Thus, by changing POS, the user can backspace or advance the punch.

The paper tape punch implements these registers:

	name		size	comments

	BUF		8	last data item processed
	CMD		1	punch enable
	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	POS		32	position in the output file
	TIME		24	time from I/O initiation to interrupt
	STOP_IOE	1	stop on I/O error

Error handling is as follows:

	error	     STOP_IOE	processed as

	not attached	1	report error and stop
			0	out of tape

	OS I/O error	x	report error and stop

2.4.3 12631C Buffered Terminal (TTY)

The console terminal has three units: keyboard (unit 0), printer
(unit 1), and punch (unit 2).  The keyboard reads from the console
keyboard; the printer writes to the simulator console window.  The
punch writes to a disk file.  The keyboard and printer units (TTY0,
TTY1) can be set to one of three modes: UC, 7B, or 8B.  In UC mode,
lower case input and output characters are automatically converted to
upper case.  In 7B mode, input and output characters are masked to 7
bits.  In 8B mode, characters are not modified.  Changing the mode
of either unit changes both.  The default mode is UC.

The console teleprinter implements these registers:

	name		size	comments

	BUF		8	last data item processed
	MODE		16	mode
	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	KPOS		32	number of characters input
	KTIME		24	keyboard polling interval
	TPOS		32	number of characters printed
	TTIME		24	time from I/O initiation to interrupt
	PPOS		32	position in the punch output file
	STOP_IOE	1	punch stop on I/O error

Error handling for the punch is as follows:

	error	     STOP_IOE	processed as

	not attached	1	report error and stop
			0	out of tape

	OS I/O error	x	report error and stop

2.4.4 12653A Printer Controller (LPS) with 2767 Printer
      12566B Microcircuit Interface

The 12653A line printer uses the 12566B microcircuit interface as
its controller.  As a line printer, LPS writes data to a disk file.
The POS register specifies the number of the next data item to be
written.  Thus, by changing POS, the user can backspace or advance
the printer.

As a microcircuit interface, LPS provides the DMA test device for
running the dual channel port controller and DMS diagnostics.  Printer
mode verus diagnostic mode is controlled by the commands:

	SET LPS PRINTER		configure as line printer
	SET LPS DIAG		configure for diagnostic tests

The 12653A is disabled by default.

The 12653A implements these registers:

	name		size	comments

	BUF		16	output buffer
	STA		16	input buffer or status
	CMD		1	printer enable
	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	POS		32	position in the output file
	CTIME		24	time between characters
	PTIME		24	time for a print operation
	STOP_IOE	1	stop on I/O error

In printer mode, error handling is as follows:

	error	     STOP_IOE	processed as

	not attached	1	report error and stop
			0	out of tape or paper

	OS I/O error	x	report error and stop

In diagnostic mode, there are no errors; data sent to the output
buffer is looped back to the status register with a fixed delay of 1.

2.4.5 12845A Printer Controller (LPT)

The line printer (LPT) writes data to a disk file.  The POS register
specifies the number of the next data item to be written.  Thus,
by changing POS, the user can backspace or advance the printer.

The line printer implements these registers:

	name		size	comments

	BUF		8	last data item processed
	CMD		1	printer enable
	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	LCNT		7	line count within page
	POS		32	position in the output file
	CTIME		24	time between characters
	PTIME		24	time for a print operation
	STOP_IOE	1	stop on I/O error

Error handling is as follows:

	error	     STOP_IOE	processed as

	not attached	1	report error and stop
			0	out of tape or paper

	OS I/O error	x	report error and stop

2.4.6 12539A/B/C Time Base Generator (CLK)

The time base generator (CLK) implements these registers:

	name		size	comments

	SEL		3	time base select
	CTR		14	repeat counter for < 1Hz operation
	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	ERR		1	error flag
	TIME[0:7]	31	clock intervals, select = 0..7
	DEVNO		6	current device number (read only)

The time base generator autocalibrates; the clock interval is adjusted
up or down so that the clock tracks actual elapsed time.  Operation at
the fastest rates (100 usec, 1 msec) is not recommended.

2.4.7 12920A Terminal Multiplexor (MUXL, MUXU, MUXC)

The 12920A is a 16-line terminal multiplexor, with five additional
receive-only diagnostic lines.  It consists of three devices:

	MUX		scanning logic (corresponding more or less
			to the upper data card)
	MUXL		individual lines (corresponding more or
			less to the lower data card)
	MUXC		modem control and status logic (corresponding
			to the control card)

The MUX performs input and output through Telnet sessions connected to a
user-specified port.  The ATTACH command to the scanning logic specifies
the port to be used:

	ATTACH MUX <port>	set up listening port

where port is a decimal number between 1 and 65535 that is not being used
for other TCP/IP activities.

Each line (each unit of MUXL) can be set to one of three modes: UC, 7B,
or 8B.  In UC mode, lower case input and output characters are converted
automatically to upper case.  In 7B mode, input and output characters
are masked to 7 bits.  In 8B mode, characters are not modified.  The
default mode is UC.  In addition, each line supports the DATASET option.
DATASET, when set, enables modem control.  The default settings are UC
mode and DATASET disabled.

The modem controls model a simplified Bell 103A dataset with just four
lines: data terminal ready and request to send from the computer to the
data set, and carrier detect and data set ready from the data set to
the computer.  There is no ring detection.  If data terminal ready is
set when a Telnet connection starts up, then carrier detect and data
set ready are also set.  The connection is established whether data
terminal ready is set or not.

Once MUX is attached and the simulator is running, the multiplexor listens
for connections on the specified port.  It assumes that the incoming
connections are Telnet connections.  The connections remain open until
disconnected either by the Telnet client, a SET MUXL DISCONNECT command,
or a DETACH MUX command.

The SHOW MUX CONNECTIONS command displays the current connections to the
extra terminals.  The SHOW MUX STATISTICS command displays statistics for
active connections.  The SET MUX DISCONNECT=linenumber disconnects the
specified line.

The scanner (MUX) implements these registers:

	name		size	comments

	IBUF		16	input buffer, holds line status
	OBUF		16	output buffer, holds channel select

The lines (MUXL) implements these registers:

	name		size	comments

	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	STA[0:20]	16	line status, lines 0-20
	RPAR[0:20]	16	receive parameters, lines 0-20
	XPAR[0:15]	16	transmit parameters, lines 0-15
	RBUF[0:20]	8	receive buffer, lines 0-20
	XBUF[0:15]	8	transmit buffer, lines 0-15
	RCHP[0:20]	1	receive character present, lines 0-20
	XDON[0:15]	1	transmit done, lines 0-15
	TIME[0:15]	24	transmit time, lines 0-15

The modem control (MUXM) implements these registers:

	name		size	comments

	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	SCAN		1	scan enabled
	CHAN		4	current line
	DSO[0:15]	6	C2,C1,ES2,ES1,SS2,SS1, lines 0-15
	DSI[0:15]	2	S2,S1, lines 0-15


The terminal multiplexor does not support save and restore.  All open
connections are lost when the simulator shuts down or MUXU is detached.

2.4.8 Interprocessor Link (IPLI, IPLO)

The interprocessor link is a pair of 12556B parallel interfaces that
are cross coupled to provide interprocessor communications to a second
copy of the HP2100 simulator.  The IPL is intended to support simulation
of a two system HP TimeShared Basic configuration.  The links are actually
bidirectional half-duplex; TimeShared Basic uses them unidirectionally.
The IPL is disabled by default.

To operate, the IPL devices must be enabled and then connected to the IPL
devices in another copy of the simulator.  The IPLI device in the first
simulator is connected to the IPLO device in the second, and vice versa.
Connections are established with the ATTACH command.  One copy of the
simulator listens for connections on a specified port (ATTACH -L); the
other establishes connections to an IP address and port (ATTACH -C).
Either copy may perform either operation, but the operations must be
done in matched pairs:

	simulator #1			simulator #2

	sim> set ipli ena		sim> set ipli ena
	(also enables iplo)		(also enables iplo)
	sim> att -lw ipli 4000
	Listening on port 4000
	Waiting for connection
					sim> att -c iplo 4000
	Connection established		Connected to 127.0.0.1 port 4000
	sim> att -lw iplo 4000
	Listening on port 4001
	Waiting for connection
					sim> att -c ipli 4001
	Connection established		Connected to 127.0.0.1 port 4000

Both forms of ATTACH take a modifier -W (wait); if specified, the command
will wait up to 30 seconds for the connection process to complete.  ATTACH
-C can specify both an IP address and a port, in the form aa.bb.cc.dd:port;
if the IP address is omitted, it defaults to 127.0.0.1 (local system).

Both IPLI and IPLO implement the BOOT command.  BOOT loads the HP Access
Basic Block Loader for the IOP into the top 64 words of memory and starts
it running.

Both IPLI and IPLO implement these registers:

	name		size	comments

	BUF		16	buffer
	HOLD		8	holding buffer
	CMD		1	device enable
	CTL		1	device/interrupt enable
	FLG		1	device ready
	FBF		1	device ready buffer
	TIME		24	polling interval for input
	STOP_IOE	1	stop on I/O error

2.5 12557A Disk Controller (DPC, DPD) with 2781 Drives
    13210A Disk Controller (DPC, DPD) with 7900 Drives

The 12557A/13210A disk controller can be configured as either a
12557A, supporting 2.5MB drives, or a 13210A, supporting 5MB drives,
with the commands:

	SET DP 12557A		2.5MB drives
	SET DP 13210A		5.0MB drives

Drive types cannot be intermixed; the controller is configured for
one type or the other.  The 13210A (for 7900/7901 disks) is selected
by default.

The simulated controller has two separate devices, a data channel and
a device controller.  The data channel includes a 128-word (one sector)
buffer for reads and writes.  The device controller includes the four
disk drives.  Disk drives can be set ONLINE or OFFLINE.

The 12557A/13210A supports the BOOT command.  BOOT DP loads the IBL
for 7900 class disks into memory and starts it running.  BOOT -F DP
boots from the fixed platter (head 2).  The switch register (S) is
set automatically to the value expected by the IBL loader:

	<15:14>	=	01
	<13:12>	=	00
	<11:6>	=	data channel device code
	<5:1> = 	00000
	<0> =		1 if booting from the fixed platter

The data channel implements these registers:

	name		size	comments

	IBUF		16	input buffer
	OBUF		16	output buffer
	DBUF[0:127]	16	sector buffer
	BPTR		7	sector buffer pointer
	CMD		1	channel enable
	CTL		1	interrupt enable
	FLG		1	channel ready
	FBF		1	channel ready buffer
	XFER		1	transfer in progress flag
	WVAL		1	write data valid flag

The device controller implements these registers:

	name		size	comments

	OBUF		16	output buffer
	BUSY		3	busy (unit #, + 1, of active unit)
	CNT		5	check record count
	CMD		1	controller enable
	CTL		1	interrupt enable
	FLG		1	controller ready
	FBF		1	controller ready buffer
	EOC		1	end of cylinder pending
	RARC[0:3]	8	record address register cylinder, drives 0-3
	RARH[0:3]	2	record address register head, drives 0-3
	RARS[0:3]	4	record address register sector, drives 0-3
	STA[0:3]	16	drive status, drives 0-3
	CTIME		24	data transfer command delay time
	DTIME		24	data channel command delay time
	STIME		24	seek delay time, per cylinder
	XTIME		24	interword transfer time

Error handling is as follows:

	error	     	processed as

	not attached	disk not ready

	end of file	assume rest of disk is zero

	OS I/O error	report error and stop

2.6 12565A Disk Controller (DQC, DRC) with 2883 Drives

The 12565A disk controller has two separate devices, a data channel and
a device controller.  The data channel includes a 128-word (one sector)
buffer for reads and writes.  The device controller includes the two
disk drives.  Disk drives can be set ONLINE or OFFLINE.

The 12565A supports the BOOT command.  BOOT DQ loads the IBL for 2883
class disks into memory and starts it running.  The switch register (S)
is set automatically to the value expected by the IBL loader:

	<15:14>	=	01
	<13:12>	=	10
	<11:6>	=	data channel device code
	<5:0> = 	00000

The data channel implements these registers:

	name		size	comments

	IBUF		16	input buffer
	OBUF		16	output buffer
	DBUF[0:127]	16	sector buffer
	BPTR		7	sector buffer pointer
	CMD		1	channel enable
	CTL		1	interrupt enable
	FLG		1	channel ready
	FBF		1	channel ready buffer
	XFER		1	transfer in progress flag
	WVAL		1	write data valid flag

The device controller implements these registers:

	name		size	comments

	OBUF		16	output buffer
	BUSY		2	busy (unit #, + 1, of active unit)
	CNT		9	check record count
	CMD		1	controller enable
	CTL		1	interrupt enable
	FLG		1	controller ready
	FBF		1	controller ready buffer
	RARC[0:1]	8	record address register cylinder, drives 0-1
	RARH[0:1]	5	record address register head, drives 0-1
	RARS[0:1]	5	record address register sector, drives 0-1
	STA[0:1]	16	drive status, drives 0-3
	CTIME		24	data transfer command delay time
	DTIME		24	data channel command delay time
	STIME		24	seek delay time, per cylinder
	XTIME		24	interword transfer time

Error handling is as follows:

	error	     	processed as

	not attached	disk not ready

	end of file	assume rest of disk is zero

	OS I/O error	report error and stop

2.7 12606B Fixed Head Disk Controller (DRC, DRD) with 2770/2771 Disk
    12610B Drum Controller (DRC, DRD) with 2773/2774/2775 Drum

The 12606B/12610B fixed head disk/drum controller has two separate devices,
a data channel and a device controller.  The device controller includes the
actual drive.  Ten different models are supported:

	SET DRC 180K		12606B, 180K words
	SET DRC 360K		12606B, 360K words
	SET DRC 720K		12606B, 720K words
	SET DRC 384K		12610B, 84K words
	SET DRC 512K		12610B, 512K words
	SET DRC 640K		12610B, 640K words
	SET DRC 768K		12610B, 768K words
	SET DRC 896K		12610B, 896K words
	SET DRC 1024K		12610B, 1024K words
	SET DRC 1536K		12610B, 1536K words 

The 12606B/12610B support the BOOT command.  The BOOT command loads the
first sector from the disk or drum into locations 0-77 and then jumps to 77.
This is very different from the IBL loader protocol used by the 12565A and
the 12557A/13210A.

The data channel implements these registers:

	name		size	comments

	IBUF		16	input buffer
	OBUF		16	output buffer
	CMD		1	channel enable
	CTL		1	interrupt enable
	FLG		1	channel ready
	FBF		1	channel ready buffer
	BPTR		6	sector buffer pointer

The device controller implements these registers:

	name		size	comments

	CW		16	command word
	STA		16	status
	CMD		1	controller enable
	CTL		1	interrupt enable
	FLG		1	controller ready
	FBF		1	controller ready buffer
	TIME		24	interword transfer time
	STOP_IOE	1	stop on I/O error

Error handling is as follows:

	error	     	processed as

	not attached	disk not ready

12606B/12610B data files are buffered in memory; therefore, end of file
and OS I/O errors cannot occur.

2.8 12559C Magnetic Tape Controller (MTC, MTD) with 3030 Drive

Magnetic tape options include the ability to make the unit write enabled
or write locked.

	SET MTC LOCKED		set unit write locked
	SET MTC WRITEENABLED	set unit write enabled

The 12559C mag tape drive has two separate devices, a data channel and
a device controller.  The data channel includes a maximum record sized
buffer for reads and writes.  The device controller includes the tape
unit.

The BOOT command is not supported.  The 12559C was HP's earliest tape
drive and is not supported by most of its operating systems.  It is
disabled by default.

The data channel implements these registers:

	name		size	comments

	FLG		1	channel ready
	DBUF[0:65535]	8	transfer buffer
	BPTR		16	buffer pointer (reads and writes)
	BMAX		16	buffer size (writes)

The device controller implements these registers:

	name		size	comments

	FNC		8	current function
	STA		9	tape status
	BUF		8	buffer
	CTL		1	interrupt enabled
	FLG		1	controller ready
	FBF		1	controller ready buffer
	DTF		1	data transfer flop
	FSVC		1	first service flop
	POS		32	magtape position
	CTIME		24	command delay time
	XTIME		24	interword transfer delay time
	STOP_IOE	1	stop on I/O error

Error handling is as follows:

	error			processed as

	not attached		tape not ready; if STOP_IOE, stop

	end of file		parity error

	OS I/O error		parity error; if STOP_IOE, stop

2.9 13181A Magnetic Tape Controller (MSC, MSD) with 7970B Drives
    18183A Magnetic Tape Controller (MSC, MSD) with 7970E Drives

Magnetic tape options include the ability to make the unit write enabled
or write locked, and the ability to select the 13181A (800 bpi) controller
or the 13183A (1600 bpi) controller.

	SET MTn LOCKED		set unit n write locked
	SET MTn WRITEENABLED	set unit n write enabled
	SET MT 13181A		set controller to 13181A
	SET MT 13183A		set controller to 13183A

The 13181A/13183A mag tape drive has two separate devices, a data channel
and a device controller.  The data channel includes a maximum record
sized buffer for reads and writes.  The device controller includes the
tape units.

The 13181A/13183A supports the BOOT command.  BOOT MS loads the IBL for
7970B/E magnetic tape drives into memory and starts it running.  BOOT -S
MS causes the loader to space forward the number of files specified in
the A register before starting to load data.  The switch register (S) is
set automatically to the value expected by the IBL loader:

	<15:14>	=	10
	<13:12>	=	00
	<11:6>	=	data channel device code
	<5:1> = 	00000
	<0> =		1 if space forward before loading

The data channel implements these registers:

	name		size	comments

	BUF		16	data buffer
	CTL		1	interrupt enabled
	FLG		1	channel ready
	FBF		1	channel ready buffer
	DBUF[0:65535]	8	transfer buffer
	BPTR		17	buffer pointer (reads and writes)
	BMAX		17	buffer size (writes)

The device controller implements these registers:

	name		size	comments

	STA		12	tape status
	BUF		16	buffer
	USEL		2	currently selected unit
	FSVC		1	first service flop
	CTL		1	interrupt enabled
	FLG		1	controller ready
	FBF		1	controller ready buffer
	POS[0:3]	32	magtape position
	CTIME		24	command delay time
	XTIME		24	interword transfer delay time
	STOP_IOE	1	stop on I/O error

Error handling is as follows:

	error			processed as

	not attached		tape not ready; if STOP_IOE, stop

	end of file		parity error

	OS I/O error		parity error; if STOP_IOE, stop

2.10 Symbolic Display and Input

The HP2100 simulator implements symbolic display and input.  Display is
controlled by command line switches:

	-a			display as ASCII character
	-c			display as two character string
	-m			display instruction mnemonics

Input parsing is controlled by the first character typed in or by command
line switches:

	' or -a			ASCII character
	" or -c			two character sixbit string
	alphabetic		instruction mnemonic
	numeric			octal number

Instruction input uses standard HP2100 assembler syntax.  There are seven
instruction classes: memory reference, I/O, shift, alter skip, extended
shift, extended memory reference, extended two address reference.

Memory reference instructions have the format

	memref {C/Z} address{,I}

where I signifies indirect, C a current page reference, and Z a zero page
reference.  The address is an octal number in the range 0 - 077777; if C or
Z is specified, the address is a page offset in the range 0 - 01777.  Normally,
C is not needed; the simulator figures out from the address what mode to use.
However, when referencing memory outside the CPU (eg, disks), there is no
valid PC, and C must be used to specify current page addressing.

IOT instructions have the format

	io device{,C}

where C signifies that the device flag is to be cleared.  The device is an
octal number in the range 0 - 77.

Shift and alter/skip instructions have the format

	sub-op sub-op sub-op...

The simulator checks that the combination of sub-opcodes is legal.

Extended shift instructions have the format

	extshift count

where count is an octal number in the range 1 - 020.

Extended memory reference instructions have the format

	extmemref address{,I}

where I signifies indirect addressing.  The address is an octal number in
the range 0 - 077777.

Extended two address instructions have the format

	ext2addr addr1{,I},addr2{,I}

where I signifies indirect addressing.  Both address 1 and address 2 are
octal numbers in the range 0 - 077777.