4ffd3be790
Because some key files have changed, V3.0 should be unzipped to a clean directory. 1. New Features in 3.0-0 1.1 SCP and Libraries - Added ASSIGN/DEASSIGN (logical name) commands. - Changed RESTORE to unconditionally detach files. - Added E11 and TPC format support to magtape library. - Fixed bug in SHOW CONNECTIONS. - Added USE_ADDR64 support 1.2 All magtapes - Magtapes support SIMH format, E11 format, and TPC format (read only). - SET <tape_unit> FORMAT=format sets the specified tape unit's format. - SHOW <tape_unit> FORMAT displays the specified tape unit's format. - Tape format can also be set as part of the ATTACH command, using the -F switch. 1.3 VAX - VAX can be compiled without USE_INT64. - If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support files > 2GB. - VAX ROM has speed control (SET ROM DELAY/NODELAY). 2. Bugs Fixed in 3.01-0 2.1 VAX - Fixed CVTfi bug: integer overflow not set if exponent out of range - Fixed EMODx bugs: o First and second operands reversed o Separated fraction received wrong exponent o Overflow calculation on separated integer incorrect o Fraction not set to zero if exponent out of range - Fixed interval timer and ROM access to pass power-up self-test even on very fast host processors (fixes from Mark Pizzolato). 2.2 1401 - Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS. - Fixed MCE bug, BS off by 1 if zero suppress. - Fixed chaining bug, D lost if return to SCP. - Fixed H branch, branch occurs after continue. - Added check for invalid 8 character MCW, LCA. - Fixed magtape load-mode end of record response. 2.3 Nova - Fixed DSK variable size interaction with restore. 2.4 PDP-1 - Fixed DT variable size interaction with restore. 2.5 PDP-11 - Fixed DT variable size interaction with restore. - Fixed bug in MMR1 update (found by Tim Stark). - Added XQ features and fixed bugs: o Corrected XQ interrupts on IE state transition (code by Tom Evans). o Added XQ interrupt clear on soft reset. o Removed XQ interrupt when setting XL or RL (multiple people). o Added SET/SHOW XQ STATS. o Added SHOW XQ FILTERS. o Added ability to split received packet into multiple buffers. o Added explicit runt and giant packet processing. 2.6 PDP-18B - Fixed DT, RF variable size interaction with restore. - Fixed MT bug in MTTR. 2.7 PDP-8 - Fixed DT, DF, RF, RX variable size interaction with restore. - Fixed MT bug in SKTR. 2.8 HP2100 - Fixed bug in DP (13210A controller only), DQ read status. - Fixed bug in DP, DQ seek complete. 2.9 GRI - Fixed bug in SC queue pointer management. 3. New Features in 3.0 vs prior releases N/A 4. Bugs Fixed in 3.0 vs prior releases N/A 5. General Notes WARNING: The RESTORE command has changed. RESTORE will now detach an attached file on a unit, if that unit did not have an attached file in the saved configuration. This is required to assure that the unit flags and the file state are consistent. WARNING: The compilation scheme for the PDP-10, PDP-11, and VAX has changed. Use one of the supplied build files, or read the documentation carefully, before compiling any of these simulators.
230 lines
9.6 KiB
C
230 lines
9.6 KiB
C
/* pdp11_xq.h: DEQNA/DELQA ethernet controller information
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------------------------------------------------------------------------------
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Copyright (c) 2002-2003, David T. Hittner
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of the author shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author.
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------------------------------------------------------------------------------
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Modification history:
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02-Jun-03 DTH Added struct xq_stats
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28-May-03 DTH Made xq_msg_que.item dynamic
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28-May-03 MP Optimized structures, removed rtime variable
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06-May-03 DTH Changed 32-bit t_addr to uint32 for v3.0
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28-Apr-03 DTH Added callbacks for multicontroller identification
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25-Mar-03 DTH Removed bootrom field - no longer needed; Updated copyright
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15-Jan-03 DTH Merged Mark Pizzolato's changes into main source
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13-Jan-03 MP Added countdown for System Id multicast packets
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10-Jan-03 DTH Added bootrom field
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30-Dec-02 DTH Added setup valid field
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21-Oct-02 DTH Corrected copyright again
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15-Oct-02 DTH Fixed copyright, added sanity timer support
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10-Oct-02 DTH Added more setup fields and bitmasks
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08-Oct-02 DTH Integrated with 2.10-0p4, added variable vector and copyrights
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03-Oct-02 DTH Beta version of xq/sim_ether released for SIMH 2.09-11
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15-Aug-02 DTH Started XQ simulation
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------------------------------------------------------------------------------
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*/
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#ifndef _PDP11_XQ_H
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#define _PDP11_XQ_H
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#if defined (VM_PDP10) /* PDP10 version */
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#error "DEQNA/DELQA not supported on PDP10!"
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#elif defined (VM_VAX) /* VAX version */
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#include "vax_defs.h"
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#define XQ_RDX 16
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#define XQ_WID 32
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extern int32 PSL; /* PSL */
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extern int32 fault_PC; /* fault PC */
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extern int32 int_req[IPL_HLVL];
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extern int32 int_vec[IPL_HLVL][32];
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#else /* PDP-11 version */
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#include "pdp11_defs.h"
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#define XQ_RDX 8
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#define XQ_WID 16
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extern int32 int_req[IPL_HLVL];
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extern int32 int_vec[IPL_HLVL][32];
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#endif
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#include "sim_ether.h"
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/* message queue arrays */
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#define XQ_QUE_MAX 500
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#define XQ_FILTER_MAX 14
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enum xq_type {XQ_T_DEQNA, XQ_T_DELQA};
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struct xq_sanity {
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int enabled; /* sanity timer enabled ? */
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int quarter_secs; /* sanity timer value in 1/4 seconds */
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int countdown; /* sanity timer countdown in 1/4 seconds */
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};
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struct xq_id {
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int enabled; /* System ID timer enabled ? */
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int countdown; /* System ID timer countdown in seconds */
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};
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struct xq_msg_itm {
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int type; /* receive (0=setup, 1=loopback, 2=normal) */
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int32 status; /* message size */
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ETH_PACK packet; /* packet */
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};
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struct xq_msg_que {
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int count;
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int head;
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int tail;
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int loss;
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int high;
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struct xq_msg_itm* item;
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};
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struct xq_setup {
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int valid; /* is the setup block valid? */
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int promiscuous; /* promiscuous mode enabled */
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int multicast; /* enable all multicast addresses */
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int l1; /* first diagnostic led state */
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int l2; /* second diagnostic led state */
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int l3; /* third diagnostic led state */
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int sanity_timer; /* sanity timer value (encoded) */
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ETH_MAC macs[XQ_FILTER_MAX]; /* MAC addresses to respond to */
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};
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struct xq_stats {
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int recv; /* received packets */
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int filter; /* filtered packets */
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int xmit; /* transmitted packets */
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int fail; /* transmit failed */
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int runt; /* runts */
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int giant; /* oversize packets */
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int setup; /* setup packets */
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int loop; /* loopback packets */
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};
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struct xq_meb { /* MEB block */
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uint8 type;
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uint8 add_lo;
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uint8 add_mi;
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uint8 add_hi;
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uint8 siz_lo;
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uint8 siz_hi;
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};
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struct xq_device {
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/*+ initialized values - DO NOT MOVE */
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ETH_PCALLBACK rcallback; /* read callback routine */
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ETH_PCALLBACK wcallback; /* write callback routine */
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ETH_MAC mac; /* MAC address */
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enum xq_type type; /* controller type */
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struct xq_sanity sanity; /* sanity timer information */
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struct xq_id id; /* System ID timer information */
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/*- initialized values - DO NOT MOVE */
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/* I/O register storage */
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uint16 addr[6];
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uint16 rbdl[2];
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uint16 xbdl[2];
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uint16 var;
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uint16 csr;
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/* buffers, etc. */
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struct xq_setup setup;
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struct xq_stats stats;
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uint8 mac_checksum[2];
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uint16 rbdl_buf[6];
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uint16 xbdl_buf[6];
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uint32 rbdl_ba;
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uint32 xbdl_ba;
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ETH_DEV* etherface;
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int receiving;
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ETH_PACK read_buffer;
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ETH_PACK write_buffer;
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struct xq_msg_que ReadQ;
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};
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struct xq_controller {
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DEVICE* dev; /* device block */
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UNIT* unit; /* unit block */
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DIB* dib; /* device interface block */
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struct xq_device* var; /* controller-specific variables */
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};
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typedef struct xq_controller CTLR;
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#define XQ_CSR_RI 0x8000 /* Receive Interrupt Request (RI) [RO/W1] */
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#define XQ_CSR_PE 0x4000 /* Parity Error in Host Memory (PE) [RO] */
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#define XQ_CSR_CA 0x2000 /* Carrier from Receiver Enabled (CA) [RO] */
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#define XQ_CSR_OK 0x1000 /* Ethernet Transceiver Power (OK) [RO] */
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#define XQ_CSR_RR 0x0800 /* Reserved : Set to Zero (RR) [RO] */
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#define XQ_CSR_SE 0x0400 /* Sanity Timer Enable (SE) [RW] */
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#define XQ_CSR_EL 0x0200 /* External Loopback (EL) [RW] */
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#define XQ_CSR_IL 0x0100 /* Internal Loopback (IL) [RW] */
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#define XQ_CSR_XI 0x0080 /* Transmit Interrupt Request (XI) [RO/W1] */
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#define XQ_CSR_IE 0x0040 /* Interrupt Enable (IE) [RW] */
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#define XQ_CSR_RL 0x0020 /* Receive List Invalid/Empty (RL) [RO] */
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#define XQ_CSR_XL 0x0010 /* Transmit List Invalid/Empty (XL) [RO] */
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#define XQ_CSR_BD 0x0008 /* Boot/Diagnostic ROM Load (BD) [RW] */
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#define XQ_CSR_NI 0x0004 /* NonExistant Memory Timeout (NXM) [RO] */
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#define XQ_CSR_SR 0x0002 /* Software Reset (SR) [RW] */
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#define XQ_CSR_RE 0x0001 /* Receiver Enable (RE) [RW] */
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/* special access bitmaps */
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#define XQ_CSR_RO 0xF8B4 /* Read-Only bits */
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#define XQ_CSR_RW 0x074B /* Read/Write bits */
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#define XQ_CSR_W1 0x8080 /* Write-one-to-clear bits */
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#define XQ_VEC_MS 0x8000 /* Mode Select (MO) [RW] */
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#define XQ_VEC_OS 0x4000 /* Option Switch Setting (OS) [RO] */
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#define XQ_VEC_RS 0x2000 /* Request Self-Test (RS) [RW] */
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#define XQ_VEC_S3 0x1000 /* Self-Test Status (S3) [RO] */
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#define XQ_VEC_S2 0x0800 /* Self-Test Status (S2) [RO] */
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#define XQ_VEC_S1 0x0400 /* Self-Test Status (S1) [RO] */
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#define XQ_VEC_ST 0x1C00 /* Self-Test (S1 + S2 + S3) [RO] */
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#define XQ_VEC_IV 0x03FC /* Interrupt Vector (IV) [RW] */
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#define XQ_VEC_RR 0x0002 /* Reserved (RR) [RO] */
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#define XQ_VEC_ID 0x0001 /* Identity Test Bit (ID) [RW] */
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/* special access bitmaps */
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#define XQ_VEC_RO 0x5C02 /* Read-Only bits */
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#define XQ_VEC_RW 0xA3FD /* Read/Write bits */
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#define XQ_DSC_V 0x8000 /* Valid bit */
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#define XQ_DSC_C 0x4000 /* Chain bit */
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#define XQ_DSC_E 0x2000 /* End of Message bit [Transmit only] */
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#define XQ_DSC_S 0x1000 /* Setup bit [Transmit only] */
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#define XQ_DSC_L 0x0080 /* Low Byte Termination bit [Transmit only] */
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#define XQ_DSC_H 0x0040 /* High Byte Start bit [Transmit only] */
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#define XQ_SETUP_MC 0x0001 /* multicast bit */
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#define XQ_SETUP_PM 0x0002 /* promiscuous bit */
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#define XQ_SETUP_LD 0x000C /* led bits */
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#define XQ_SETUP_ST 0x0070 /* sanity timer bits */
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#endif /* _PDP11_XQ_H */
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