5cda68abce
Can now boot the last test programs from floppy, and runs INSTRUCTION-C and PAGING-C without errors.
419 lines
12 KiB
C
419 lines
12 KiB
C
/*
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* Copyright (c) 2023 Anders Magnusson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <setjmp.h>
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#include "sim_defs.h"
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#include "nd100_defs.h"
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/*
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* Nord-100 Memory Management I
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*
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* The paging system on Nord-100 have two modes; normal and extended.
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* In normal mode it is Nord-10-compatible (with a maximum of 512KW memory)
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* and in extended it can handle up to 16MW.
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*
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* It is quite extensive with both individual page protection (RWX) and
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* ring protection, where it has four rings. Ring 0 has lowest prio, ring 3
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* has highest.
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*
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* Page size is 1KW, so 64 pages per address space (page table, PT).
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* A process can use an extra page table as well, called alternate page table.
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* It is intended to allow large processes to use a separate data space.
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* There are four page tables, the PCR tells which table(s) to use.
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*
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* Which protection ring and which page tables a user belongs to is
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* configured in the internal Paging Control Register (PCR). There is
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* one PCR per interrupt level. The PCR looks like this:
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*
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* +-------------------+-------+-----+----------+--+-----+
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* | Unused | PT | APT | Level | 0| Ring|
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* +-------------------+-------+-----+----------+--+-----+
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* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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*
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* PT/APT tells which page table should be used. There are four of them.
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* Level is not stored in the PCR, it is only used to tell which level
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* a PCR belongs to.
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* Ring is the user ring. Must always be >= the page ring.
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*
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* The page tables are located in "shadow memory". Shadow memory is the
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* top pages (>= 177400 in normal mode and >= 177000 in extended) only
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* accessible when running as ring 3.
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* Page table for normal mode looks as below:
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*
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* +---+---+---+---+---+-------+-------------------------+
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* |WPM|RPM|FPM|WIP|PGU| Ring | Physical Page Number |
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* +---+---+---+---+---+-------+-------------------------+
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* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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*
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* WPM/RPM/FPM allows for Write/Read/Fetch.
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* WIP is set by HW and means "Written in page".
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* PGU is set by HW and means "Page used".
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* Ring is the ring the page belongs to. Must be <= User ring.
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*
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* Note that the executing program get its ring level from the page where
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* the instruction were fetched from, so if the User ring is 3 but the
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* page ring is 2 then the progra cannot access the page tables.
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*/
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#define MAXMEMSIZE (512*1024)
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t_stat mm_reset(DEVICE *dptr);
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uint16 PM[MAXMEMSIZE];
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uint16 PCR[16]; /* Paging control register */
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uint16 ptmap[4][64]; /* protection */
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uint16 pmmap[4][64]; /* memory mapping */
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uint16 pea, pes, pgs;
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int pea_locked, pgs_locked; /* flag to lock register after error */
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int userring; /* current user ring */
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extern jmp_buf env;
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#define ISDIS() (mm_dev.flags & DEV_DIS)
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UNIT mm_unit = { UDATA(NULL, UNIT_FIX+UNIT_DISABLE+UNIT_BINK, 0) };
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REG mm_reg[] = {
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{ BRDATA(PCR, PCR, 8, 16, 16) },
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{ ORDATA(PEA, pea, 16) },
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{ ORDATA(PES, pes, 16) },
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{ ORDATA(PGS, pgs, 16) },
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{ NULL }
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};
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DEVICE mm_dev = {
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"MM", &mm_unit, mm_reg, 0,
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1, 8, 16, 1, 8, 16,
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0, 0, &mm_reset,
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NULL, NULL, NULL,
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NULL, DEV_DISABLE
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};
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/*
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* Internal registers located on the MM module.
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*/
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int
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mm_tra(int reg)
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{
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int rv = 0;
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switch (reg) {
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case IRR_PES:
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regA = pes;
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break;
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case IRR_PGS:
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regA = pgs;
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pgs_locked = 0;
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break;
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case IRR_PGC:
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regA = PCR[(regA >> 3) & 017];
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break;
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case IRR_PEA:
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regA = pea;
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pea_locked = 0;
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break;
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default:
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rv = STOP_UNHINS;
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}
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return rv;
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}
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/*
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* Read a byte. 0 in lr is left byte, 1 is right byte.
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*/
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uint8
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rdbyte(int vaddr, int lr, int how)
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{
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uint16 val = rdmem(vaddr, how);
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return lr ? val & 0377 : val >> 8;
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}
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/*
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* Write a byte. 0 in lr is left byte, 1 is right byte.
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*/
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void
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wrbyte(int vaddr, int val, int lr, int how)
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{
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uint16 ov = rdmem(vaddr, how);
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val &= 0377; /* sanity */
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ov = lr ? (ov & 0177400) | val : (ov & 0377) | (val << 8);
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wrmem(vaddr, ov, how);
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}
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/*
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* Access shadow memory. if:
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* sexi == 0 && v >= 0177400 && (myring == 3 || pon == 0)
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* or
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* sexi == 1 && v >= 0177000 && (myring == 3 || pon == 0)
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*/
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static int
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is_shadow(int vaddr)
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{
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if ((PCR[curlvl] & 03) < 3 && ISPON())
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return 0; /* not valid */
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if (vaddr > 0177777)
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return 0;
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if (ISSEX())
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return 1;
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return (vaddr >= 0177400);
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}
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/*
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* Fetch a word from the shadow mem.
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*/
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static int
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shadowrd(int v)
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{
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int pt;
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int x = 0;
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if (ISSEX())
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x = v & 1, v >>= 1;
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pt = (v >> 6) & 03;
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v &= 077;
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if (ISSEX())
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return x ? pmmap[pt][v] : ptmap[pt][v];
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return ptmap[pt][v]|pmmap[pt][v];
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}
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/*
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* Write a word to the shadow mem.
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*/
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static void
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shadowwr(int v, int dat)
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{
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int pt;
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int x = 0;
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if (ISSEX())
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x = v & 1, v >>= 1;
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pt = (v >> 6) & 03;
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v &= 077;
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if (ISSEX()) {
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if (x)
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pmmap[pt][v] = dat;
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else
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ptmap[pt][v] = dat;
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} else {
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pmmap[pt][v] = dat & 0777;
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ptmap[pt][v] = dat & 0177000;
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}
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}
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/*
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* MOR - memory out of range. Addressing non-existent memory.
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*/
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void
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morerr(int addr, int why, int pesval)
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{
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if (pea_locked == 0) {
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pea = (uint16)addr;
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pes = (uint16)(addr >> 16) | pesval;
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pea_locked = 1;
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}
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intrpt14(IIE_MOR, why);
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}
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/*
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* Physical memory read when doing DMA.
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* The only error that can occur is non-existent memory (MOR).
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* returns -1 if MOR, value otherwise.
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*/
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int
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dma_rdmem(int addr)
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{
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addr &= 0xffffff;
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if (addr < MAXMEMSIZE)
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return PM[addr];
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morerr(addr, PM_DMA, PES_DMA);
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return -1;
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}
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int
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dma_wrmem(int addr, int val)
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{
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addr &= 0xffffff;
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if (addr < MAXMEMSIZE) {
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PM[addr] = val;
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return 0;
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}
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morerr(addr, PM_DMA, PES_DMA);
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return -1;
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}
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/*
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* Read direct from physical (24-bit-addr) memory.
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*/
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uint16
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prdmem(int vaddr, int how)
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{
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if ((vaddr & 0xffffff) < MAXMEMSIZE)
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return PM[vaddr];
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morerr(vaddr, PM_CPU, how == M_FETCH ? PES_FETCH : 0);
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return 0;
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}
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static void
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pgsupd(int pgnr, int pnr, int flg)
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{
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if (pgs_locked)
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return;
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pgs = (pgnr << 6) | pnr | flg;
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pgs_locked = 1;
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}
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uint16
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rdmem(int vaddr, int how)
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{
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uint16 *ptmapp;
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int sh, pagetablenr, pagering, pagenr, permit, p;
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vaddr &= 0177777; /* Sanity */
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/* Shadow memory? */
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if ((vaddr >= 0177000) && is_shadow(vaddr))
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return shadowrd(vaddr);
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/* Physical memory? */
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if (ISPON() == 0)
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return prdmem(vaddr, 0);
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/* Paging on. */
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permit = (how == M_FETCH ? PT_FPM : PT_RPM);
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userring = PCR[curlvl] & 03;
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sh = how == M_APT ? 7 : 9;
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pagetablenr = (PCR[curlvl] >> sh) & 03;
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pagenr = vaddr >> 10;
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ptmapp = &ptmap[pagetablenr][pagenr];
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pagering = (*ptmapp >> 9) & 03;
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p = (permit == PT_FPM ? PGS_FF : 0);
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if ((*ptmapp & (PT_WPM|PT_RPM|PT_FPM)) == 0) {
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/* page fault */
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pgsupd(pagetablenr, pagenr, p | PGS_PM);
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intrpt14(IIE_PF, PM_CPU);
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} else if ((*ptmapp & permit) == 0) {
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pgsupd(pagetablenr, pagenr, p | PGS_PM);
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intrpt14(IIE_PV, PM_CPU);
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} else if (pagering > userring) {
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pgsupd(pagetablenr, pagenr, p);
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intrpt14(IIE_PV, PM_CPU);
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} else {
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/* Mark page as read */
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*ptmapp |= PT_PGU;
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vaddr = (pmmap[pagetablenr][pagenr] << 10) | (vaddr & 01777);
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return prdmem(vaddr, 0);
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}
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return 0;
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}
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/*
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* Write direct to physical (24-bit-addr) memory.
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*/
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void
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pwrmem(int vaddr, int val, int how)
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{
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if ((vaddr & 0xffffff) < MAXMEMSIZE)
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PM[vaddr] = val;
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else
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morerr(vaddr, PM_CPU, how == M_FETCH ? PES_FETCH : 0);
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}
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void
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wrmem(int vaddr, int val, int how)
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{
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uint16 *ptmapp;
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int sh, pagetablenr, pagering, permit, pagenr;
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vaddr &= 0177777;
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if ((vaddr >= 0177000) && is_shadow(vaddr)) {
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shadowwr(vaddr, val);
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return;
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}
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if (ISPON() == 0) {
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pwrmem(vaddr, val, PM_CPU);
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return;
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}
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/* Paging on. */
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permit = PT_WPM;
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userring = PCR[curlvl] & 03;
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sh = how == M_APT ? 7 : 9;
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pagetablenr = (PCR[curlvl] >> sh) & 03;
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pagenr = vaddr >> 10;
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ptmapp = &ptmap[pagetablenr][pagenr];
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pagering = (*ptmapp >> 9) & 03;
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if ((*ptmapp & (PT_WPM|PT_RPM|PT_FPM)) == 0) {
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/* page fault */
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pgsupd(pagetablenr, pagenr, PGS_PM);
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intrpt14(IIE_PF, PM_CPU);
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} else if ((*ptmapp & permit) == 0) {
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pgsupd(pagetablenr, pagenr, PGS_PM);
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intrpt14(IIE_PV, PM_CPU);
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} else if (pagering > userring) {
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pgsupd(pagetablenr, pagenr, 0);
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intrpt14(IIE_PV, PM_CPU);
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} else {
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/* Mark page as written */
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*ptmapp |= (PT_PGU|PT_WIP);
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vaddr = (pmmap[pagetablenr][pagenr] << 10) | (vaddr & 01777);
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pwrmem(vaddr, val, PM_CPU);
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}
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}
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void
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mm_wrpcr()
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{
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if (ISDIS())
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return;
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PCR[(regA >> 3) & 017] = regA & 03603;
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}
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t_stat
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mm_reset(DEVICE *dptr)
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{
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return 0;
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}
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/*
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* Check if instruction is privileged enough to execute,
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* otherwise give priv instruction fault.
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*/
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void
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mm_privcheck(void)
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{
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if (ISPON() == 0)
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return;
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if (userring > 1)
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return;
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intrpt14(IIE_PI, PM_CPU);
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}
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