1170 lines
42 KiB
C
1170 lines
42 KiB
C
/*************************************************************************
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* s100_tarbell.c: Tarbell Single Density Disk Controller
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*
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* Created by Patrick Linstruth
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* Based on s100_mdsa.c written by Mike Douglas
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*
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* Module Description:
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* Tarbell 1011 Single Density Disk Controller module for SIMH
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*
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* Environment:
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* User mode only
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*
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*************************************************************************/
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/* #define DBG_MSG */
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#include "altairz80_defs.h"
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#include "sim_imd.h"
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#if defined (_WIN32)
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#include <windows.h>
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#endif
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#ifdef DBG_MSG
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#define DBG_PRINT(args) sim_printf args
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#else
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#define DBG_PRINT(args)
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#endif
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extern uint32 PCX;
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extern t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
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int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
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#define TARBELL_MAX_ADAPTERS 1
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#define TARBELL_MAX_DRIVES 4
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#define TARBELL_SECTOR_LEN 128
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#define TARBELL_SECTORS_PER_TRACK 26
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#define TARBELL_BYTES_PER_TRACK ((TARBELL_SECTORS_PER_TRACK * 186) + 73 + 247)
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#define TARBELL_TRACKS 77
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#define TARBELL_CAPACITY (256256) /* Default Tarbell Disk Capacity */
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#define TARBELL_ROTATION_MS 50
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#define TARBELL_HEAD_TIMEOUT (TARBELL_ROTATION_MS * 2)
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#define TARBELL_PROM_SIZE 32
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#define TARBELL_PROM_MASK (TARBELL_PROM_SIZE-1)
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#define TARBELL_RAM_SIZE 256
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#define TARBELL_RAM_MASK (TARBELL_RAM_SIZE-1)
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#define TARBELL_PROM_READ FALSE
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#define TARBELL_PROM_WRITE TRUE
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/* Tarbell PROM is 32 bytes */
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static uint8 tarbell_prom[TARBELL_PROM_SIZE] = {
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0xdb, 0xfc, 0xaf, 0x6f, 0x67, 0x3c, 0xd3, 0xfa,
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0x3e, 0x8c, 0xd3, 0xf8, 0xdb, 0xfc, 0xb7, 0xf2,
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0x19, 0x00, 0xdb, 0xfb, 0x77, 0x23, 0xc3, 0x0c,
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0x00, 0xdb, 0xf8, 0xb7, 0xca, 0x7d, 0x00, 0x76
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};
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static uint8 tarbell_ram[TARBELL_RAM_SIZE];
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/*
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** Western Digital FD1771 Registers and Interface Controls
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*/
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typedef struct {
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uint8 track; /* Track Register */
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uint8 sector; /* Sector Register */
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uint8 command; /* Command Register */
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uint8 status; /* Status Register */
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uint8 data; /* Data Register */
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uint8 intrq; /* Interrupt Request */
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int8 stepDir; /* Last Step Direction */
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uint32 dataCount; /* Number of data bytes transferred from controller for current sector/address */
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uint32 trkCount; /* Number of data bytes transferred from controller for current track */
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uint8 readActive; /* Read Active */
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uint8 readTrkActive; /* Read Track Active */
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uint8 writeActive; /* Write Active */
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uint8 writeTrkActive; /* Write Track Active */
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uint8 addrActive; /* Address Active */
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uint8 driveNotReady; /* Drive Not Ready */
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uint8 headLoaded; /* Head Loaded */
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uint32 headUnlTime; /* Time to unload head */
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} FD1771_REG;
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#define FD1771_STAT_NOTREADY 0x80
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#define FD1771_STAT_WRITEPROT 0x40
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#define FD1771_STAT_RTYPEMSB 0x40
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#define FD1771_STAT_HEADLOAD 0x20
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#define FD1771_STAT_RTYPELSB 0x20
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#define FD1771_STAT_WRITEFAULT 0x20
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#define FD1771_STAT_SEEKERROR 0x10
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#define FD1771_STAT_NOTFOUND 0x10
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#define FD1771_STAT_CRCERROR 0x08
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#define FD1771_STAT_TRACK0 0x04
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#define FD1771_STAT_LOSTDATA 0x04
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#define FD1771_STAT_INDEX 0x02
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#define FD1771_STAT_DRQ 0x02
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#define FD1771_STAT_BUSY 0x01
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typedef struct {
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} TARBELL_DRIVE_STATUS;
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typedef struct {
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PNP_INFO pnp; /* Plug and Play */
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uint8 promEnabled; /* PROM is enabled */
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uint8 writeProtect; /* Write Protect is enabled */
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uint8 currentDrive; /* currently selected drive */
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FD1771_REG FD1771[TARBELL_MAX_DRIVES]; /* FD1771 Registers and Data */
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UNIT *uptr[TARBELL_MAX_DRIVES];
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} TARBELL_INFO;
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#define TARBELL_PNP_MEMBASE 0x0000
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#define TARBELL_PNP_MEMSIZE TARBELL_RAM_SIZE
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#define TARBELL_PNP_IOBASE 0xF8
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#define TARBELL_PNP_IOSIZE 5
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static TARBELL_INFO tarbell_info_data = { { TARBELL_PNP_MEMBASE, TARBELL_PNP_MEMSIZE, TARBELL_PNP_IOBASE, TARBELL_PNP_IOSIZE } };
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static TARBELL_INFO *tarbell_info = &tarbell_info_data;
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static uint8 sdata[TARBELL_SECTOR_LEN];
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static uint32 stepCleared = TRUE; /* true when step bit has returned to zero */
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/* Tarbell Registers */
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#define TARBELL_REG_STATUS 0x00
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#define TARBELL_REG_COMMAND 0x00
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#define TARBELL_REG_TRACK 0x01
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#define TARBELL_REG_SECTOR 0x02
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#define TARBELL_REG_DATA 0x03
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#define TARBELL_REG_EXT 0x04
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/* Tarbell Commands */
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#define TARBELL_CMD_RESTORE 0x00
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#define TARBELL_CMD_SEEK 0x10
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#define TARBELL_CMD_STEP 0x20
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#define TARBELL_CMD_STEPU (TARBELL_CMD_STEP | TARBELL_FLAG_U)
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#define TARBELL_CMD_STEPIN 0x40
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#define TARBELL_CMD_STEPINU (TARBELL_CMD_STEPIN | TARBELL_FLAG_U)
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#define TARBELL_CMD_STEPOUT 0x60
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#define TARBELL_CMD_STEPOUTU (TARBELL_CMD_STEPOUT | TARBELL_FLAG_U)
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#define TARBELL_CMD_READ 0x80
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#define TARBELL_CMD_READM (TARBELL_CMD_READM | TARBELL_FLAG_M)
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#define TARBELL_CMD_WRITE 0xA0
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#define TARBELL_CMD_WRITEM (TARBELL_CMD_WRITEM | TARBELL_FLAG_M)
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#define TARBELL_CMD_READ_ADDRESS 0xC0
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#define TARBELL_CMD_READ_TRACK 0xE0
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#define TARBELL_CMD_WRITE_TRACK 0xF0
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#define TARBELL_CMD_FORCE_INTR 0xD0
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#define TARBELL_FLAG_V 0x04
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#define TARBELL_FLAG_H 0x08
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#define TARBELL_FLAG_U 0x10
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#define TARBELL_FLAG_M 0x10
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#define TARBELL_FLAG_B 0x08
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#define TARBELL_FLAG_S 0x01
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#define TARBELL_FLAG_E 0x04
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#define TARBELL_FLAG_A1A0_FB 0x00
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#define TARBELL_FLAG_A1A0_FA 0x01
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#define TARBELL_FLAG_A1A0_F9 0x02
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#define TARBELL_FLAG_A1A0_F8 0x03
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#define TARBELL_FLAG_I0 0x01
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#define TARBELL_FLAG_I1 0x02
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#define TARBELL_FLAG_I2 0x04
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#define TARBELL_FLAG_I3 0x08
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#define TARBELL_FLAG_R1R0_6MS 0x00
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#define TARBELL_FLAG_R1R0_10ms 0x02
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#define TARBELL_FLAG_R1R0_20ms 0x03
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#define TARBELL_ADDR_TRACK 0x00
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#define TARBELL_ADDR_ZEROS 0x01
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#define TARBELL_ADDR_SECTOR 0x02
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#define TARBELL_ADDR_LENGTH 0x03
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#define TARBELL_ADDR_CRC1 0x04
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#define TARBELL_ADDR_CRC2 0x05
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/* Local function prototypes */
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static t_stat tarbell_reset(DEVICE *tarbell_dev);
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static t_stat tarbell_svc(UNIT *uptr);
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static t_stat tarbell_attach(UNIT *uptr, CONST char *cptr);
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static t_stat tarbell_detach(UNIT *uptr);
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static t_stat tarbell_boot(int32 unitno, DEVICE *dptr);
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static t_stat tarbell_set_prom(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
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static void TARBELL_HeadLoad(UNIT *uptr, FD1771_REG *pFD1771, uint8 load);
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static uint8 TARBELL_Read(const uint32 Addr);
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static uint8 TARBELL_Write(const uint32 Addr, int32 data);
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static uint8 TARBELL_Command(UNIT *uptr, FD1771_REG *pFD1771, const int32 data);
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static uint32 TARBELL_ReadSector(UNIT *uptr, uint16 track, uint16 sector, uint8 *buffer);
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static uint32 TARBELL_WriteSector(UNIT *uptr, uint16 track, uint16 sector, uint8 *buffer);
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static const char* tarbell_description(DEVICE *dptr);
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static void showdata(int32 isRead);
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static void showregs(FD1771_REG *pFD1771);
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static int32 tarbelldev(const int32 Addr, const int32 rw, const int32 data);
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static int32 tarbellprom(const int32 Addr, const int32 rw, const int32 data);
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static UNIT tarbell_unit[TARBELL_MAX_DRIVES] = {
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{ UDATA (tarbell_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, TARBELL_CAPACITY), 10000 },
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{ UDATA (tarbell_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, TARBELL_CAPACITY), 10000 },
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{ UDATA (tarbell_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, TARBELL_CAPACITY), 10000 },
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{ UDATA (tarbell_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, TARBELL_CAPACITY), 10000 }
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};
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static REG tarbell_reg[] = {
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{ NULL }
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};
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#define TARBELL_NAME "Tarbell 1011 Single Density Controller"
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#define TARBELL_SNAME "TARBELL"
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static const char* tarbell_description(DEVICE *dptr) {
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return TARBELL_NAME;
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}
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#define UNIT_V_TARBELL_VERBOSE (UNIT_V_UF + 0) /* VERBOSE / QUIET */
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#define UNIT_TARBELL_VERBOSE (1 << UNIT_V_TARBELL_VERBOSE)
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#define UNIT_V_TARBELL_WPROTECT (UNIT_V_UF + 1) /* WRTENB / WRTPROT */
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#define UNIT_TARBELL_WPROTECT (1 << UNIT_V_TARBELL_WPROTECT)
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static MTAB tarbell_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE",
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&set_iobase, &show_iobase, NULL, "Sets disk controller IO base address" },
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{ MTAB_XTD | MTAB_VDV, 1, NULL, "PROM", &tarbell_set_prom,
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NULL, NULL, "Enable Tarbell boot PROM"},
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "NOPROM", &tarbell_set_prom,
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NULL, NULL, "Disable Tarbell boot PROM" },
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{ UNIT_TARBELL_VERBOSE, 0, "QUIET", "QUIET",
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NULL, NULL, NULL, "No verbose messages for unit " TARBELL_NAME "n" },
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{ UNIT_TARBELL_VERBOSE, UNIT_TARBELL_VERBOSE, "VERBOSE", "VERBOSE",
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NULL, NULL, NULL, "Verbose messages for unit " TARBELL_NAME "n" },
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{ UNIT_TARBELL_WPROTECT, 0, "WRTENB", "WRTENB", NULL, NULL, NULL,
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"Enables " TARBELL_NAME "n for writing" },
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{ UNIT_TARBELL_WPROTECT, UNIT_TARBELL_WPROTECT, "WRTPROT", "WRTPROT", NULL, NULL, NULL,
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"Protects " TARBELL_NAME "n from writing" },
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{ 0 }
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};
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/* Debug flags */
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#define ERROR_MSG (1 << 0)
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#define SEEK_MSG (1 << 1)
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#define CMD_MSG (1 << 2)
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#define RD_DATA_MSG (1 << 3)
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#define WR_DATA_MSG (1 << 4)
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#define STATUS_MSG (1 << 5)
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#define RD_DATA_DETAIL_MSG (1 << 6)
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#define WR_DATA_DETAIL_MSG (1 << 7)
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/* Debug Flags */
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static DEBTAB tarbell_dt[] = {
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{ "ERROR", ERROR_MSG, "Error messages" },
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{ "SEEK", SEEK_MSG, "Seek messages" },
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{ "CMD", CMD_MSG, "Command messages" },
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{ "READ", RD_DATA_MSG, "Read messages" },
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{ "WRITE", WR_DATA_MSG, "Write messages" },
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{ "STATUS", STATUS_MSG, "Status messages" },
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{ "RDDETAIL", RD_DATA_DETAIL_MSG, "Read detail messages" },
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{ "WRDETAIL", WR_DATA_DETAIL_MSG, "Write detail messags" },
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{ NULL, 0 }
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};
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DEVICE tarbell_dev = {
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"TARBELL", /* name */
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tarbell_unit, /* unit */
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tarbell_reg, /* registers */
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tarbell_mod, /* modifiers */
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TARBELL_MAX_DRIVES, /* # units */
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10, /* address radix */
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31, /* address width */
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1, /* addr increment */
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TARBELL_MAX_DRIVES, /* data radix */
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TARBELL_MAX_DRIVES, /* data width */
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NULL, /* examine routine */
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NULL, /* deposit routine */
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&tarbell_reset, /* reset routine */
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&tarbell_boot, /* boot routine */
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&tarbell_attach, /* attach routine */
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&tarbell_detach, /* detach routine */
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&tarbell_info_data, /* context */
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(DEV_DISABLE | DEV_DIS | DEV_DEBUG), /* flags */
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ERROR_MSG, /* debug control */
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tarbell_dt, /* debug flags */
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NULL, /* mem size routine */
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NULL, /* logical name */
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NULL, /* help */
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NULL, /* attach help */
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NULL, /* context for help */
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&tarbell_description /* description */
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};
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/* Reset routine */
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t_stat tarbell_reset(DEVICE *dptr)
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{
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uint8 i;
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PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
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TARBELL_INFO *pInfo = (TARBELL_INFO *)dptr->ctxt;
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if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
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sim_map_resource(pInfo->pnp.mem_base, pInfo->pnp.mem_size, RESOURCE_TYPE_MEMORY, &tarbellprom, TRUE);
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sim_map_resource(pInfo->pnp.io_base, pInfo->pnp.io_size, RESOURCE_TYPE_IO, &tarbelldev, TRUE);
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} else {
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if(sim_map_resource(pInfo->pnp.mem_base, pInfo->pnp.mem_size, RESOURCE_TYPE_MEMORY, &tarbellprom, FALSE) != 0) {
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sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": Error mapping MEM resource at 0x%04x" NLP, pInfo->pnp.mem_base);
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return SCPE_ARG;
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}
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/* Connect I/O Ports at base address */
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if(sim_map_resource(pInfo->pnp.io_base, pInfo->pnp.io_size, RESOURCE_TYPE_IO, &tarbelldev, FALSE) != 0) {
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sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": Error mapping I/O resource at 0x%02x" NLP, pInfo->pnp.io_base);
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return SCPE_ARG;
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}
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}
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/* Enable PROM */
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pInfo->promEnabled = TRUE;
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pInfo->writeProtect = FALSE;
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/* Reset Registers and Interface Controls */
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for (int i=0; i < TARBELL_MAX_DRIVES; i++) {
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pInfo->FD1771[i].track = 0;
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pInfo->FD1771[i].sector = 1;
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pInfo->FD1771[i].command = 0;
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pInfo->FD1771[i].status = 0;
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pInfo->FD1771[i].data = 0;
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pInfo->FD1771[i].intrq = 0;
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pInfo->FD1771[i].stepDir = 1;
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pInfo->FD1771[i].dataCount = 0;
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pInfo->FD1771[i].trkCount = 0;
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pInfo->FD1771[i].addrActive = FALSE;
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pInfo->FD1771[i].readActive = FALSE;
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pInfo->FD1771[i].readTrkActive = FALSE;
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pInfo->FD1771[i].writeActive = FALSE;
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pInfo->FD1771[i].writeTrkActive = FALSE;
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pInfo->FD1771[i].addrActive = FALSE;
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pInfo->FD1771[i].headLoaded = FALSE;
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pInfo->FD1771[i].driveNotReady = TRUE;
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}
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return SCPE_OK;
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}
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static t_stat tarbell_svc(UNIT *uptr)
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{
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FD1771_REG *pFD1771;
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uint32 now;
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pFD1771 = &tarbell_info->FD1771[tarbell_info->currentDrive];
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/*
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** Get current msec time
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*/
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now = sim_os_msec();
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if (now < pFD1771->headUnlTime) {
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sim_activate(uptr, 100000); /* restart timer */
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}
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else if (pFD1771->headLoaded == TRUE) {
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TARBELL_HeadLoad(uptr, pFD1771, FALSE);
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}
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return SCPE_OK;
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}
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/* Attach routine */
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t_stat tarbell_attach(UNIT *uptr, CONST char *cptr)
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{
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char header[4];
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t_stat r;
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unsigned int i = 0;
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r = attach_unit(uptr, cptr); /* attach unit */
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if(r != SCPE_OK) { /* error? */
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sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": ATTACH error=%d" NLP, r);
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return r;
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}
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/* Determine length of this disk */
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if(sim_fsize(uptr->fileref) != 0) {
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uptr->capac = sim_fsize(uptr->fileref);
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} else {
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uptr->capac = TARBELL_CAPACITY;
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}
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DBG_PRINT(("TARBELL: ATTACH uptr->capac=%d" NLP, uptr->capac));
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for (i = 0; i < TARBELL_MAX_DRIVES; i++) {
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tarbell_info->uptr[i] = &tarbell_dev.units[i];
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}
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for (i = 0; i < TARBELL_MAX_DRIVES; i++) {
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if(tarbell_dev.units[i].fileref == uptr->fileref) {
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break;
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}
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}
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/* Default for new file is DSK */
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uptr->u3 = IMAGE_TYPE_DSK;
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if(uptr->capac > 0) {
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char *rtn = fgets(header, 4, uptr->fileref);
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if((rtn != NULL) && (strncmp(header, "CPT", 3) == 0)) {
|
|
sim_printf("CPT images not yet supported" NLP);
|
|
uptr->u3 = IMAGE_TYPE_CPT;
|
|
tarbell_detach(uptr);
|
|
return SCPE_OPENERR;
|
|
} else {
|
|
uptr->u3 = IMAGE_TYPE_DSK;
|
|
}
|
|
}
|
|
|
|
if (uptr->flags & UNIT_TARBELL_VERBOSE) {
|
|
sim_printf(TARBELL_SNAME "%d, attached to '%s', type=%s, len=%d" NLP, i, cptr,
|
|
uptr->u3 == IMAGE_TYPE_CPT ? "CPT" : "DSK",
|
|
uptr->capac);
|
|
}
|
|
|
|
/*
|
|
** Clear Not Ready Flag
|
|
*/
|
|
tarbell_info->FD1771[i].driveNotReady = FALSE;
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
|
|
/* Detach routine */
|
|
t_stat tarbell_detach(UNIT *uptr)
|
|
{
|
|
t_stat r;
|
|
int8 i;
|
|
|
|
for (i = 0; i < TARBELL_MAX_DRIVES; i++) {
|
|
if(tarbell_dev.units[i].fileref == uptr->fileref) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (i >= TARBELL_MAX_DRIVES) {
|
|
return SCPE_ARG;
|
|
}
|
|
|
|
DBG_PRINT(("Detach TARBELL%d\n", i));
|
|
|
|
r = detach_unit(uptr); /* detach unit */
|
|
|
|
if (r != SCPE_OK) {
|
|
return r;
|
|
}
|
|
|
|
tarbell_dev.units[i].fileref = NULL;
|
|
|
|
if (uptr->flags & UNIT_TARBELL_VERBOSE) {
|
|
sim_printf(TARBELL_SNAME "%d detached." NLP, i);
|
|
}
|
|
|
|
/*
|
|
** Set Not Ready Flag
|
|
*/
|
|
tarbell_info->FD1771[i].driveNotReady = TRUE;
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat tarbell_set_prom(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
|
|
{
|
|
tarbell_info->promEnabled = (uint8) value;
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat tarbell_boot(int32 unitno, DEVICE *dptr)
|
|
{
|
|
|
|
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
|
|
|
|
sim_debug(STATUS_MSG, &tarbell_dev, TARBELL_SNAME ": Booting Controller at 0x%04x" NLP, pnp->mem_base);
|
|
|
|
*((int32 *) sim_PC->loc) = pnp->mem_base;
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static int32 tarbelldev(const int32 Addr, const int32 rw, const int32 data)
|
|
{
|
|
if (rw == 0) { /* Read */
|
|
return(TARBELL_Read(Addr));
|
|
} else { /* Write */
|
|
return(TARBELL_Write(Addr, data));
|
|
}
|
|
}
|
|
|
|
static void showdata(int32 isRead) {
|
|
int32 i;
|
|
sim_debug(RD_DATA_DETAIL_MSG|WR_DATA_DETAIL_MSG, &tarbell_dev, TARBELL_SNAME ": %s sector:" NLP "\t", isRead ? "Read" : "Write");
|
|
for (i=0; i < TARBELL_SECTOR_LEN; i++) {
|
|
sim_debug(RD_DATA_DETAIL_MSG|WR_DATA_DETAIL_MSG, &tarbell_dev, "%02X ", sdata[i]);
|
|
if (((i+1) & 0xf) == 0) {
|
|
sim_debug(RD_DATA_DETAIL_MSG|WR_DATA_DETAIL_MSG, &tarbell_dev, NLP "\t");
|
|
}
|
|
}
|
|
sim_debug(RD_DATA_DETAIL_MSG|WR_DATA_DETAIL_MSG, &tarbell_dev, NLP);
|
|
}
|
|
|
|
static void showregs(FD1771_REG *pFD1771)
|
|
{
|
|
DBG_PRINT(("TARBELL: DRV=%d PE=%d AA=%d RA=%d WA=%d DC=%03d CMD=%02Xh DATA=%02Xh TRK=%03d SEC=%03d STAT=%02X" NLP,
|
|
tarbell_info->currentDrive, tarbell_info->promEnabled, pFD1771->addrActive, pFD1771->readActive, pFD1771->writeActive, pFD1771->dataCount,
|
|
pFD1771->command, pFD1771->data, pFD1771->track, pFD1771->sector, pFD1771->status));
|
|
}
|
|
|
|
|
|
static uint32 calculate_tarbell_sec_offset(uint8 track, uint8 sector)
|
|
{
|
|
uint32 offset;
|
|
|
|
offset = ((track * (TARBELL_SECTOR_LEN * TARBELL_SECTORS_PER_TRACK)) + ((sector-1) * TARBELL_SECTOR_LEN));
|
|
|
|
DBG_PRINT(("TARBELL: CALC track=%d sector=%d offset=%04X" NLP, track, sector, offset));
|
|
|
|
return (offset);
|
|
}
|
|
|
|
static void TARBELL_HeadLoad(UNIT *uptr, FD1771_REG *pFD1771, uint8 load)
|
|
{
|
|
sim_cancel(uptr); /* cancel timer */
|
|
|
|
if (load) {
|
|
pFD1771->headUnlTime = sim_os_msec() + TARBELL_HEAD_TIMEOUT;
|
|
sim_activate(uptr, 100000); /* activate timer */
|
|
}
|
|
|
|
if (load == TRUE && pFD1771->headLoaded == FALSE) {
|
|
sim_debug(STATUS_MSG, &tarbell_dev, TARBELL_SNAME ": Drive %d head Loaded." NLP, tarbell_info->currentDrive);
|
|
}
|
|
|
|
if (load == FALSE && pFD1771->headLoaded == TRUE) {
|
|
sim_debug(STATUS_MSG, &tarbell_dev, TARBELL_SNAME ": Drive %d head Unloaded." NLP, tarbell_info->currentDrive);
|
|
}
|
|
|
|
pFD1771->headLoaded = load;
|
|
}
|
|
|
|
static uint8 TARBELL_Read(const uint32 Addr)
|
|
{
|
|
uint8 cData;
|
|
uint8 driveNum;
|
|
FD1771_REG *pFD1771;
|
|
UNIT *uptr;
|
|
int32 rtn;
|
|
|
|
cData = 0;
|
|
uptr = tarbell_info->uptr[tarbell_info->currentDrive];
|
|
pFD1771 = &tarbell_info->FD1771[tarbell_info->currentDrive];
|
|
|
|
switch(Addr & 0x07) {
|
|
case TARBELL_REG_STATUS:
|
|
cData = pFD1771->status;
|
|
break;
|
|
|
|
case TARBELL_REG_TRACK:
|
|
cData = pFD1771->track;
|
|
break;
|
|
|
|
case TARBELL_REG_DATA:
|
|
/*
|
|
** If a READ operation is currently active, get the next byte
|
|
*/
|
|
if (pFD1771->readActive) {
|
|
/* Store byte in DATA register */
|
|
pFD1771->data = sdata[pFD1771->dataCount++];
|
|
|
|
/* If we reached the end of the sector, terminate command and set INTRQ */
|
|
if (pFD1771->dataCount == TARBELL_SECTOR_LEN) {
|
|
pFD1771->readActive = FALSE;
|
|
pFD1771->dataCount = 0;
|
|
pFD1771->status = 0x00;
|
|
pFD1771->intrq = TRUE;
|
|
|
|
showregs(pFD1771);
|
|
}
|
|
else {
|
|
pFD1771->status |= FD1771_STAT_DRQ; /* Another byte is ready */
|
|
}
|
|
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
else if (pFD1771->addrActive) {
|
|
/* Store byte in DATA register */
|
|
pFD1771->data = sdata[pFD1771->dataCount++];
|
|
|
|
DBG_PRINT(("TARBELL: READ ADDR data=%03d" NLP, pFD1771->data));
|
|
|
|
/* If we reached the end of the address data, terminate command and set INTRQ */
|
|
if (pFD1771->dataCount > TARBELL_ADDR_CRC2) {
|
|
pFD1771->addrActive = FALSE;
|
|
pFD1771->status = 0x00;
|
|
pFD1771->intrq = TRUE;
|
|
|
|
showregs(pFD1771);
|
|
}
|
|
else {
|
|
pFD1771->status |= FD1771_STAT_DRQ; /* Another byte is ready */
|
|
}
|
|
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
|
|
cData = pFD1771->data;
|
|
break;
|
|
|
|
case TARBELL_REG_SECTOR:
|
|
cData = pFD1771->sector;
|
|
break;
|
|
|
|
case TARBELL_REG_EXT:
|
|
cData = (pFD1771->intrq) ? 0x00 : 0x80; /* Bit 7 True if DRQ */
|
|
break;
|
|
|
|
default:
|
|
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": READ Invalid I/O Address %02x (%02x)" NLP, Addr & 0xFF, Addr & 0x07);
|
|
cData = 0xff;
|
|
break;
|
|
}
|
|
|
|
return (cData);
|
|
}
|
|
|
|
static uint8 TARBELL_Write(const uint32 Addr, const int32 Data)
|
|
{
|
|
uint8 cData;
|
|
uint8 driveNum;
|
|
int32 rtn;
|
|
UNIT *uptr;
|
|
FD1771_REG *pFD1771;
|
|
|
|
DBG_PRINT(("TARBELL: WRITE Address %02x Data %02x" NLP, Addr & 0xFF, Data & 0xFF));
|
|
|
|
cData = 0;
|
|
uptr = tarbell_info->uptr[tarbell_info->currentDrive];
|
|
pFD1771 = &tarbell_info->FD1771[tarbell_info->currentDrive];
|
|
|
|
switch(Addr & 0x07) {
|
|
case TARBELL_REG_COMMAND:
|
|
cData = TARBELL_Command(uptr, pFD1771, Data);
|
|
break;
|
|
|
|
case TARBELL_REG_DATA:
|
|
pFD1771->data = Data; /* Store byte in DATA register */
|
|
|
|
if (pFD1771->writeActive) {
|
|
|
|
/* Store DATA register in Sector Buffer */
|
|
sdata[pFD1771->dataCount++] = pFD1771->data;
|
|
|
|
/* If we reached the end of the sector, write sector, terminate command and set INTRQ */
|
|
if (pFD1771->dataCount == TARBELL_SECTOR_LEN) {
|
|
pFD1771->status = 0x00; /* Clear Status Bits */
|
|
|
|
rtn = TARBELL_WriteSector(uptr, pFD1771->track, pFD1771->sector, sdata);
|
|
|
|
if (rtn != TARBELL_SECTOR_LEN) {
|
|
pFD1771->status |= FD1771_STAT_WRITEFAULT;
|
|
}
|
|
pFD1771->writeActive = FALSE;
|
|
pFD1771->dataCount = 0;
|
|
pFD1771->intrq = TRUE;
|
|
|
|
showregs(pFD1771);
|
|
}
|
|
else {
|
|
pFD1771->status |= FD1771_STAT_DRQ; /* Ready for another byte */
|
|
}
|
|
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
else if (pFD1771->writeTrkActive) {
|
|
|
|
/*
|
|
** Increment number for bytes written to track
|
|
*/
|
|
pFD1771->trkCount++;
|
|
|
|
if (pFD1771->data == 0xE5) {
|
|
|
|
/* Store DATA register in Sector Buffer */
|
|
sdata[pFD1771->dataCount++] = pFD1771->data;
|
|
|
|
/* If we reached the end of the sector, write sector, terminate command and set INTRQ */
|
|
if (pFD1771->dataCount == TARBELL_SECTOR_LEN) {
|
|
pFD1771->status &= ~FD1771_STAT_WRITEFAULT; /* Clear Status Bit */
|
|
|
|
rtn = TARBELL_WriteSector(uptr, pFD1771->track, pFD1771->sector, sdata);
|
|
|
|
if (rtn != TARBELL_SECTOR_LEN) {
|
|
pFD1771->status |= FD1771_STAT_WRITEFAULT;
|
|
}
|
|
|
|
pFD1771->sector++;
|
|
pFD1771->dataCount = 0;
|
|
pFD1771->status &= ~FD1771_STAT_BUSY; /* Clear BUSY Bit */
|
|
|
|
DBG_PRINT(("TARBELL: WRITE TRACK track=%03d sector=%03d trkcount=%d datacount=%d data=%02X status=%02X" NLP, pFD1771->track, pFD1771->sector, pFD1771->trkCount, pFD1771->dataCount, pFD1771->data, pFD1771->status));
|
|
|
|
showregs(pFD1771);
|
|
}
|
|
}
|
|
|
|
if (pFD1771->trkCount < TARBELL_BYTES_PER_TRACK) {
|
|
pFD1771->status |= FD1771_STAT_DRQ; /* Ready for another byte */
|
|
}
|
|
else {
|
|
pFD1771->status = 0x00; /* Clear Status Bits */
|
|
pFD1771->intrq = TRUE; /* Simulate reaching index hole */
|
|
sim_debug(WR_DATA_MSG, &tarbell_dev, TARBELL_SNAME ": WRITE TRACK track=%03d sector=%03d trkcount=%d datacount=%d data=%02X status=%02X" NLP, pFD1771->track, pFD1771->sector, pFD1771->trkCount, pFD1771->dataCount, pFD1771->data, pFD1771->status);
|
|
}
|
|
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
|
|
DBG_PRINT(("TARBELL: WRITE DATA REG %02X" NLP, Data));
|
|
break;
|
|
|
|
case TARBELL_REG_TRACK:
|
|
pFD1771->track = Data;
|
|
DBG_PRINT(("TARBELL: TRACK REG=%d" NLP, pFD1771->track));
|
|
break;
|
|
|
|
case TARBELL_REG_SECTOR:
|
|
if (Data > TARBELL_SECTORS_PER_TRACK) {
|
|
pFD1771->sector = 1;
|
|
}
|
|
|
|
pFD1771->sector = Data;
|
|
|
|
DBG_PRINT(("TARBELL: SECTOR REG=%d" NLP, pFD1771->sector));
|
|
|
|
break;
|
|
|
|
case TARBELL_REG_EXT:
|
|
cData = ~(Data >> 4) & 0x03;
|
|
if (cData < TARBELL_MAX_DRIVES) {
|
|
tarbell_info->currentDrive = cData;
|
|
sim_debug(STATUS_MSG, &tarbell_dev, TARBELL_SNAME ": Current drive now %d" NLP, tarbell_info->currentDrive);
|
|
}
|
|
else {
|
|
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": Invalid Drive Number drive=%02x (%02x)" NLP, Data, cData);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": WRITE Invalid I/O Address %02x (%02x)" NLP, Addr & 0xFF, Addr & 0x07);
|
|
cData = 0xff;
|
|
break;
|
|
}
|
|
|
|
DBG_PRINT(("TARBELL: COMPLETE currentDrive=%d sector=%02x data=%02x" NLP, tarbell_info->currentDrive, pFD1771->sector, pFD1771->data));
|
|
|
|
return(cData);
|
|
}
|
|
|
|
static uint32 TARBELL_ReadSector(UNIT *uptr, uint16 track, uint16 sector, uint8 *buffer)
|
|
{
|
|
uint32 sec_offset;
|
|
uint32 rtn = 0;
|
|
|
|
if (uptr->fileref == NULL) {
|
|
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": READSEC uptr.fileref is NULL!" NLP);
|
|
return 0;
|
|
}
|
|
|
|
sec_offset = calculate_tarbell_sec_offset(track, sector);
|
|
|
|
sim_debug(RD_DATA_MSG, &tarbell_dev, TARBELL_SNAME ": READSEC track %03d sector %03d at offset %04X" NLP, track, sector, sec_offset);
|
|
|
|
if (sim_fseek(uptr->fileref, sec_offset, SEEK_SET) != 0) {
|
|
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": READSEC sim_fseek error." NLP);
|
|
return 0;
|
|
}
|
|
|
|
rtn = sim_fread(buffer, 1, TARBELL_SECTOR_LEN, uptr->fileref);
|
|
|
|
return rtn;
|
|
}
|
|
|
|
|
|
static uint32 TARBELL_WriteSector(UNIT *uptr, uint16 track, uint16 sector, uint8 *buffer)
|
|
{
|
|
uint32 sec_offset;
|
|
uint32 rtn = 0;
|
|
|
|
if (uptr->fileref == NULL) {
|
|
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": READSEC uptr.fileref is NULL!" NLP);
|
|
return 0;
|
|
}
|
|
|
|
sec_offset = calculate_tarbell_sec_offset(track, sector);
|
|
|
|
sim_debug(WR_DATA_MSG, &tarbell_dev, TARBELL_SNAME ": WRITESEC track %03d sector %03d at offset %04X" NLP, track, sector, sec_offset);
|
|
|
|
if (sim_fseek(uptr->fileref, sec_offset, SEEK_SET) != 0) {
|
|
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": WRITESEC sim_fseek error." NLP);
|
|
return 0;
|
|
}
|
|
|
|
rtn = sim_fwrite(buffer, 1, TARBELL_SECTOR_LEN, uptr->fileref);
|
|
|
|
return rtn;
|
|
}
|
|
|
|
|
|
static uint8 TARBELL_Command(UNIT *uptr, FD1771_REG *pFD1771, const int32 Data)
|
|
{
|
|
uint8 cData;
|
|
uint8 newTrack;
|
|
uint8 statusUpdate;
|
|
int32 rtn;
|
|
|
|
cData = 0;
|
|
rtn=0;
|
|
statusUpdate = TRUE;
|
|
|
|
pFD1771->command = (Data & 0xF0);
|
|
|
|
pFD1771->status |= FD1771_STAT_BUSY;
|
|
pFD1771->intrq = FALSE;
|
|
|
|
/*
|
|
** Type II-IV Command
|
|
*/
|
|
if (pFD1771->command & 0x80) {
|
|
pFD1771->readActive = FALSE;
|
|
pFD1771->writeActive = FALSE;
|
|
pFD1771->readTrkActive = FALSE;
|
|
pFD1771->writeTrkActive = FALSE;
|
|
pFD1771->addrActive = FALSE;
|
|
pFD1771->dataCount = 0;
|
|
|
|
pFD1771->status &= ~FD1771_STAT_DRQ; /* Reset DRQ */
|
|
}
|
|
|
|
/*
|
|
** Set BUSY for all but Force Interrupt
|
|
*/
|
|
if ((pFD1771->command & TARBELL_CMD_FORCE_INTR) == TARBELL_CMD_FORCE_INTR) {
|
|
pFD1771->status |= FD1771_STAT_BUSY;
|
|
}
|
|
|
|
switch(pFD1771->command) {
|
|
case TARBELL_CMD_RESTORE:
|
|
pFD1771->track = 0;
|
|
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": RESTORE track=%03d" NLP, pFD1771->track);
|
|
|
|
if (Data & TARBELL_FLAG_H) {
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
|
|
pFD1771->status &= ~FD1771_STAT_SEEKERROR;
|
|
pFD1771->status &= ~FD1771_STAT_BUSY;
|
|
pFD1771->status &= ~FD1771_STAT_DRQ;
|
|
pFD1771->intrq = TRUE;
|
|
break;
|
|
|
|
case TARBELL_CMD_SEEK:
|
|
newTrack = pFD1771->data;
|
|
|
|
DBG_PRINT(("TARBELL: TRACK DATA=%d (SEEK)" NLP, newTrack));
|
|
|
|
pFD1771->status &= ~FD1771_STAT_SEEKERROR;
|
|
|
|
if (newTrack < TARBELL_TRACKS) {
|
|
pFD1771->track = newTrack;
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": SEEK track=%03d" NLP, pFD1771->track);
|
|
}
|
|
else {
|
|
pFD1771->status |= FD1771_STAT_SEEKERROR;
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": SEEK ERR track=%03d" NLP, newTrack);
|
|
}
|
|
|
|
if (Data & TARBELL_FLAG_H) {
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
|
|
pFD1771->status &= ~FD1771_STAT_BUSY;
|
|
pFD1771->status &= ~FD1771_STAT_DRQ;
|
|
pFD1771->intrq = TRUE;
|
|
break;
|
|
|
|
case TARBELL_CMD_STEP:
|
|
case TARBELL_CMD_STEPU:
|
|
pFD1771->status &= ~FD1771_STAT_SEEKERROR;
|
|
|
|
newTrack = pFD1771->track + pFD1771->stepDir;
|
|
|
|
if (newTrack < TARBELL_TRACKS-1) {
|
|
if (Data & TARBELL_FLAG_U) {
|
|
pFD1771->track = newTrack;
|
|
}
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": STEP track=%03d" NLP, pFD1771->track);
|
|
}
|
|
else {
|
|
pFD1771->status |= FD1771_STAT_SEEKERROR;
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": STEP ERR track=%03d" NLP, newTrack);
|
|
}
|
|
|
|
if (Data & TARBELL_FLAG_H) {
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
|
|
pFD1771->status &= ~FD1771_STAT_BUSY;
|
|
pFD1771->status &= ~FD1771_STAT_DRQ;
|
|
pFD1771->intrq = TRUE;
|
|
break;
|
|
|
|
case TARBELL_CMD_STEPIN:
|
|
case TARBELL_CMD_STEPINU:
|
|
pFD1771->status &= ~FD1771_STAT_SEEKERROR;
|
|
|
|
if (pFD1771->track < TARBELL_TRACKS) {
|
|
if (Data & TARBELL_FLAG_U) {
|
|
pFD1771->track++;
|
|
}
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": STEPIN track=%03d" NLP, pFD1771->track);
|
|
}
|
|
else {
|
|
pFD1771->status |= FD1771_STAT_SEEKERROR;
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": STEPIN ERR track=%03d" NLP, pFD1771->track+1);
|
|
}
|
|
|
|
if (Data & TARBELL_FLAG_H) {
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
|
|
pFD1771->stepDir = 1;
|
|
pFD1771->status &= ~FD1771_STAT_BUSY;
|
|
pFD1771->status &= ~FD1771_STAT_DRQ;
|
|
pFD1771->intrq = TRUE;
|
|
break;
|
|
|
|
case TARBELL_CMD_STEPOUT:
|
|
case TARBELL_CMD_STEPOUTU:
|
|
pFD1771->status &= ~FD1771_STAT_SEEKERROR;
|
|
|
|
if (pFD1771->track > 0) {
|
|
if (Data & TARBELL_FLAG_U) {
|
|
pFD1771->track--;
|
|
}
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": STEPOUT track=%03d" NLP, pFD1771->track);
|
|
}
|
|
else {
|
|
pFD1771->status |= FD1771_STAT_SEEKERROR;
|
|
sim_debug(SEEK_MSG, &tarbell_dev, TARBELL_SNAME ": STEPOUT ERR track=%03d" NLP, pFD1771->track-1);
|
|
}
|
|
|
|
if (Data & TARBELL_FLAG_H) {
|
|
TARBELL_HeadLoad(uptr, pFD1771, TRUE);
|
|
}
|
|
|
|
pFD1771->stepDir = -1;
|
|
pFD1771->status &= ~FD1771_STAT_BUSY;
|
|
pFD1771->status &= ~FD1771_STAT_DRQ;
|
|
pFD1771->intrq = TRUE;
|
|
break;
|
|
|
|
case TARBELL_CMD_READ:
|
|
|
|
if ((uptr == NULL) || (uptr->fileref == NULL)) {
|
|
DBG_PRINT(("TARBELL: " ADDRESS_FORMAT
|
|
" Drive: %d not attached - read ignored." NLP,
|
|
PCX, tarbell_info->currentDrive));
|
|
|
|
pFD1771->status &= ~FD1771_STAT_BUSY;
|
|
|
|
return cData;
|
|
}
|
|
|
|
rtn = TARBELL_ReadSector(uptr, pFD1771->track, pFD1771->sector, sdata);
|
|
|
|
if (rtn == TARBELL_SECTOR_LEN) {
|
|
pFD1771->readActive = TRUE;
|
|
|
|
showdata(TRUE);
|
|
}
|
|
else {
|
|
DBG_PRINT(("TARBELL: " ADDRESS_FORMAT " READ: sim_fread error." NLP, PCX));
|
|
|
|
pFD1771->status |= FD1771_STAT_NOTFOUND;
|
|
pFD1771->intrq = TRUE;
|
|
}
|
|
|
|
break;
|
|
|
|
case TARBELL_CMD_WRITE:
|
|
if ((uptr->flags & UNIT_TARBELL_WPROTECT) || tarbell_info->writeProtect) {
|
|
DBG_PRINT((TARBELL_SNAME ": Disk write protected. uptr->flags=%04x writeProtect=%04x" NLP, uptr->flags & UNIT_TARBELL_WPROTECT, tarbell_info->writeProtect));
|
|
pFD1771->intrq = TRUE;
|
|
}
|
|
else {
|
|
pFD1771->writeActive = TRUE;
|
|
pFD1771->dataCount = 0;
|
|
pFD1771->status |= FD1771_STAT_DRQ; /* Set DRQ */
|
|
}
|
|
|
|
break;
|
|
|
|
case TARBELL_CMD_READ_ADDRESS:
|
|
sdata[TARBELL_ADDR_TRACK]=pFD1771->track;
|
|
sdata[TARBELL_ADDR_ZEROS]=0;
|
|
sdata[TARBELL_ADDR_SECTOR]=pFD1771->sector;
|
|
sdata[TARBELL_ADDR_LENGTH]=TARBELL_SECTOR_LEN;
|
|
sdata[TARBELL_ADDR_CRC1]=0;
|
|
sdata[TARBELL_ADDR_CRC2]=0;
|
|
|
|
pFD1771->addrActive = TRUE;
|
|
pFD1771->status |= FD1771_STAT_DRQ; /* Set DRQ */
|
|
|
|
break;
|
|
|
|
case TARBELL_CMD_READ_TRACK:
|
|
pFD1771->readTrkActive = TRUE;
|
|
pFD1771->trkCount=0;
|
|
pFD1771->dataCount=0;
|
|
pFD1771->sector=1;
|
|
pFD1771->status |= FD1771_STAT_DRQ; /* Set DRQ */
|
|
break;
|
|
|
|
case TARBELL_CMD_WRITE_TRACK:
|
|
if ((uptr->flags & UNIT_TARBELL_WPROTECT) || tarbell_info->writeProtect) {
|
|
DBG_PRINT((TARBELL_SNAME ": Disk write protected. uptr->flags=%04x writeProtect=%04x" NLP, uptr->flags & UNIT_TARBELL_WPROTECT, tarbell_info->writeProtect));
|
|
pFD1771->intrq = TRUE;
|
|
}
|
|
else {
|
|
pFD1771->writeTrkActive = TRUE;
|
|
pFD1771->trkCount=0;
|
|
pFD1771->dataCount=0;
|
|
pFD1771->sector=1;
|
|
pFD1771->status |= FD1771_STAT_DRQ; /* Set DRQ */
|
|
}
|
|
break;
|
|
|
|
case TARBELL_CMD_FORCE_INTR:
|
|
if (pFD1771->status & FD1771_STAT_BUSY) {
|
|
pFD1771->status &= ~FD1771_STAT_BUSY;
|
|
statusUpdate = FALSE;
|
|
}
|
|
|
|
/* Reset Status */
|
|
pFD1771->dataCount = 0;
|
|
pFD1771->readActive = FALSE;
|
|
pFD1771->readTrkActive = FALSE;
|
|
pFD1771->writeActive = FALSE;
|
|
pFD1771->writeTrkActive = FALSE;
|
|
pFD1771->addrActive = FALSE;
|
|
|
|
break;
|
|
|
|
default:
|
|
cData=0xFF;
|
|
sim_debug(ERROR_MSG, &tarbell_dev, "TARBELL: UNRECOGNIZED CMD %02X" NLP, pFD1771->command);
|
|
break;
|
|
}
|
|
|
|
/**************************/
|
|
/* Update Status Register */
|
|
/**************************/
|
|
|
|
pFD1771->status |= (pFD1771->driveNotReady) ? FD1771_STAT_NOTREADY : 0x00;
|
|
|
|
switch(pFD1771->command) {
|
|
case TARBELL_CMD_RESTORE:
|
|
case TARBELL_CMD_SEEK:
|
|
case TARBELL_CMD_STEP:
|
|
case TARBELL_CMD_STEPU:
|
|
case TARBELL_CMD_STEPIN:
|
|
case TARBELL_CMD_STEPINU:
|
|
case TARBELL_CMD_STEPOUT:
|
|
case TARBELL_CMD_STEPOUTU:
|
|
case TARBELL_CMD_FORCE_INTR:
|
|
if (statusUpdate) {
|
|
pFD1771->status &= ~FD1771_STAT_WRITEPROT;
|
|
pFD1771->status &= ~FD1771_STAT_CRCERROR;
|
|
pFD1771->status &= ~FD1771_STAT_TRACK0;
|
|
pFD1771->status |= ((uptr->flags & UNIT_TARBELL_WPROTECT) || tarbell_info->writeProtect) ? FD1771_STAT_WRITEPROT : 0x00;
|
|
pFD1771->status |= (pFD1771->track) ? 0x00 : FD1771_STAT_TRACK0;
|
|
pFD1771->status |= (pFD1771->headLoaded) ? FD1771_STAT_HEADLOAD : 0x00;
|
|
pFD1771->status |= FD1771_STAT_INDEX; /* Always set Index Flag if Drive Ready */
|
|
}
|
|
break;
|
|
|
|
case TARBELL_CMD_READ:
|
|
pFD1771->status &= ~FD1771_STAT_LOSTDATA;
|
|
pFD1771->status &= ~FD1771_STAT_NOTFOUND;
|
|
pFD1771->status &= ~FD1771_STAT_CRCERROR;
|
|
break;
|
|
|
|
case TARBELL_CMD_WRITE:
|
|
pFD1771->status &= ~FD1771_STAT_WRITEPROT;
|
|
pFD1771->status &= ~FD1771_STAT_LOSTDATA;
|
|
pFD1771->status &= ~FD1771_STAT_NOTFOUND;
|
|
pFD1771->status &= ~FD1771_STAT_CRCERROR;
|
|
pFD1771->status |= ((uptr->flags & UNIT_TARBELL_WPROTECT) || tarbell_info->writeProtect) ? FD1771_STAT_WRITEPROT : 0x00;
|
|
break;
|
|
|
|
case TARBELL_CMD_READ_ADDRESS:
|
|
pFD1771->status &= ~0x20;
|
|
pFD1771->status &= ~0x40;
|
|
pFD1771->status &= ~FD1771_STAT_LOSTDATA;
|
|
pFD1771->status &= ~FD1771_STAT_NOTFOUND;
|
|
pFD1771->status &= ~FD1771_STAT_CRCERROR;
|
|
break;
|
|
|
|
case TARBELL_CMD_READ_TRACK:
|
|
pFD1771->status &= ~0x08;
|
|
pFD1771->status &= ~0x10;
|
|
pFD1771->status &= ~0x20;
|
|
pFD1771->status &= ~0x40;
|
|
pFD1771->status &= ~FD1771_STAT_LOSTDATA;
|
|
break;
|
|
|
|
case TARBELL_CMD_WRITE_TRACK:
|
|
pFD1771->status &= ~0x08;
|
|
pFD1771->status &= ~0x10;
|
|
pFD1771->status &= ~FD1771_STAT_WRITEPROT;
|
|
pFD1771->status &= ~FD1771_STAT_LOSTDATA;
|
|
pFD1771->status &= ~FD1771_STAT_WRITEFAULT;
|
|
pFD1771->status |= ((uptr->flags & UNIT_TARBELL_WPROTECT) || tarbell_info->writeProtect) ? FD1771_STAT_WRITEPROT : 0x00;
|
|
break;
|
|
}
|
|
|
|
sim_debug(CMD_MSG, &tarbell_dev, TARBELL_SNAME ": CMD drive=%d cmd=%02X track=%03d sector=%03d status=%02X" NLP,
|
|
tarbell_info->currentDrive, pFD1771->command, pFD1771->track, pFD1771->sector, pFD1771->status);
|
|
|
|
return(cData);
|
|
}
|
|
|
|
static int32 tarbellprom(const int32 Addr, const int32 rw, const int32 Data)
|
|
{
|
|
/*
|
|
** The Tarbell controller overlays the first 32 bytes of RAM with a PROM.
|
|
** The PROM is enabled/disabled with switch position 7:
|
|
** ON = ENABLED
|
|
** OFF = DISABLED
|
|
**
|
|
** If the PROM is enabled, writes to 0x0000-0x001F are written to RAM, reads are
|
|
** from the PROM.
|
|
**
|
|
** The PROM is disabled if the controller detects a memory read with bit A5 enabled,
|
|
** which can't be implemented because Examine reads 6 bytes at a time. We will disable
|
|
** the PROM if address >= 0x0025 is read. Hack.
|
|
*/
|
|
|
|
if (rw == TARBELL_PROM_WRITE) {
|
|
tarbell_ram[Addr & TARBELL_RAM_MASK] = Data;
|
|
return 0;
|
|
} else {
|
|
if (Addr >= 0x0025 && tarbell_info->promEnabled == TRUE) {
|
|
tarbell_info->promEnabled = FALSE;
|
|
sim_debug(STATUS_MSG, &tarbell_dev, TARBELL_SNAME ": Boot PROM disabled." NLP);
|
|
}
|
|
|
|
if (tarbell_info->promEnabled == TRUE && Addr < TARBELL_PROM_SIZE) {
|
|
return(tarbell_prom[Addr & TARBELL_PROM_MASK]);
|
|
} else {
|
|
return(tarbell_ram[Addr & TARBELL_RAM_MASK]);
|
|
}
|
|
}
|
|
}
|
|
|