9c4779c061
The makefile now works for Linux and most Unix's. Howevr, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
612 lines
24 KiB
C
612 lines
24 KiB
C
/* pdp11_ta.c: PDP-11 cassette tape simulator
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Copyright (c) 2007-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ATAION OF CONTRATA, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNETAION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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ta TA11/TU60 cassette tape
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06-Aug-07 RMS Foward op at BOT skips initial file gap
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Magnetic tapes are represented as a series of variable records
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of the form:
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32b byte count
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byte 0
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byte 1
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:
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byte n-2
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byte n-1
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32b byte count
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If the byte count is odd, the record is padded with an extra byte
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of junk. File marks are represented by a byte count of 0.
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Cassette format differs in one very significant way: it has file gaps
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rather than file marks. If the controller spaces or reads into a file
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gap and then reverses direction, the file gap is not seen again. This
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is in contrast to magnetic tapes, where the file mark is a character
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sequence and is seen again if direction is reversed. In addition,
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cassettes have an initial file gap which is automatically skipped on
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forward operations from beginning of tape.
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*/
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#include "pdp11_defs.h"
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#include "sim_tape.h"
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#define TA_NUMDR 2 /* #drives */
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#define FNC u3 /* unit function */
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#define UST u4 /* unit status */
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#define TA_SIZE 93000 /* chars/tape */
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#define TA_MAXFR (TA_SIZE) /* max record lnt */
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/* Control/status - TACS */
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#define TACS_ERR (1 << CSR_V_ERR) /* error */
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#define TACS_CRC 0040000 /* CRC */
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#define TACS_BEOT 0020000 /* BOT/EOT */
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#define TACS_WLK 0010000 /* write lock */
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#define TACS_EOF 0004000 /* end file */
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#define TACS_TIM 0002000 /* timing */
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#define TACS_EMP 0001000 /* empty */
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#define TACS_V_UNIT 8 /* unit */
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#define TACS_M_UNIT (TA_NUMDR - 1)
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#define TACS_UNIT (TACS_M_UNIT << TACS_V_UNIT)
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#define TACS_TR (1 << CSR_V_DONE) /* transfer req */
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#define TACS_IE (1 << CSR_V_IE) /* interrupt enable */
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#define TACS_RDY 0000040 /* ready */
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#define TACS_ILBS 0000020 /* start CRC */
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#define TACS_V_FNC 1 /* function */
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#define TACS_M_FNC 07
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#define TACS_WFG 00
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#define TACS_WRITE 01
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#define TACS_READ 02
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#define TACS_SRF 03
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#define TACS_SRB 04
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#define TACS_SFF 05
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#define TACS_SFB 06
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#define TACS_REW 07
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#define TACS_2ND 010
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#define TACS_3RD 030
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#define TACS_FNC (TACS_M_FNC << TACS_V_FNC)
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#define TACS_GO (1 << CSR_V_GO) /* go */
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#define TACS_W (TACS_UNIT|TACS_IE|TACS_ILBS|TACS_FNC)
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#define TACS_XFRERR (TACS_ERR|TACS_CRC|TACS_WLK|TACS_EOF|TACS_TIM)
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#define GET_UNIT(x) (((x) >> TACS_V_UNIT) & TACS_M_UNIT)
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#define GET_FNC(x) (((x) >> TACS_V_FNC) & TACS_M_FNC)
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/* Function code flags */
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#define OP_WRI 01 /* op is a write */
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#define OP_REV 02 /* op is rev motion */
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#define OP_FWD 04 /* op is fwd motion */
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/* Unit status flags */
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#define UST_REV (OP_REV) /* last op was rev */
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#define UST_GAP 01 /* last op hit gap */
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extern int32 int_req[IPL_HLVL];
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extern FILE *sim_deb;
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uint32 ta_cs = 0; /* control/status */
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uint32 ta_idb = 0; /* input data buf */
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uint32 ta_odb = 0; /* output data buf */
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uint32 ta_write = 0; /* TU60 write flag */
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uint32 ta_bptr = 0; /* buf ptr */
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uint32 ta_blnt = 0; /* buf length */
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int32 ta_stime = 1000; /* start time */
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int32 ta_ctime = 100; /* char latency */
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uint32 ta_stopioe = 1; /* stop on error */
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uint8 *ta_xb = NULL; /* transfer buffer */
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static uint8 ta_fnc_tab[TACS_M_FNC + 1] = {
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OP_WRI|OP_FWD, OP_WRI|OP_FWD, OP_FWD, OP_REV,
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OP_REV , OP_FWD, OP_FWD, 0
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};
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DEVICE ta_dev;
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t_stat ta_rd (int32 *data, int32 PA, int32 access);
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t_stat ta_wr (int32 data, int32 PA, int32 access);
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t_stat ta_svc (UNIT *uptr);
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t_stat ta_reset (DEVICE *dptr);
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t_stat ta_attach (UNIT *uptr, char *cptr);
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t_stat ta_detach (UNIT *uptr);
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void ta_go (void);
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t_stat ta_map_err (UNIT *uptr, t_stat st);
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UNIT *ta_busy (void);
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void ta_set_tr (void);
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uint32 ta_updsta (UNIT *uptr);
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uint32 ta_crc (uint8 *buf, uint32 cnt);
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/* TA data structures
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ta_dev TA device descriptor
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ta_unit TA unit list
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ta_reg TA register list
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ta_mod TA modifier list
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*/
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DIB ta_dib = {
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IOBA_TA, IOLN_TA, &ta_rd, &ta_wr,
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1, IVCL (TA), VEC_TA, { NULL }
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};
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UNIT ta_unit[] = {
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{ UDATA (&ta_svc, UNIT_ATTABLE+UNIT_ROABLE, TA_SIZE) },
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{ UDATA (&ta_svc, UNIT_ATTABLE+UNIT_ROABLE, TA_SIZE) },
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};
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REG ta_reg[] = {
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{ ORDATA (TACS, ta_cs, 16) },
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{ ORDATA (TAIDB, ta_idb, 8) },
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{ ORDATA (TAODB, ta_odb, 8) },
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{ FLDATA (WRITE, ta_write, 0) },
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{ FLDATA (INT, IREQ (TA), INT_V_TA) },
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{ FLDATA (ERR, ta_cs, CSR_V_ERR) },
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{ FLDATA (TR, ta_cs, CSR_V_DONE) },
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{ FLDATA (IE, ta_cs, CSR_V_IE) },
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{ DRDATA (BPTR, ta_bptr, 17) },
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{ DRDATA (BLNT, ta_blnt, 17) },
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{ DRDATA (STIME, ta_stime, 24), PV_LEFT + REG_NZ },
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{ DRDATA (CTIME, ta_ctime, 24), PV_LEFT + REG_NZ },
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{ FLDATA (STOP_IOE, ta_stopioe, 0) },
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{ URDATA (UFNC, ta_unit[0].FNC, 8, 5, 0, TA_NUMDR, 0), REG_HRO },
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{ URDATA (UST, ta_unit[0].UST, 8, 2, 0, TA_NUMDR, 0), REG_HRO },
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{ URDATA (POS, ta_unit[0].pos, 10, T_ADDR_W, 0,
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TA_NUMDR, PV_LEFT | REG_RO) },
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{ ORDATA (DEVADDR, ta_dib.ba, 32), REG_HRO },
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{ ORDATA (DEVVEC, ta_dib.vec, 16), REG_HRO },
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{ NULL }
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};
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MTAB ta_mod[] = {
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{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
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{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
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// { MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
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// &sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
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{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", NULL,
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NULL, &sim_tape_show_capac, NULL },
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{ MTAB_XTD|MTAB_VDV, IOLN_TA, "ADDRESS", "ADDRESS",
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&set_addr, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
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&set_vec, &show_vec, NULL },
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{ 0 }
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};
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DEVICE ta_dev = {
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"TA", ta_unit, ta_reg, ta_mod,
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TA_NUMDR, 10, 31, 1, 8, 8,
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NULL, NULL, &ta_reset,
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NULL, &ta_attach, &ta_detach,
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&ta_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG
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};
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/* I/O dispatch routines, I/O addresses 17777500 - 17777503
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17777500 TACS read/write
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17777502 TADB read/write
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*/
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t_stat ta_rd (int32 *data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 01) { /* decode PA<1> */
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case 0: /* TACSR */
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*data = ta_updsta (NULL); /* update status */
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break;
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case 1: /* TADB */
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*data = ta_idb; /* return byte */
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ta_cs &= ~TACS_TR; /* clear tra req */
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ta_updsta (NULL);
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break;
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}
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return SCPE_OK;
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}
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t_stat ta_wr (int32 data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 01) { /* decode PA<1> */
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case 0: /* TACS */
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if (access == WRITEB) data = (PA & 1)? /* byte write? */
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(ta_cs & 0377) | (data << 8): /* merge old */
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(ta_cs & ~0377) | data;
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ta_cs = (ta_cs & ~TACS_W) | (data & TACS_W); /* merge new */
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if ((data & CSR_GO) && !ta_busy ()) /* go, not busy? */
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ta_go (); /* start operation */
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if (ta_cs & TACS_ILBS) /* ILBS inhibits TR */
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ta_cs &= ~TACS_TR;
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break;
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case 1: /* TADB */
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if (PA & 1) /* ignore odd byte */
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break;
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ta_odb = data; /* return byte */
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ta_cs &= ~TACS_TR; /* clear tra req */
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break;
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} /* end switch */
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ta_updsta (NULL); /* update status */
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return SCPE_OK;
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}
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/* Start a new operation - cassette is not busy */
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void ta_go (void)
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{
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UNIT *uptr = ta_dev.units + GET_UNIT (ta_cs);
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uint32 fnc = GET_FNC (ta_cs);
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uint32 flg = ta_fnc_tab[fnc];
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uint32 old_ust = uptr->UST;
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if (DEBUG_PRS (ta_dev)) fprintf (sim_deb,
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">>TA start: op=%o, old_sta = %o, pos=%d\n",
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fnc, uptr->UST, uptr->pos);
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ta_cs &= ~(TACS_XFRERR|TACS_EMP|TACS_TR|TACS_RDY); /* clr err, tr, rdy */
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ta_bptr = 0; /* init buffer */
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ta_blnt = 0;
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if ((uptr->flags & UNIT_ATT) == 0) {
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ta_cs |= TACS_ERR|TACS_EMP|TACS_RDY;
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return;
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}
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if (flg & OP_WRI) { /* write op? */
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if (sim_tape_wrp (uptr)) { /* locked? */
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ta_cs |= TACS_ERR|TACS_WLK|TACS_RDY; /* don't start */
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return;
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}
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ta_odb = 0;
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ta_write = 1;
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}
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else {
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ta_idb = 0;
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ta_write = 0;
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}
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ta_cs &= ~TACS_BEOT; /* tape in motion */
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uptr->FNC = fnc; /* save function */
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if ((fnc != TACS_REW) && !(flg & OP_WRI)) { /* spc/read cmd? */
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t_mtrlnt t;
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t_stat st;
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uptr->UST = flg & UST_REV; /* save direction */
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if (sim_tape_bot (uptr) && (flg & OP_FWD)) { /* spc/read fwd bot? */
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st = sim_tape_rdrecf (uptr, ta_xb, &t, TA_MAXFR); /* skip file gap */
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if (st != MTSE_TMK) /* not there? */
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sim_tape_rewind (uptr); /* restore tap pos */
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else old_ust = 0; /* defang next */
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}
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if ((old_ust ^ uptr->UST) == (UST_REV|UST_GAP)) { /* reverse in gap? */
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if (uptr->UST) /* skip file gap */
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sim_tape_rdrecr (uptr, ta_xb, &t, TA_MAXFR);
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else sim_tape_rdrecf (uptr, ta_xb, &t, TA_MAXFR);
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if (DEBUG_PRS (ta_dev))
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fprintf (sim_deb, ">>TA skip gap: op=%o, old_sta = %o, pos=%d\n",
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fnc, uptr->UST, uptr->pos);
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}
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}
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else uptr->UST = 0;
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sim_activate (uptr, ta_stime); /* schedule op */
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return;
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}
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/* Unit service */
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t_stat ta_svc (UNIT *uptr)
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{
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uint32 i, crc;
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uint32 flg = ta_fnc_tab[uptr->FNC & TACS_M_FNC];
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t_mtrlnt tbc;
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t_stat st, r;
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if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
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ta_cs |= TACS_ERR|TACS_EMP|TACS_RDY;
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ta_updsta (uptr); /* update status */
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return (ta_stopioe? SCPE_UNATT: SCPE_OK);
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}
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if (((flg & OP_FWD) && sim_tape_eot (uptr)) || /* illegal motion? */
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((flg & OP_REV) && sim_tape_bot (uptr))) {
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ta_cs |= TACS_ERR|TACS_BEOT|TACS_RDY; /* error */
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ta_updsta (uptr);
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return SCPE_OK;
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}
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r = SCPE_OK;
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switch (uptr->FNC) { /* case on function */
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case TACS_READ: /* read start */
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st = sim_tape_rdrecf (uptr, ta_xb, &ta_blnt, TA_MAXFR); /* get rec */
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if (st == MTSE_RECE) /* rec in err? */
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ta_cs |= TACS_ERR|TACS_CRC;
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else if (st != MTSE_OK) { /* other error? */
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r = ta_map_err (uptr, st); /* map error */
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break;
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}
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crc = ta_crc (ta_xb, ta_blnt); /* calculate CRC */
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ta_xb[ta_blnt++] = (crc >> 8) & 0377; /* append to buffer */
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ta_xb[ta_blnt++] = crc & 0377;
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uptr->FNC |= TACS_2ND; /* next state */
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sim_activate (uptr, ta_ctime); /* sched next char */
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return SCPE_OK;
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case TACS_READ|TACS_2ND: /* read char */
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if (ta_bptr < ta_blnt) /* more chars? */
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ta_idb = ta_xb[ta_bptr++];
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else { /* no */
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ta_idb = 0;
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ta_cs |= TACS_ERR|TACS_CRC; /* overrun */
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break; /* tape stops */
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}
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if (ta_cs & TACS_ILBS) { /* CRC seq? */
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uptr->FNC |= TACS_3RD; /* next state */
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sim_activate (uptr, ta_stime); /* sched CRC chk */
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}
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else {
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ta_set_tr (); /* set tra req */
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sim_activate (uptr, ta_ctime); /* sched next char */
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}
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return SCPE_OK;
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case TACS_READ|TACS_3RD: /* second read CRC */
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if (ta_bptr != ta_blnt) { /* partial read? */
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crc = ta_crc (ta_xb, ta_bptr + 2); /* actual CRC */
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if (crc != 0) /* must be zero */
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ta_cs |= TACS_ERR|TACS_CRC;
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}
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break; /* read done */
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case TACS_WRITE: /* write start */
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for (i = 0; i < TA_MAXFR; i++) /* clear buffer */
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ta_xb[i] = 0;
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ta_set_tr (); /* set tra req */
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uptr->FNC |= TACS_2ND; /* next state */
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sim_activate (uptr, ta_ctime); /* sched next char */
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return SCPE_OK;
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case TACS_WRITE|TACS_2ND: /* write char */
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if (ta_cs & TACS_ILBS) { /* CRC seq? */
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uptr->FNC |= TACS_3RD; /* next state */
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sim_activate (uptr, ta_stime); /* sched wri done */
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}
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else {
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if ((ta_bptr < TA_MAXFR) && /* room in buf? */
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((uptr->pos + ta_bptr) < uptr->capac)) /* room on tape? */
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ta_xb[ta_bptr++] = ta_odb; /* store char */
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ta_set_tr (); /* set tra req */
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sim_activate (uptr, ta_ctime); /* sched next char */
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}
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return SCPE_OK;
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case TACS_WRITE|TACS_3RD: /* write CRC */
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if (ta_bptr) { /* anything to write? */
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if (st = sim_tape_wrrecf (uptr, ta_xb, ta_bptr)) /* write, err? */
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r = ta_map_err (uptr, st); /* map error */
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}
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break; /* op done */
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case TACS_WFG: /* write file gap */
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if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
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r = ta_map_err (uptr, st); /* map error */
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break;
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case TACS_REW: /* rewind */
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sim_tape_rewind (uptr);
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ta_cs |= TACS_BEOT; /* bot, no error */
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break;
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case TACS_SRB: /* space rev blk */
|
|
if (st = sim_tape_sprecr (uptr, &tbc)) /* space rev, err? */
|
|
r = ta_map_err (uptr, st); /* map error */
|
|
break;
|
|
|
|
case TACS_SRF: /* space rev file */
|
|
while ((st = sim_tape_sprecr (uptr, &tbc)) == MTSE_OK) ;
|
|
if (st == MTSE_TMK) /* if tape mark, */
|
|
ta_cs |= TACS_EOF; /* set EOF, no err */
|
|
else r = ta_map_err (uptr, st); /* else map error */
|
|
break;
|
|
|
|
case TACS_SFB: /* space fwd blk */
|
|
if (st = sim_tape_sprecf (uptr, &tbc)) /* space rev, err? */
|
|
r = ta_map_err (uptr, st); /* map error */
|
|
ta_cs |= TACS_CRC; /* CRC sets, no err */
|
|
break;
|
|
|
|
case TACS_SFF: /* space fwd file */
|
|
while ((st = sim_tape_sprecf (uptr, &tbc)) == MTSE_OK) ;
|
|
if (st == MTSE_TMK) /* if tape mark, */
|
|
ta_cs |= TACS_EOF; /* set EOF, no err */
|
|
else r = ta_map_err (uptr, st); /* else map error */
|
|
break;
|
|
|
|
default: /* never get here! */
|
|
return SCPE_IERR;
|
|
} /* end case */
|
|
|
|
ta_cs |= TACS_RDY; /* set ready */
|
|
ta_updsta (uptr); /* update status */
|
|
if (DEBUG_PRS (ta_dev))
|
|
fprintf (sim_deb, ">>TA done: op=%o, status = %o, pos=%d\n",
|
|
uptr->FNC, ta_cs, uptr->pos);
|
|
return r;
|
|
}
|
|
|
|
/* Update controller status */
|
|
|
|
uint32 ta_updsta (UNIT *uptr)
|
|
{
|
|
if (uptr == NULL) { /* unit specified? */
|
|
if ((uptr = ta_busy ()) == NULL) /* use busy */
|
|
uptr = ta_dev.units + GET_UNIT (ta_cs); /* use sel unit */
|
|
}
|
|
else if (ta_cs & TACS_EOF) /* save EOF */
|
|
uptr->UST |= UST_GAP;
|
|
if (uptr->flags & UNIT_ATT) /* attached? */
|
|
ta_cs &= ~TACS_EMP;
|
|
else ta_cs |= TACS_EMP|TACS_RDY; /* no, empty, ready */
|
|
if ((ta_cs & TACS_IE) && /* int enabled? */
|
|
(ta_cs & (TACS_TR|TACS_RDY))) /* req or ready? */
|
|
SET_INT (TA); /* set int req */
|
|
else CLR_INT (TA); /* no, clr int req */
|
|
return ta_cs;
|
|
}
|
|
|
|
/* Set transfer request */
|
|
|
|
void ta_set_tr (void)
|
|
{
|
|
if (ta_cs & TACS_TR) /* flag still set? */
|
|
ta_cs |= (TACS_ERR|TACS_TIM);
|
|
else ta_cs |= TACS_TR; /* set xfr req */
|
|
if (ta_cs & TACS_IE) /* if ie, int req */
|
|
SET_INT (TA);
|
|
return;
|
|
}
|
|
|
|
/* Test if controller busy */
|
|
|
|
UNIT *ta_busy (void)
|
|
{
|
|
uint32 u;
|
|
UNIT *uptr;
|
|
|
|
for (u = 0; u < TA_NUMDR; u++) { /* loop thru units */
|
|
uptr = ta_dev.units + u;
|
|
if (sim_is_active (uptr))
|
|
return uptr;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/* Calculate CRC on buffer */
|
|
|
|
uint32 ta_crc (uint8 *buf, uint32 cnt)
|
|
{
|
|
uint32 crc, i, j;
|
|
|
|
crc = 0;
|
|
for (i = 0; i < cnt; i++) {
|
|
crc = crc ^ (((uint32) buf[i]) << 8);
|
|
for (j = 0; j < 8; j++) {
|
|
if (crc & 1)
|
|
crc = (crc >> 1) ^ 0xA001;
|
|
else crc = crc >> 1;
|
|
}
|
|
}
|
|
return crc;
|
|
}
|
|
|
|
/* Map error status */
|
|
|
|
t_stat ta_map_err (UNIT *uptr, t_stat st)
|
|
{
|
|
switch (st) {
|
|
|
|
case MTSE_FMT: /* illegal fmt */
|
|
case MTSE_UNATT: /* unattached */
|
|
ta_cs |= TACS_ERR|TACS_CRC;
|
|
case MTSE_OK: /* no error */
|
|
return SCPE_IERR; /* never get here! */
|
|
|
|
case MTSE_TMK: /* end of file */
|
|
ta_cs |= TACS_ERR|TACS_EOF;
|
|
break;
|
|
|
|
case MTSE_IOERR: /* IO error */
|
|
ta_cs |= TACS_ERR|TACS_CRC; /* set crc err */
|
|
if (ta_stopioe)
|
|
return SCPE_IOERR;
|
|
break;
|
|
|
|
case MTSE_INVRL: /* invalid rec lnt */
|
|
ta_cs |= TACS_ERR|TACS_CRC; /* set crc err */
|
|
return SCPE_MTRLNT;
|
|
|
|
case MTSE_RECE: /* record in error */
|
|
case MTSE_EOM: /* end of medium */
|
|
ta_cs |= TACS_ERR|TACS_CRC; /* set crc err */
|
|
break;
|
|
|
|
case MTSE_BOT: /* reverse into BOT */
|
|
ta_cs |= TACS_ERR|TACS_BEOT; /* set bot */
|
|
break;
|
|
|
|
case MTSE_WRP: /* write protect */
|
|
ta_cs |= TACS_ERR|TACS_WLK; /* set wlk err */
|
|
break;
|
|
}
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat ta_reset (DEVICE *dptr)
|
|
{
|
|
uint32 u;
|
|
UNIT *uptr;
|
|
|
|
ta_cs = 0;
|
|
ta_idb = 0;
|
|
ta_odb = 0;
|
|
ta_write = 0;
|
|
ta_bptr = 0;
|
|
ta_blnt = 0;
|
|
CLR_INT (TA); /* clear interrupt */
|
|
for (u = 0; u < TA_NUMDR; u++) { /* loop thru units */
|
|
uptr = ta_dev.units + u;
|
|
sim_cancel (uptr); /* cancel activity */
|
|
sim_tape_reset (uptr); /* reset tape */
|
|
}
|
|
if (ta_xb == NULL)
|
|
ta_xb = (uint8 *) calloc (TA_MAXFR + 2, sizeof (uint8));
|
|
if (ta_xb == NULL)
|
|
return SCPE_MEM;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Attach routine */
|
|
|
|
t_stat ta_attach (UNIT *uptr, char *cptr)
|
|
{
|
|
t_stat r;
|
|
|
|
r = sim_tape_attach (uptr, cptr);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
ta_updsta (NULL);
|
|
uptr->UST = 0;
|
|
return r;
|
|
}
|
|
|
|
/* Detach routine */
|
|
|
|
t_stat ta_detach (UNIT* uptr)
|
|
{
|
|
t_stat r;
|
|
|
|
if (!(uptr->flags & UNIT_ATT)) /* check attached */
|
|
return SCPE_OK;
|
|
r = sim_tape_detach (uptr);
|
|
ta_updsta (NULL);
|
|
uptr->UST = 0;
|
|
return r;
|
|
}
|