334 lines
13 KiB
C
334 lines
13 KiB
C
/* i7094_drm.c: 7289/7320A drum simulator
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Copyright (c) 2005-2011, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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drm 7289/7320A "fast" drum
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23-Mar-12 RMS Corrected disk addressing and logical disk crossing
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25-Mar-11 RMS Updated based on RPQ
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This simulator implements a subset of the functionality of the 7289, as
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required by CTSS.
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- The drum channel/controller behaves like a hybrid of the 7607 and the 7909.
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It responds to SCD (like the 7909), gets its address from the channel
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program (like the 7909), but responds to IOCD/IOCP (like the 7607) and
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sets channel flags (like the 7607).
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- The drum channel supports at least 2 drums. The maximum is 4 or less.
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Physical drums are numbered from 0.
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- Each drum has a capacity of 192K 36b words. This is divided into 6
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"logical" drum of 32KW each. Each "logical" drum has 16 2048W "sectors".
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Logical drums are numbered from 1.
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- The drum allows transfers across sector boundaries, but not logical
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drum boundaries.
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- The drum's only supports IOCD, IOCP, and IOCT. IOCT (and chaining mode)
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are not used by CTSS.
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Limitations in this simulator:
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- Chain mode is not implemented.
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- LPCR is not implemented.
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For speed, the entire drum is buffered in memory.
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*/
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#include "i7094_defs.h"
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#include <math.h>
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#define DRM_NUMDR 4 /* drums/controller */
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/* Drum geometry */
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#define DRM_NUMWDG 1024 /* words/group */
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#define DRM_GPMASK (DRM_NUMWDG - 1) /* group mask */
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#define DRM_NUMWDS 2048 /* words/sector */
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#define DRM_SCMASK (DRM_NUMWDS - 1) /* sector mask */
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#define DRM_NUMSC 16 /* sectors/log drum */
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#define DRM_NUMWDL (DRM_NUMWDS * DRM_NUMSC) /* words/log drum */
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#define DRM_LDMASK (DRM_NUMWDL - 1) /* logical disk mask */
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#define DRM_NUMLD 6 /* log drums/phys drum */
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#define DRM_SIZE (DRM_NUMLD * DRM_NUMWDL) /* words/phys drum */
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#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \
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((double) DRM_NUMWDS)))
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#define GET_PROT(x) ((x[drm_phy] >> (drm_log - 1)) & 1)
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/* Drum address from channel */
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#define DRM_V_PHY 30 /* physical drum sel */
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#define DRM_M_PHY 03
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#define DRM_V_LOG 18 /* logical drum sel */
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#define DRM_M_LOG 07
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#define DRM_V_WDA 0 /* word address */
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#define DRM_M_WDA (DRM_NUMWDL - 1)
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#define DRM_GETPHY(x) (((uint32) ((x) >> DRM_V_PHY)) & DRM_M_PHY)
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#define DRM_GETLOG(x) ((((uint32) (x)) >> DRM_V_LOG) & DRM_M_LOG)
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#define DRM_GETWDA(x) ((((uint32) (x)) >> DRM_V_WDA) & DRM_M_WDA)
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#define DRM_GETDA(l,x) ((((l) - 1) * DRM_NUMWDL) + (x))
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/* SCD word */
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#define DRMS_V_IOC 35 /* IO check */
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#define DRMS_V_INV 33 /* invalid command */
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#define DRMS_V_PHY 31 /* physical drum */
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#define DRMS_V_LOG 28 /* logical drum */
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#define DRMS_V_WDA 13 /* disk address */
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#define DRMS_V_WRP 22 /* write protect */
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#define DRMS_V_LPCR 18 /* LPRCR */
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#define DRMS_M_LPCR 017
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/* Drum controller states */
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#define DRM_IDLE 0
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#define DRM_1ST 1
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#define DRM_FILL 2
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#define DRM_DATA 3
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#define DRM_EOD 4
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uint32 drm_ch = CH_G; /* drum channel */
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uint32 drm_da = 0; /* drum address */
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uint32 drm_phy = 0; /* physical drum */
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uint32 drm_log = 0; /* logical drum */
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uint32 drm_sta = 0; /* state */
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uint32 drm_op = 0; /* operation */
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t_uint64 drm_chob = 0; /* output buf */
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uint32 drm_chob_v = 0; /* valid */
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uint32 drm_prot[DRM_NUMDR] = { 0 }; /* drum protect sw */
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int32 drm_time = 10; /* inter-word time */
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extern uint32 ind_ioc;
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t_stat drm_svc (UNIT *uptr);
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t_stat drm_reset (DEVICE *dptr);
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t_stat drm_chsel (uint32 ch, uint32 sel, uint32 unit);
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t_stat drm_chwr (uint32 ch, t_uint64 val, uint32 flags);
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t_bool drm_da_incr (void);
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/* DRM data structures
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drm_dev DRM device descriptor
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drm_unit DRM unit descriptor
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drm_reg DRM register list
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*/
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DIB drm_dib = { &drm_chsel, &drm_chwr };
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UNIT drm_unit[] = {
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{ UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+
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UNIT_MUSTBUF+UNIT_DISABLE, DRM_SIZE) },
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{ UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+
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UNIT_MUSTBUF+UNIT_DISABLE, DRM_SIZE) },
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{ UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+
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UNIT_MUSTBUF+UNIT_DISABLE+UNIT_DIS, DRM_SIZE) },
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{ UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+
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UNIT_MUSTBUF+UNIT_DISABLE+UNIT_DIS, DRM_SIZE) },
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};
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REG drm_reg[] = {
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{ ORDATA (STATE, drm_sta, 3) },
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{ ORDATA (UNIT,drm_phy, 2), REG_RO },
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{ ORDATA (LOG, drm_log, 3), REG_RO },
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{ ORDATA (DA, drm_da, 15) },
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{ FLDATA (OP, drm_op, 0) },
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{ ORDATA (CHOB, drm_chob, 36) },
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{ FLDATA (CHOBV, drm_chob_v, 0) },
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{ ORDATA (PROT0, drm_prot[0], 6) },
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{ ORDATA (PROT1, drm_prot[1], 6) },
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{ ORDATA (PROT2, drm_prot[2], 6) },
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{ ORDATA (PROT3, drm_prot[3], 6) },
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{ DRDATA (TIME, drm_time, 24), REG_NZ + PV_LEFT },
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{ DRDATA (CHAN, drm_ch, 3), REG_HRO },
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{ NULL }
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};
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MTAB drm_mtab[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "CHANNEL", NULL, NULL, &ch_show_chan },
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{ 0 }
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};
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DEVICE drm_dev = {
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"DRM", drm_unit, drm_reg, drm_mtab,
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DRM_NUMDR, 8, 18, 1, 8, 36,
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NULL, NULL, &drm_reset,
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NULL, NULL, NULL,
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&drm_dib, DEV_DIS
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};
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/* Channel select routine */
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t_stat drm_chsel (uint32 ch, uint32 sel, uint32 unit)
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{
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drm_ch = ch; /* save channel */
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if (sel & CHSL_NDS) /* nds? nop */
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return ch6_end_nds (ch);
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switch (sel) { /* case on cmd */
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case CHSL_RDS: /* read */
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case CHSL_WRS: /* write */
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if (drm_sta != DRM_IDLE) /* busy? */
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return ERR_STALL;
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drm_sta = DRM_1ST; /* initial state */
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if (sel == CHSL_WRS) /* set read/write */
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drm_op = 1;
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else drm_op = 0; /* LCHx sends addr */
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break; /* wait for addr */
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default: /* other */
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return STOP_ILLIOP;
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}
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return SCPE_OK;
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}
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/* Channel diagnostic store routine */
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t_uint64 drm_sdc (uint32 ch)
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{
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t_uint64 val;
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val = (((t_uint64) ind_ioc) << DRMS_V_IOC) |
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(((t_uint64) drm_phy) << DRMS_V_PHY) |
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(((t_uint64) drm_log) << DRMS_V_LOG) |
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(((t_uint64) (drm_da & ~ DRM_GPMASK)) << DRMS_V_WDA) |
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(((t_uint64) GET_PROT(drm_prot)) << DRMS_V_WRP);
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return val;
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}
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/* Channel write routine */
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t_stat drm_chwr (uint32 ch, t_uint64 val, uint32 flags)
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{
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int32 cp, dp;
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if (drm_sta == DRM_1ST) {
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drm_phy = DRM_GETPHY (val); /* get unit */
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drm_log = DRM_GETLOG (val); /* get logical disk */
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drm_da = DRM_GETWDA (val); /* get drum word addr */
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if ((drm_unit[drm_phy].flags & UNIT_DIS) || /* disabled unit? */
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(drm_log == 0) || (drm_log > DRM_NUMLD) || /* invalid log drum? */
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((drm_op != 0) && (GET_PROT (drm_prot) != 0))) { /* write to prot drum? */
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ch6_err_disc (ch, U_DRM, CHF_TRC); /* disconnect */
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drm_sta = DRM_IDLE;
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return SCPE_OK;
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}
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cp = GET_POS (drm_time); /* current pos in sec */
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dp = (drm_da & DRM_SCMASK) - cp; /* delta to desired pos */
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if (dp <= 0) /* if neg, add rev */
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dp = dp + DRM_NUMWDS;
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sim_activate (&drm_unit[drm_phy], dp * drm_time); /* schedule */
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if (drm_op) { /* if write, get word */
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ch6_req_wr (ch, U_DRM);
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drm_sta = DRM_FILL; /* sector fill */
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}
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else drm_sta = DRM_DATA; /* data transfer */
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drm_chob = 0; /* clr, inval buffer */
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drm_chob_v = 0;
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}
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else {
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drm_chob = val & DMASK;
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drm_chob_v = 1;
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}
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return SCPE_OK;
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}
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/* Unit service - this code assumes the entire drum is buffered */
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t_stat drm_svc (UNIT *uptr)
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{
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uint32 i;
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t_uint64 *fbuf = (t_uint64 *) uptr->filebuf;
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uint32 da = DRM_GETDA (drm_log, drm_da);
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if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? */
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ch6_err_disc (drm_ch, U_DRM, CHF_TRC); /* set TRC, disc */
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drm_sta = DRM_IDLE; /* drum is idle */
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return SCPE_UNATT;
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}
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switch (drm_sta) { /* case on state */
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case DRM_FILL: /* write, clr group */
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for (i = da & ~DRM_GPMASK; i <= (da | DRM_GPMASK); i++)
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fbuf[i] = 0; /* clear group */
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if (i >= uptr-> hwmark)
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uptr->hwmark = i + 1;
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drm_sta = DRM_DATA; /* now data */
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/* fall through */
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case DRM_DATA: /* data */
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if (drm_op) { /* write? */
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if (drm_chob_v) /* valid? clear */
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drm_chob_v = 0;
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else if (ch6_qconn (drm_ch, U_DRM)) /* no, chan conn? */
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ind_ioc = 1; /* io check */
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fbuf[da] = drm_chob; /* get data */
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if (da >= uptr->hwmark)
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uptr->hwmark = da + 1;
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if (!drm_da_incr ()) /* room for more? */
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ch6_req_wr (drm_ch, U_DRM);
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}
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else{ /* read */
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ch6_req_rd (drm_ch, U_DRM, fbuf[da], 0); /* send word to channel */
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drm_da_incr ();
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}
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sim_activate (uptr, drm_time); /* next word */
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break;
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case DRM_EOD: /* end logical disk */
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if (ch6_qconn (drm_ch, U_DRM)) /* drum still conn? */
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ch6_err_disc (drm_ch, U_DRM, CHF_EOF); /* set EOF, disc */
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drm_sta = DRM_IDLE; /* drum is idle */
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break;
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} /* end case */
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return SCPE_OK;
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}
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/* Increment drum address - return true, set new state if end of logical disk */
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t_bool drm_da_incr (void)
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{
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drm_da = (drm_da + 1) & DRM_LDMASK;
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if (drm_da != 0)
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return FALSE;
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drm_sta = DRM_EOD;
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return TRUE;
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}
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/* Reset routine */
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t_stat drm_reset (DEVICE *dptr)
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{
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uint32 i;
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drm_phy = 0;
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drm_log = 0;
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drm_da = 0;
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drm_op = 0;
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drm_sta = DRM_IDLE;
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drm_chob = 0;
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drm_chob_v = 0;
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for (i = 0; i < dptr->numunits; i++)
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sim_cancel (dptr->units + i);
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return SCPE_OK;
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}
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