492 lines
19 KiB
C
492 lines
19 KiB
C
/*************************************************************************
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* *
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* $Id: n8vem.c 1995 2008-07-15 03:59:13Z hharte $ *
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* *
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* Copyright (c) 2007-2008 Howard M. Harte. *
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* http://www.hartetec.com *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining *
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* a copy of this software and associated documentation files (the *
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* "Software"), to deal in the Software without restriction, including *
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* without limitation the rights to use, copy, modify, merge, publish, *
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* distribute, sublicense, and/or sell copies of the Software, and to *
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* permit persons to whom the Software is furnished to do so, subject to *
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* the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be *
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* included in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *
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* NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *
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* *
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* Except as contained in this notice, the name of Howard M. Harte shall *
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* not be used in advertising or otherwise to promote the sale, use or *
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* other dealings in this Software without prior written authorization *
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* Howard M. Harte. *
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* *
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* SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
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* *
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* Module Description: *
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* N8VEM Single-Board Computer I/O module for SIMH. *
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* http://groups.google.com/group/n8vem/web/n8vem-single-board-computer-home-page *
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* *
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* Environment: *
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* User mode only *
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* *
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*************************************************************************/
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/* #define DBG_MSG */
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#include "altairz80_defs.h"
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#if defined (_WIN32)
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#include <windows.h>
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#endif
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#ifdef DBG_MSG
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#define DBG_PRINT(args) printf args
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#else
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#define DBG_PRINT(args)
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#endif
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/* Debug flags */
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#define ERROR_MSG (1 << 0)
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#define PIO_MSG (1 << 1)
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#define UART_MSG (1 << 2)
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#define RTC_MSG (1 << 3)
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#define MPCL_MSG (1 << 4)
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#define ROM_MSG (1 << 5)
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#define VERBOSE_MSG (1 << 7)
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#define N8VEM_MAX_DRIVES 2
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typedef struct {
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PNP_INFO pnp; /* Plug and Play */
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uint8 *ram;
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uint8 *rom;
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uint8 rom_attached;
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uint8 uart_scr;
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uint8 uart_lcr;
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uint8 mpcl_ram;
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uint8 mpcl_rom;
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} N8VEM_INFO;
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static N8VEM_INFO n8vem_info_data = { { 0x0, 0x8000, 0x60, 32 } };
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static N8VEM_INFO *n8vem_info = &n8vem_info_data;
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extern t_stat set_membase(UNIT *uptr, int32 val, char *cptr, void *desc);
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extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, void *desc);
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extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);
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extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);
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extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
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int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
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extern uint32 PCX;
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extern REG *sim_PC;
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extern int32 find_unit_index (UNIT *uptr);
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static t_stat n8vem_reset(DEVICE *n8vem_dev);
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static t_stat n8vem_boot(int32 unitno, DEVICE *dptr);
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static t_stat n8vem_attach(UNIT *uptr, char *cptr);
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static t_stat n8vem_detach(UNIT *uptr);
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static uint8 N8VEM_Read(const uint32 Addr);
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static uint8 N8VEM_Write(const uint32 Addr, uint8 cData);
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static int32 n8vemdev(const int32 port, const int32 io, const int32 data);
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static int32 n8vem_mem(const int32 port, const int32 io, const int32 data);
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static int32 save_rom = 0x00; /* When set to 1, saves ROM back to file on disk at detach time */
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static int32 save_ram = 0x00; /* When set to 1, saves RAM back to file on disk at detach time */
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static int32 n8vem_pio1a = 0x00; /* 8255 PIO1A IN Port */
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static int32 n8vem_pio1b = 0x00; /* 8255 PIO1B OUT Port */
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static int32 n8vem_pio1c = 0x00; /* 8255 PIO1C IN Port */
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static int32 n8vem_pio1ctrl = 0x00; /* 8255 PIO1 Control Port */
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#define N8VEM_ROM_SIZE (1024 * 1024)
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#define N8VEM_RAM_SIZE (512 * 1024)
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#define N8VEM_RAM_SELECT (1 << 7)
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#define N8VEM_RAM_MASK 0x0F
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#define N8VEM_ROM_MASK 0x1F
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#define N8VEM_ADDR_MASK 0x7FFF
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static UNIT n8vem_unit[] = {
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, N8VEM_ROM_SIZE) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, N8VEM_RAM_SIZE) }
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};
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static REG n8vem_reg[] = {
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{ HRDATA (SAVEROM, save_rom, 1), },
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{ HRDATA (SAVERAM, save_ram, 1), },
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{ HRDATA (PIO1A, n8vem_pio1a, 8), },
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{ HRDATA (PIO1B, n8vem_pio1b, 8), },
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{ HRDATA (PIO1C, n8vem_pio1c, 8), },
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{ HRDATA (PIO1CTRL, n8vem_pio1ctrl, 8), },
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{ NULL }
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};
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static MTAB n8vem_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "MEMBASE", "MEMBASE", &set_membase, &show_membase, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL },
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{ 0 }
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};
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/* Debug Flags */
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static DEBTAB n8vem_dt[] = {
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{ "ERROR", ERROR_MSG },
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{ "PIO", PIO_MSG },
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{ "UART", UART_MSG },
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{ "RTC", RTC_MSG },
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{ "ROM", ROM_MSG },
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{ "VERBOSE",VERBOSE_MSG },
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{ NULL, 0 }
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};
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DEVICE n8vem_dev = {
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"N8VEM", n8vem_unit, n8vem_reg, n8vem_mod,
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N8VEM_MAX_DRIVES, 10, 31, 1, N8VEM_MAX_DRIVES, N8VEM_MAX_DRIVES,
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NULL, NULL, &n8vem_reset,
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&n8vem_boot, &n8vem_attach, &n8vem_detach,
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&n8vem_info_data, (DEV_DISABLE | DEV_DIS | DEV_DEBUG), ERROR_MSG,
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n8vem_dt, NULL, "Single-Board Computer N8VEM"
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};
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/* Reset routine */
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static t_stat n8vem_reset(DEVICE *dptr)
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{
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PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
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sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Reset.\n");
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if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
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sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &n8vemdev, TRUE);
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sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &n8vem_mem, TRUE);
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free(n8vem_info->ram);
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free(n8vem_info->rom);
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} else {
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/* Connect N8VEM at base address */
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if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &n8vemdev, FALSE) != 0) {
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printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
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return SCPE_ARG;
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}
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/* Connect N8VEM Memory (512K RAM, 1MB FLASH) */
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if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &n8vem_mem, FALSE) != 0) {
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printf("%s: error mapping MEM resource at 0x%04x\n", __FUNCTION__, pnp->mem_base);
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return SCPE_ARG;
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}
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n8vem_info->ram = calloc(1, (N8VEM_RAM_SIZE));
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n8vem_info->rom = calloc(1, (N8VEM_ROM_SIZE));
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/* Clear the RAM and ROM mapping registers */
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n8vem_info->mpcl_ram = 0;
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n8vem_info->mpcl_rom = 0;
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}
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return SCPE_OK;
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}
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static t_stat n8vem_boot(int32 unitno, DEVICE *dptr)
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{
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sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Boot.\n");
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/* Clear the RAM and ROM mapping registers */
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n8vem_info->mpcl_ram = 0;
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n8vem_info->mpcl_rom = 0;
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/* Set the PC to 0, and go. */
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*((int32 *) sim_PC->loc) = 0;
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return SCPE_OK;
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}
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/* Attach routine */
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static t_stat n8vem_attach(UNIT *uptr, char *cptr)
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{
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t_stat r;
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int32 i = 0, rtn;
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i = find_unit_index(uptr);
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if (i == -1) {
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return (SCPE_IERR);
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}
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r = attach_unit(uptr, cptr); /* attach unit */
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if ( r != SCPE_OK) /* error? */
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return r;
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/* Determine length of this disk */
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uptr->capac = sim_fsize(uptr->fileref);
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sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Attach %s.\n", i == 0 ? "ROM" : "RAM");
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if(i == 0) { /* Attaching ROM */
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n8vem_info->rom_attached = TRUE;
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/* Erase ROM */
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memset(n8vem_info->rom, 0xFF, N8VEM_ROM_SIZE);
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if(uptr->capac > 0) {
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/* Only read in enough of the file to fill the ROM. */
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if (uptr->capac > N8VEM_ROM_SIZE)
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uptr->capac = N8VEM_ROM_SIZE;
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rtn = fread((void *)(n8vem_info->rom), uptr->capac, 1, uptr->fileref);
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sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Reading %d bytes into ROM." " Result = %ssuccessful.\n", uptr->capac, rtn == 1 ? "" : "not ");
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}
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} else { /* attaching RAM */
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/* Erase RAM */
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memset(n8vem_info->ram, 0x00, N8VEM_RAM_SIZE);
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if(uptr->capac > 0) {
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/* Only read in enough of the file to fill the RAM. */
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if(uptr->capac > N8VEM_RAM_SIZE)
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uptr->capac = N8VEM_RAM_SIZE;
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rtn = fread((void *)(n8vem_info->ram), uptr->capac, 1, uptr->fileref);
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sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Reading %d bytes into RAM." " Result = %ssuccessful.\n", uptr->capac, rtn == 1 ? "" : "not ");
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}
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}
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return r;
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}
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/* Detach routine */
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static t_stat n8vem_detach(UNIT *uptr)
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{
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t_stat r;
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int32 i = 0;
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i = find_unit_index(uptr);
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if (i == -1) {
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return (SCPE_IERR);
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}
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sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Detach %s.\n", i == 0 ? "ROM" : "RAM");
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/* rewind to the beginning of the file. */
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sim_fseek(uptr->fileref, 0, SEEK_SET);
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if(i == 0) { /* ROM */
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/* Save the ROM back to disk if SAVEROM is set. */
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if(save_rom == 1) {
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sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Writing %d bytes into ROM image.\n", N8VEM_ROM_SIZE);
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fwrite((void *)(n8vem_info->rom), N8VEM_ROM_SIZE, 1, uptr->fileref);
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}
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} else { /* RAM */
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/* Save the RAM back to disk if SAVERAM is set. */
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if(save_ram == 1) {
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sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Writing %d bytes into RAM image.\n", N8VEM_RAM_SIZE);
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fwrite((void *)(n8vem_info->ram), N8VEM_RAM_SIZE, 1, uptr->fileref);
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}
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}
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r = detach_unit(uptr); /* detach unit */
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return r;
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}
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/* RAM MEMORY PAGE CONFIGURATION LATCH CONTROL PORT ( IO_Y3 ) INFORMATION
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*
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* 7 6 5 4 3 2 1 0 ONLY APPLICABLE TO THE LOWER MEMORY PAGE $0000-$7FFF
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* ^ ^ ^ ^ ^ ^ ^ ^
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* : : : : : : : :--0 = A15 RAM ADDRESS LINE DEFAULT IS 0
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* : : : : : : :----0 = A16 RAM ADDRESS LINE DEFAULT IS 0
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* : : : : : :------0 = A17 RAM ADDRESS LINE DEFAULT IS 0
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* : : : : :--------0 = A18 RAM ADDRESS LINE DEFAULT IS 0
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* : : : :-----------0 =
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* : : :-------------0 =
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* : :---------------0 =
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* :-----------------0 =
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*
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* ROM MEMORY PAGE CONFIGURATION LATCH CONTROL PORT ( IO_Y3+$04 ) INFORMATION
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*
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* 7 6 5 4 3 2 1 0 ONLY APPLICABLE TO THE LOWER MEMORY PAGE $0000-$7FFF
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* ^ ^ ^ ^ ^ ^ ^ ^
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* : : : : : : : :--0 = A15 ROM ADDRESS LINE DEFAULT IS 0
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* : : : : : : :----0 = A16 ROM ADDRESS LINE DEFAULT IS 0
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* : : : : : :------0 = A17 ROM ADDRESS LINE DEFAULT IS 0
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* : : : : :--------0 = A18 ROM ADDRESS LINE DEFAULT IS 0
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* : : : :-----------0 = A19 ROM ONLY ADDRESS LINE DEFAULT IS 0
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* : : :-------------0 =
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* : :---------------0 =
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* :-----------------0 = ROM SELECT (0=ROM, 1=RAM) DEFAULT IS 0
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*/
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static int32 n8vem_mem(const int32 Addr, const int32 write, const int32 data)
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{
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/* DBG_PRINT(("N8VEM: ROM %s, Addr %04x" NLP, write ? "WR" : "RD", Addr)); */
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if(write) {
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if(n8vem_info->mpcl_rom & N8VEM_RAM_SELECT)
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{
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n8vem_info->ram[((n8vem_info->mpcl_ram & N8VEM_RAM_MASK) << 15) | (Addr & N8VEM_ADDR_MASK)] = data;
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} else {
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if(save_rom == 1) {
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n8vem_info->rom[((n8vem_info->mpcl_rom & N8VEM_ROM_MASK) << 15) | (Addr & N8VEM_ADDR_MASK)] = data;
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} else {
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sim_debug(ROM_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR ROM[0x%05x]: Cannot write to ROM.\n", PCX, ((n8vem_info->mpcl_rom & N8VEM_ROM_MASK) << 15) | (Addr & N8VEM_ADDR_MASK));
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}
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}
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return 0;
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} else {
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if(n8vem_info->mpcl_rom & N8VEM_RAM_SELECT)
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{
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return n8vem_info->ram[((n8vem_info->mpcl_ram & N8VEM_RAM_MASK) << 15) | (Addr & N8VEM_ADDR_MASK)];
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} else {
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return n8vem_info->rom[((n8vem_info->mpcl_rom & N8VEM_ROM_MASK) << 15) | (Addr & N8VEM_ADDR_MASK)];
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}
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}
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}
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static int32 n8vemdev(const int32 port, const int32 io, const int32 data)
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{
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/* DBG_PRINT(("N8VEM: IO %s, Port %02x\n", io ? "WR" : "RD", port)); */
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if(io) {
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N8VEM_Write(port, data);
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return 0;
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} else {
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return(N8VEM_Read(port));
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}
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}
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#define N8VEM_PIO1A 0x00 /* (INPUT) IN 1-8 */
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#define N8VEM_PIO1B 0x01 /* (OUTPUT) OUT TO LEDS */
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#define N8VEM_PIO1C 0x02 /* (INPUT) */
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#define N8VEM_PIO1CONT 0x03 /* CONTROL BYTE PIO 82C55 */
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#define N8VEM_UART_DATA 0x08
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#define N8VEM_UART_RSR 0x09
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#define N8VEM_UART_INTR 0x0A
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#define N8VEM_UART_LCR 0x0B
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#define N8VEM_UART_MCR 0x0C
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#define N8VEM_UART_LSR 0x0D
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#define N8VEM_UART_MSR 0x0E
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#define N8VEM_UART_SCR 0x0F
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#define N8VEM_MPCL_RAM 0x18 /* RAM Address control port */
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#define N8VEM_MPCL_RAM1 0x19 /* RAM Address control port */
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#define N8VEM_MPCL_RAM2 0x1A /* RAM Address control port */
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#define N8VEM_MPCL_RAM3 0x1B /* RAM Address control port */
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#define N8VEM_MPCL_ROM 0x1C /* ROM Address control port */
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#define N8VEM_MPCL_ROM1 0x1D /* ROM Address control port */
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#define N8VEM_MPCL_ROM2 0x1E /* ROM Address control port */
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#define N8VEM_MPCL_ROM3 0x1F /* ROM Address control port */
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extern int32 sio0d(const int32 port, const int32 io, const int32 data);
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extern int32 sio0s(const int32 port, const int32 io, const int32 data);
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static uint8 N8VEM_Read(const uint32 Addr)
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{
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uint8 cData = 0xFF;
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switch(Addr & 0x1F) {
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case N8VEM_PIO1A:
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sim_debug(PIO_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " RD: PIO1A\n", PCX);
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cData = n8vem_pio1a;
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break;
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case N8VEM_PIO1B:
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sim_debug(PIO_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " RD: PIO1B\n", PCX);
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cData = n8vem_pio1b;
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break;
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case N8VEM_PIO1C:
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sim_debug(PIO_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " RD: PIO1C\n", PCX);
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cData = n8vem_pio1c;
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break;
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case N8VEM_PIO1CONT:
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sim_debug(PIO_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " RD: PIO1CTRL\n", PCX);
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cData = n8vem_pio1ctrl;
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break;
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case N8VEM_UART_LCR:
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cData = n8vem_info->uart_lcr;
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break;
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case N8VEM_UART_DATA:
|
|
case N8VEM_UART_RSR:
|
|
case N8VEM_UART_LSR:
|
|
case N8VEM_UART_INTR:
|
|
case N8VEM_UART_MCR:
|
|
case N8VEM_UART_MSR:
|
|
sim_debug(UART_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " RD[%02x]: UART not Implemented.\n", PCX, Addr);
|
|
break;
|
|
case N8VEM_UART_SCR: /* 16550 Scratchpad, implemented so software can detect UART is present */
|
|
cData = n8vem_info->uart_scr;
|
|
break;
|
|
case N8VEM_MPCL_RAM:
|
|
case N8VEM_MPCL_RAM1:
|
|
case N8VEM_MPCL_RAM2:
|
|
case N8VEM_MPCL_RAM3:
|
|
sim_debug(MPCL_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " RD: MPCL_RAM not Implemented.\n", PCX);
|
|
break;
|
|
case N8VEM_MPCL_ROM:
|
|
case N8VEM_MPCL_ROM1:
|
|
case N8VEM_MPCL_ROM2:
|
|
case N8VEM_MPCL_ROM3:
|
|
sim_debug(MPCL_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " RD: MPCL_ROM not Implemented.\n", PCX);
|
|
break;
|
|
default:
|
|
sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " RD[%02x]: not Implemented.\n", PCX, Addr);
|
|
break;
|
|
}
|
|
|
|
return (cData);
|
|
|
|
}
|
|
|
|
static uint8 N8VEM_Write(const uint32 Addr, uint8 cData)
|
|
{
|
|
|
|
switch(Addr & 0x1F) {
|
|
case N8VEM_PIO1A:
|
|
sim_debug(PIO_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR: PIO1A=0x%02x\n", PCX, cData);
|
|
n8vem_pio1a = cData;
|
|
break;
|
|
case N8VEM_PIO1B:
|
|
sim_debug(PIO_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR: PIO1B=0x%02x\n", PCX, cData);
|
|
n8vem_pio1b = cData;
|
|
break;
|
|
case N8VEM_PIO1C:
|
|
sim_debug(PIO_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR: PIO1C=0x%02x\n", PCX, cData);
|
|
n8vem_pio1c = cData;
|
|
break;
|
|
case N8VEM_PIO1CONT:
|
|
sim_debug(PIO_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR: PIO1_CTRL=0x%02x\n", PCX, cData);
|
|
n8vem_pio1ctrl = cData;
|
|
break;
|
|
case N8VEM_UART_LCR:
|
|
sim_debug(UART_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR: UART LCR=%02x.\n", PCX, cData);
|
|
n8vem_info->uart_lcr = cData;
|
|
break;
|
|
case N8VEM_UART_DATA:
|
|
case N8VEM_UART_RSR:
|
|
case N8VEM_UART_INTR:
|
|
case N8VEM_UART_MCR:
|
|
case N8VEM_UART_LSR:
|
|
case N8VEM_UART_MSR:
|
|
sim_debug(UART_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR[%02x]: UART not Implemented.\n", PCX, Addr);
|
|
break;
|
|
case N8VEM_UART_SCR: /* 16550 Scratchpad, implemented so software can detect UART is present */
|
|
n8vem_info->uart_scr = cData;
|
|
break;
|
|
case N8VEM_MPCL_RAM:
|
|
case N8VEM_MPCL_RAM1:
|
|
case N8VEM_MPCL_RAM2:
|
|
case N8VEM_MPCL_RAM3:
|
|
sim_debug(MPCL_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR: MPCL_RAM=0x%02x\n", PCX, cData);
|
|
n8vem_info->mpcl_ram = cData;
|
|
break;
|
|
case N8VEM_MPCL_ROM:
|
|
case N8VEM_MPCL_ROM1:
|
|
case N8VEM_MPCL_ROM2:
|
|
case N8VEM_MPCL_ROM3:
|
|
sim_debug(MPCL_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR: MPCL_ROM=0x%02x\n", PCX, cData);
|
|
n8vem_info->mpcl_rom = cData;
|
|
break;
|
|
default:
|
|
sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: " ADDRESS_FORMAT " WR[0x%02x]=0x%02x: not Implemented.\n", PCX, Addr, cData);
|
|
break;
|
|
}
|
|
|
|
return(0);
|
|
}
|
|
|